| Tue, 02 Jun 2026 22:25:11 -0700 |
Michael Pavone |
Very verbose SH2 debug logging behind an #ifdef guard that was used to locate the mac.w bug
default tip
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| Tue, 02 Jun 2026 22:14:23 -0700 |
Michael Pavone |
Fix stupid regression in mac.w from when I was fixing saturate mode
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| Tue, 02 Jun 2026 22:13:38 -0700 |
Michael Pavone |
Fix size of pointer array for IRL interrupts in SH2 disasssembler
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| Sun, 31 May 2026 22:33:03 -0700 |
Michael Pavone |
Fix SH7095 DMA channel 1 completion interrupts
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| Sun, 31 May 2026 22:33:00 -0700 |
Michael Pavone |
Make sure the PWM control reg is updated before calling maybe_udpate_pwm_dreq
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| Sun, 31 May 2026 21:44:33 -0700 |
Michael Pavone |
Relax SH2 forced sync interval now that the issue the low value was papering over has been fixed
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| Sun, 31 May 2026 18:20:03 -0700 |
Michael Pavone |
Substantial optimization to PWM code. Disable remaining 32X debug printf junk
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| Sun, 31 May 2026 18:19:32 -0700 |
Michael Pavone |
Disable some debug printf junk by default
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| Sun, 31 May 2026 15:08:51 -0700 |
Michael Pavone |
Fix off-by-one in 32X layer compositing
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| Sun, 31 May 2026 12:15:30 -0700 |
Michael Pavone |
Scale H32 MD layer to H40 when 32X is present
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| Sat, 30 May 2026 23:44:28 -0700 |
Michael Pavone |
Add 32x to default extensions. add migration to add it to existing config
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| Sat, 30 May 2026 23:40:47 -0700 |
Michael Pavone |
Try not to leak all the 32X resources
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| Sat, 30 May 2026 23:40:28 -0700 |
Michael Pavone |
Make sure eeprom map is initialized to NULL for the autodetected Acclaim mapper EEPROM on 32X
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| Sat, 30 May 2026 23:00:48 -0700 |
Michael Pavone |
Fix trapa in SH2 core
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| Sat, 30 May 2026 23:00:36 -0700 |
Michael Pavone |
Start SCI transmit when TDRE is cleared if TE is set
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| Sat, 30 May 2026 23:00:12 -0700 |
Michael Pavone |
Handle initial SH2 VBR in ROM rather than SDRAM in disassembler
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| Sat, 30 May 2026 20:29:29 -0700 |
Michael Pavone |
Add a ROM DB entry for Shadow Squadron because it has an ambiguous region header
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| Sat, 30 May 2026 20:28:12 -0700 |
Michael Pavone |
Add a ROM DB entry for Corpse Killer 32X because it has a broken controller routine that doesn't like having a second normal controller plugged in
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| Sat, 30 May 2026 19:48:28 -0700 |
Michael Pavone |
Fix bug in SCD automatic labels in disassembler/debuger
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| Sat, 30 May 2026 17:58:51 -0700 |
Michael Pavone |
Implement Acclaim mapper/I2C EEPROM for 32X games
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| Sat, 30 May 2026 17:06:39 -0700 |
Michael Pavone |
Fix the polarity of PEN
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| Sat, 30 May 2026 16:29:08 -0700 |
Michael Pavone |
Fix jsr (a7) in 68K dynarec
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| Sat, 30 May 2026 00:46:12 -0700 |
Michael Pavone |
Fix 32X cart SRAM access
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| Fri, 29 May 2026 02:11:46 -0700 |
Michael Pavone |
Fix mov @rm+,rn when rm==rn
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| Fri, 29 May 2026 00:11:37 -0700 |
Michael Pavone |
Show both front and back framebuffer in 32X debug layer view
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| Fri, 29 May 2026 00:10:31 -0700 |
Michael Pavone |
Implement debugger step/next/over for SH2 braf/bsrf
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| Fri, 29 May 2026 00:10:02 -0700 |
Michael Pavone |
Fix crash bug in SH2 disassembler
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| Wed, 27 May 2026 21:42:59 -0700 |
Michael Pavone |
Fix some SH7095 DIVU edge cases
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| Tue, 26 May 2026 23:37:39 -0700 |
Michael Pavone |
Set division unit overflow flag in the correct byte of DVCR
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| Tue, 26 May 2026 22:38:07 -0700 |
Michael Pavone |
Respect 32X FM bit
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| Sun, 24 May 2026 23:46:12 -0700 |
Michael Pavone |
only apply accidental change in last commit to SH2 access, not 68K
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| Sun, 24 May 2026 23:34:50 -0700 |
Michael Pavone |
Fix some SH7095 divide cleanup that was missed
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| Sun, 24 May 2026 22:15:34 -0700 |
Michael Pavone |
Add some missing update_sync calls in SH2 core. Fixes Sega logo chant in Space Harrier 32X
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| Sun, 24 May 2026 21:07:10 -0700 |
Michael Pavone |
Enforce tighter sync between SH2s and use a slightly cleaner way for checking main SH2 in memory access handlers
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| Sun, 24 May 2026 20:58:55 -0700 |
Michael Pavone |
Star Wars Arcade depends on one final fill address register increment
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| Sun, 24 May 2026 15:33:45 -0700 |
Michael Pavone |
Fix other SH7095 peripherals to take clock divider into account
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| Sun, 24 May 2026 15:00:54 -0700 |
Michael Pavone |
Fix some issues with WDT implementaiton and ensure predicted next interrupt gets updated when it changes due to SH7095 peripheral activity
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| Sun, 24 May 2026 14:59:53 -0700 |
Michael Pavone |
Fix breakpoints on SH2 cache data array region
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| Sun, 24 May 2026 01:14:09 -0700 |
Michael Pavone |
Fix BRAM loading/saving/auto-formatting for 32XCD games
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| Sun, 24 May 2026 00:51:53 -0700 |
Michael Pavone |
Fix 32X RLE mode
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| Sun, 24 May 2026 00:31:43 -0700 |
Michael Pavone |
Fix 32X cycle deduction
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| Sat, 23 May 2026 23:32:44 -0700 |
Michael Pavone |
Implement WDT interval timer interrupts
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| Sat, 23 May 2026 22:48:27 -0700 |
Michael Pavone |
Fix stupid bug that broke Windows x86-64 build
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| Sat, 23 May 2026 21:51:02 -0700 |
Michael Pavone |
Fix 32X support in 32-bit x86 builds
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| Sat, 23 May 2026 00:42:58 -0700 |
Michael Pavone |
Get 32-bit build to compile again
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| Fri, 22 May 2026 23:27:50 -0700 |
Michael Pavone |
Fix some issues with 32/32 mode of the SH7095 division unit
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| Fri, 22 May 2026 19:45:52 -0700 |
Michael Pavone |
Fix disassembly of gbr-relative mov
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| Fri, 22 May 2026 19:20:41 -0700 |
Michael Pavone |
Fix bug that could prevent 32X VDP fill progress when the SH2 polled VDP regs in a tight loop
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| Fri, 22 May 2026 19:19:59 -0700 |
Michael Pavone |
Generate baked memory handler functions for SH2 interpreter using gen_mem_fun
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| Wed, 20 May 2026 23:25:21 -0700 |
Michael Pavone |
Corpse Killer 32XCD depends on 16-byte burst DMA being in units of 4-bytes so manual is correct and Mars Check Program is wrong
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| Wed, 20 May 2026 21:42:30 -0700 |
Michael Pavone |
Fix accidental reuse of va_list in log_msg
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| Wed, 20 May 2026 20:55:09 -0700 |
Michael Pavone |
Fix disassembly of certain mac.w instructions
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| Wed, 20 May 2026 20:36:08 -0700 |
Michael Pavone |
Fix some issues with mac.w/mac.l saturate operation
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| Wed, 20 May 2026 20:35:47 -0700 |
Michael Pavone |
Fix some issues with access to cache and peripherals from SH2 debugger
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| Tue, 19 May 2026 23:14:50 -0700 |
Michael Pavone |
Fix mov rm,@-rn when rm==rn
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| Tue, 19 May 2026 22:33:09 -0700 |
Michael Pavone |
Toggle FEN during hblank to fix Metal Head
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| Tue, 19 May 2026 22:11:11 -0700 |
Michael Pavone |
Fix mac.w in SH2 core
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| Tue, 19 May 2026 22:10:59 -0700 |
Michael Pavone |
Fix out of bounds access to write_mask arrays and actually set main on the main SH2
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| Tue, 19 May 2026 22:10:24 -0700 |
Michael Pavone |
Use correct clock/counter array for WDT
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| Tue, 19 May 2026 00:02:47 -0700 |
Michael Pavone |
Treat DMAC 16-byte burst mode as 8 word transfers instead of 4 longword transfers in terms of updating TCR
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