repos/blastem: upd78k2_util.c annotate

annotate upd78k2_util.c @ 2716:033d8d4308e3

Fix enough issues in uPD78K/II core so that LaserActive firmware regularly polls front-panel button state

author	Michael Pavone <pavone@retrodev.com>
date	Sat, 12 Jul 2025 22:25:20 -0700
parents	d30e7f605ff8
children	8ce5d1a7ef54

rev	line source
2705 ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	1 #include <string.h>
ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	2
ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	3 void upd78k2_read_8(upd78k2_context *upd)
ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	4 {
ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	5 uint32_t tmp = upd->scratch1;
ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	6 upd->scratch1 = read_byte(upd->scratch1, (void **)upd->mem_pointers, &upd->opts->gen, upd);
ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	7 if (tmp == upd->pc) {
ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	8 printf("uPD78K/II fetch %04X: %02X, AX=%02X%02X BC=%02X%02X DE=%02X%02X HL=%02X%02X SP=%04X\n", tmp, upd->scratch1,
ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	9 upd->main[1], upd->main[0], upd->main[3], upd->main[2], upd->main[5], upd->main[4], upd->main[7], upd->main[6], upd->sp);
ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	10 }
2713 a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	11 //FIXME: cycle count
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	12 upd->cycles += 2 * upd->opts->gen.clock_divider;
2705 ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	13 }
ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	14
ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	15 void upd78k2_write_8(upd78k2_context *upd)
ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	16 {
ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	17 write_byte(upd->scratch2, upd->scratch1, (void **)upd->mem_pointers, &upd->opts->gen, upd);
2713 a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	18 //FIXME: cycle count
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	19 upd->cycles += 2 * upd->opts->gen.clock_divider;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	20 }
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	21
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	22 #define CE0 0x08
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	23 #define CE1 0x08
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	24 #define CIF00 0x0010
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	25 #define CIF01 0x0020
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	26 #define CIF10 0x0040
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	27 #define CIF11 0x0080
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	28
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	29 void upd78k2_update_timer0(upd78k2_context *upd)
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	30 {
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	31 uint32_t diff = (upd->cycles - upd->tm0_cycle) / upd->opts->gen.clock_divider;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	32 upd->tm0_cycle += (diff & ~7) * upd->opts->gen.clock_divider;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	33 diff >>= 3;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	34 if (upd->tmc0 & CE0) {
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	35 uint32_t tmp = upd->tm0 + diff;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	36 //TODO: the rest of the CR00/CR01 stuff
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	37 if (upd->tm0 < upd->cr00 && tmp >= upd->cr00) {
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	38 upd->if0 \|= CIF00;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	39 }
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	40 if (upd->tm0 < upd->cr01 && tmp >= upd->cr01) {
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	41 upd->if0 \|= CIF01;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	42 if (upd->crc0 & 8) {
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	43 //CR01 clear is enabled
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	44 if (upd->cr01) {
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	45 while (tmp >= upd->cr01) {
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	46 tmp -= upd->cr01;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	47 }
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	48 } else {
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	49 tmp = 0;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	50 }
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	51 }
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	52 }
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	53 if (tmp > 0xFFFF) {
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	54 upd->tmc0 \|= 4;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	55 }
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	56 upd->tm0 = tmp;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	57 }
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	58 }
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	59
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	60 uint8_t upd78k2_tm1_scale(upd78k2_context *upd)
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	61 {
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	62 uint8_t scale = upd->prm1 & 3;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	63 if (scale < 2) {
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	64 scale = 2;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	65 }
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	66 scale++;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	67 return scale;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	68 }
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	69
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	70 void upd78k2_update_timer1(upd78k2_context *upd)
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	71 {
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	72 uint8_t scale = upd78k2_tm1_scale(upd);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	73 uint32_t diff = (upd->cycles - upd->tm1_cycle) / upd->opts->gen.clock_divider;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	74 upd->tm1_cycle += (diff & ~((1 << scale) - 1)) * upd->opts->gen.clock_divider;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	75 diff >>= scale;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	76 if (upd->tmc1 & CE1) {
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	77 //tm1 count enabled
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	78 uint32_t tmp = upd->tm1 + diff;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	79 if (upd->tm1 < upd->cr10 && tmp >= upd->cr10) {
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	80 upd->if0 \|= CIF10;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	81 }
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	82 if (upd->tm1 < upd->cr11 && tmp >= upd->cr11) {
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	83 upd->if0 \|= CIF11;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	84 }
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	85 uint8_t do_clr11 = 0;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	86 if (upd->crc1 & 2) {
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	87 //clr10 enabled
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	88 uint8_t do_clr10 = 1;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	89 if ((upd->crc1 & 0xC) == 8) {
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	90 //clr11 also enabled
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	91 if (upd->cr11 < upd->cr10) {
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	92 do_clr10 = 0;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	93 do_clr11 = 1;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	94
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	95 }
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	96 }
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	97 if (do_clr10) {
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	98 if (upd->cr10) {
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	99 while (tmp >= upd->cr10) {
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	100 tmp -= upd->cr10;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	101 }
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	102 } else {
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	103 tmp = 0;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	104 }
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	105 }
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	106 } else if ((upd->crc1 & 0xC) == 8) {
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	107 do_clr11 = 1;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	108 }
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	109 if (do_clr11) {
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	110 if (upd->cr11) {
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	111 while (tmp >= upd->cr11) {
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	112 tmp -= upd->cr11;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	113 }
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	114 } else {
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	115 tmp = 0;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	116 }
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	117 }
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	118 if (tmp > 0xFF) {
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	119 upd->tmc1 \|= 4;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	120 }
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	121 upd->tm1 = tmp;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	122 }
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	123 }
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	124
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	125 #define CMK00 CIF00
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	126 #define CMK01 CIF01
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	127 #define CMK10 CIF10
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	128 #define CMK11 CIF11
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	129
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	130 void upd78k2_calc_next_int(upd78k2_context *upd)
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	131 {
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	132 uint32_t next_int = 0xFFFFFFFF;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	133 if (!upd->int_enable) {
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	134 //maskable interrupts disabled
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	135 //TODO: NMIs
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	136 upd->int_cycle = next_int;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	137 return;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	138 }
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	139 if (upd->if0 & (~upd->mk0)) {
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	140 //unmasked interrupt is pending
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	141 upd->int_cycle = upd->cycles;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	142 return;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	143 }
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	144 uint32_t cycle;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	145 if (!(upd->mk0 & CMK00) && (upd->tmc0 & CE0)) {
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	146 //TODO: account for clear function
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	147 cycle = ((uint16_t)(upd->cr00 - upd->tm0)) << 3;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	148 cycle *= upd->opts->gen.clock_divider;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	149 cycle += upd->tm0_cycle;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	150 if (cycle < next_int) {
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	151 next_int = cycle;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	152 }
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	153 }
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	154 if (!(upd->mk0 & CMK01) && (upd->tmc0 & CE0)) {
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	155 //TODO: account for clear function
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	156 cycle = ((uint16_t)(upd->cr01 - upd->tm0)) << 3;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	157 cycle *= upd->opts->gen.clock_divider;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	158 cycle += upd->tm0_cycle;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	159 if (cycle < next_int) {
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	160 next_int = cycle;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	161 }
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	162 }
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	163 uint8_t scale = upd78k2_tm1_scale(upd);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	164 if (!(upd->mk0 & CMK10) && (upd->tmc1 & CE1)) {
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	165 //TODO: account for clear function
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	166 cycle = ((uint8_t)(upd->cr10 - upd->tm1)) << scale;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	167 cycle *= upd->opts->gen.clock_divider;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	168 cycle += upd->tm1_cycle;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	169 if (cycle < next_int) {
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	170 next_int = cycle;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	171 }
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	172 }
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	173 if (!(upd->mk0 & CMK11) && (upd->tmc1 & CE1)) {
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	174 //TODO: account for clear function
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	175 cycle = ((uint8_t)(upd->cr11 - upd->tm1)) << scale;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	176 cycle *= upd->opts->gen.clock_divider;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	177 cycle += upd->tm1_cycle;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	178 if (cycle < next_int) {
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	179 next_int = cycle;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	180 }
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	181 }
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	182 if (next_int != upd->int_cycle) {
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	183 printf("UPD78K/II int cycle: %u, cur cycle %u\n", next_int, upd->cycles);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	184 }
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	185 upd->int_cycle = next_int;
2705 ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	186 }
ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	187
ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	188 uint8_t upd78237_sfr_read(uint32_t address, void *context)
ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	189 {
ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	190 upd78k2_context *upd = context;
ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	191 switch (address)
ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	192 {
2716 033d8d4308e3 Fix enough issues in uPD78K/II core so that LaserActive firmware regularly polls front-panel button state Michael Pavone <pavone@retrodev.com> parents: 2714 diff changeset	193 case 0x00:
033d8d4308e3 Fix enough issues in uPD78K/II core so that LaserActive firmware regularly polls front-panel button state Michael Pavone <pavone@retrodev.com> parents: 2714 diff changeset	194 case 0x04:
033d8d4308e3 Fix enough issues in uPD78K/II core so that LaserActive firmware regularly polls front-panel button state Michael Pavone <pavone@retrodev.com> parents: 2714 diff changeset	195 case 0x05:
033d8d4308e3 Fix enough issues in uPD78K/II core so that LaserActive firmware regularly polls front-panel button state Michael Pavone <pavone@retrodev.com> parents: 2714 diff changeset	196 case 0x06:
033d8d4308e3 Fix enough issues in uPD78K/II core so that LaserActive firmware regularly polls front-panel button state Michael Pavone <pavone@retrodev.com> parents: 2714 diff changeset	197 return upd->port_data[address];
033d8d4308e3 Fix enough issues in uPD78K/II core so that LaserActive firmware regularly polls front-panel button state Michael Pavone <pavone@retrodev.com> parents: 2714 diff changeset	198 case 0x02:
033d8d4308e3 Fix enough issues in uPD78K/II core so that LaserActive firmware regularly polls front-panel button state Michael Pavone <pavone@retrodev.com> parents: 2714 diff changeset	199 case 0x07:
033d8d4308e3 Fix enough issues in uPD78K/II core so that LaserActive firmware regularly polls front-panel button state Michael Pavone <pavone@retrodev.com> parents: 2714 diff changeset	200 //input only
033d8d4308e3 Fix enough issues in uPD78K/II core so that LaserActive firmware regularly polls front-panel button state Michael Pavone <pavone@retrodev.com> parents: 2714 diff changeset	201 if (upd->io_read) {
033d8d4308e3 Fix enough issues in uPD78K/II core so that LaserActive firmware regularly polls front-panel button state Michael Pavone <pavone@retrodev.com> parents: 2714 diff changeset	202 upd->io_read(upd, address);
033d8d4308e3 Fix enough issues in uPD78K/II core so that LaserActive firmware regularly polls front-panel button state Michael Pavone <pavone@retrodev.com> parents: 2714 diff changeset	203 }
033d8d4308e3 Fix enough issues in uPD78K/II core so that LaserActive firmware regularly polls front-panel button state Michael Pavone <pavone@retrodev.com> parents: 2714 diff changeset	204 return upd->port_input[address];
033d8d4308e3 Fix enough issues in uPD78K/II core so that LaserActive firmware regularly polls front-panel button state Michael Pavone <pavone@retrodev.com> parents: 2714 diff changeset	205 break;
033d8d4308e3 Fix enough issues in uPD78K/II core so that LaserActive firmware regularly polls front-panel button state Michael Pavone <pavone@retrodev.com> parents: 2714 diff changeset	206 case 0x01:
033d8d4308e3 Fix enough issues in uPD78K/II core so that LaserActive firmware regularly polls front-panel button state Michael Pavone <pavone@retrodev.com> parents: 2714 diff changeset	207 case 0x03:
033d8d4308e3 Fix enough issues in uPD78K/II core so that LaserActive firmware regularly polls front-panel button state Michael Pavone <pavone@retrodev.com> parents: 2714 diff changeset	208 if (upd->io_read) {
033d8d4308e3 Fix enough issues in uPD78K/II core so that LaserActive firmware regularly polls front-panel button state Michael Pavone <pavone@retrodev.com> parents: 2714 diff changeset	209 upd->io_read(upd, address);
033d8d4308e3 Fix enough issues in uPD78K/II core so that LaserActive firmware regularly polls front-panel button state Michael Pavone <pavone@retrodev.com> parents: 2714 diff changeset	210 }
033d8d4308e3 Fix enough issues in uPD78K/II core so that LaserActive firmware regularly polls front-panel button state Michael Pavone <pavone@retrodev.com> parents: 2714 diff changeset	211 return (upd->port_input[address] & upd->port_mode[address]) \| (upd->port_data[address] & ~upd->port_mode[address]);
2714 d30e7f605ff8 Get uPD78k/II timer interrupts actually working and implement instructions needed for them to run to completion Michael Pavone <pavone@retrodev.com> parents: 2713 diff changeset	212 case 0x10:
d30e7f605ff8 Get uPD78k/II timer interrupts actually working and implement instructions needed for them to run to completion Michael Pavone <pavone@retrodev.com> parents: 2713 diff changeset	213 return upd->cr00;
d30e7f605ff8 Get uPD78k/II timer interrupts actually working and implement instructions needed for them to run to completion Michael Pavone <pavone@retrodev.com> parents: 2713 diff changeset	214 case 0x11:
d30e7f605ff8 Get uPD78k/II timer interrupts actually working and implement instructions needed for them to run to completion Michael Pavone <pavone@retrodev.com> parents: 2713 diff changeset	215 return upd->cr00 >> 8;
d30e7f605ff8 Get uPD78k/II timer interrupts actually working and implement instructions needed for them to run to completion Michael Pavone <pavone@retrodev.com> parents: 2713 diff changeset	216 case 0x12:
d30e7f605ff8 Get uPD78k/II timer interrupts actually working and implement instructions needed for them to run to completion Michael Pavone <pavone@retrodev.com> parents: 2713 diff changeset	217 return upd->cr01;
d30e7f605ff8 Get uPD78k/II timer interrupts actually working and implement instructions needed for them to run to completion Michael Pavone <pavone@retrodev.com> parents: 2713 diff changeset	218 case 0x13:
d30e7f605ff8 Get uPD78k/II timer interrupts actually working and implement instructions needed for them to run to completion Michael Pavone <pavone@retrodev.com> parents: 2713 diff changeset	219 return upd->cr01 >> 8;
d30e7f605ff8 Get uPD78k/II timer interrupts actually working and implement instructions needed for them to run to completion Michael Pavone <pavone@retrodev.com> parents: 2713 diff changeset	220 case 0x14:
d30e7f605ff8 Get uPD78k/II timer interrupts actually working and implement instructions needed for them to run to completion Michael Pavone <pavone@retrodev.com> parents: 2713 diff changeset	221 return upd->cr10;
d30e7f605ff8 Get uPD78k/II timer interrupts actually working and implement instructions needed for them to run to completion Michael Pavone <pavone@retrodev.com> parents: 2713 diff changeset	222 case 0x1C:
d30e7f605ff8 Get uPD78k/II timer interrupts actually working and implement instructions needed for them to run to completion Michael Pavone <pavone@retrodev.com> parents: 2713 diff changeset	223 return upd->cr11;
2705 ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	224 case 0x21:
ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	225 case 0x26:
ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	226 return upd->port_mode[address & 0x7];
2713 a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	227 case 0x5D:
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	228 upd78k2_update_timer0(upd);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	229 printf("TMC0 Read: %02X\n", upd->tmc0);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	230 return upd->tmc0;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	231 case 0x5F:
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	232 upd78k2_update_timer1(upd);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	233 printf("TMC1 Read: %02X\n", upd->tmc1);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	234 return upd->tmc1;
2705 ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	235 case 0xC4:
ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	236 return upd->mm;
2706 0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop Michael Pavone <pavone@retrodev.com> parents: 2705 diff changeset	237 case 0xE0:
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop Michael Pavone <pavone@retrodev.com> parents: 2705 diff changeset	238 return upd->if0;
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop Michael Pavone <pavone@retrodev.com> parents: 2705 diff changeset	239 case 0xE1:
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop Michael Pavone <pavone@retrodev.com> parents: 2705 diff changeset	240 return upd->if0 >> 8;
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop Michael Pavone <pavone@retrodev.com> parents: 2705 diff changeset	241 case 0xE4:
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop Michael Pavone <pavone@retrodev.com> parents: 2705 diff changeset	242 return upd->mk0;
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop Michael Pavone <pavone@retrodev.com> parents: 2705 diff changeset	243 case 0xE5:
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop Michael Pavone <pavone@retrodev.com> parents: 2705 diff changeset	244 return upd->mk0 >> 8;
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop Michael Pavone <pavone@retrodev.com> parents: 2705 diff changeset	245 case 0xE8:
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop Michael Pavone <pavone@retrodev.com> parents: 2705 diff changeset	246 return upd->pr0;
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop Michael Pavone <pavone@retrodev.com> parents: 2705 diff changeset	247 case 0xE9:
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop Michael Pavone <pavone@retrodev.com> parents: 2705 diff changeset	248 return upd->pr0 >> 8;
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop Michael Pavone <pavone@retrodev.com> parents: 2705 diff changeset	249 case 0xEC:
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop Michael Pavone <pavone@retrodev.com> parents: 2705 diff changeset	250 return upd->ism0;
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop Michael Pavone <pavone@retrodev.com> parents: 2705 diff changeset	251 case 0xED:
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop Michael Pavone <pavone@retrodev.com> parents: 2705 diff changeset	252 return upd->ism0 >> 8;
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop Michael Pavone <pavone@retrodev.com> parents: 2705 diff changeset	253 case 0xF4:
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop Michael Pavone <pavone@retrodev.com> parents: 2705 diff changeset	254 return upd->intm0;
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop Michael Pavone <pavone@retrodev.com> parents: 2705 diff changeset	255 case 0xF5:
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop Michael Pavone <pavone@retrodev.com> parents: 2705 diff changeset	256 return upd->intm1;
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop Michael Pavone <pavone@retrodev.com> parents: 2705 diff changeset	257 case 0xF8:
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop Michael Pavone <pavone@retrodev.com> parents: 2705 diff changeset	258 return upd->ist;
2705 ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	259 default:
ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	260 fprintf(stderr, "Unhandled uPD78237 SFR read %02X\n", address);
ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	261 return 0xFF;
ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	262 }
ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	263 }
ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	264
ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	265 void upd78237_sfr_write(uint32_t address, void context, uint8_t value)
ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	266 {
ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	267 upd78k2_context *upd = context;
ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	268 if (address < 8 && address != 2 && address != 7) {
ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	269 upd->port_data[address] = value;
ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	270 } else {
ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	271 switch (address)
ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	272 {
2713 a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	273 case 0x00:
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	274 case 0x01:
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	275 case 0x03:
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	276 case 0x04:
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	277 case 0x05:
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	278 case 0x06:
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	279 printf("P%X: %02X\n", address & 7, value);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	280 upd->port_data[address & 7] = value;
2716 033d8d4308e3 Fix enough issues in uPD78K/II core so that LaserActive firmware regularly polls front-panel button state Michael Pavone <pavone@retrodev.com> parents: 2714 diff changeset	281 if (upd->io_write) {
033d8d4308e3 Fix enough issues in uPD78K/II core so that LaserActive firmware regularly polls front-panel button state Michael Pavone <pavone@retrodev.com> parents: 2714 diff changeset	282 upd->io_write(upd, address);
033d8d4308e3 Fix enough issues in uPD78K/II core so that LaserActive firmware regularly polls front-panel button state Michael Pavone <pavone@retrodev.com> parents: 2714 diff changeset	283 }
2713 a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	284 break;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	285 case 0x10:
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	286 upd78k2_update_timer0(upd);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	287 upd->cr00 &= 0xFF00;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	288 upd->cr00 \|= value;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	289 printf("CR00: %04X\n", upd->cr00);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	290 upd78k2_calc_next_int(upd);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	291 break;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	292 case 0x11:
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	293 upd78k2_update_timer0(upd);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	294 upd->cr00 &= 0xFF;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	295 upd->cr00 \|= value << 8;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	296 printf("CR00: %04X\n", upd->cr00);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	297 upd78k2_calc_next_int(upd);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	298 break;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	299 case 0x12:
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	300 upd78k2_update_timer0(upd);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	301 upd->cr01 &= 0xFF00;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	302 upd->cr01 \|= value;
2714 d30e7f605ff8 Get uPD78k/II timer interrupts actually working and implement instructions needed for them to run to completion Michael Pavone <pavone@retrodev.com> parents: 2713 diff changeset	303 printf("CR01: %04X\n", upd->cr01);
2713 a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	304 upd78k2_calc_next_int(upd);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	305 break;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	306 case 0x13:
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	307 upd78k2_update_timer0(upd);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	308 upd->cr01 &= 0xFF;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	309 upd->cr01 \|= value << 8;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	310 printf("CR01: %04X\n", upd->cr01);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	311 upd78k2_calc_next_int(upd);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	312 break;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	313 case 0x14:
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	314 upd78k2_update_timer1(upd);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	315 upd->cr10 = value;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	316 printf("CR10: %02X\n", value);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	317 upd78k2_calc_next_int(upd);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	318 break;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	319 case 0x1C:
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	320 upd78k2_update_timer1(upd);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	321 upd->cr11 = value;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	322 printf("CR11: %02X\n", value);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	323 upd78k2_calc_next_int(upd);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	324 break;
2705 ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	325 case 0x20:
2713 a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	326 case 0x21:
2705 ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	327 case 0x23:
ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	328 case 0x25:
ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	329 case 0x26:
2713 a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	330 printf("PM%X: %02X\n", address & 0x7, value);
2705 ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	331 upd->port_mode[address & 7] = value;
ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	332 break;
2713 a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	333 case 0x30:
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	334 upd78k2_update_timer0(upd);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	335 upd->crc0 = value;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	336 printf("CRC0 CLR01: %X, MOD: %X, Other: %X\n", value >> 3 & 1, value >> 6, value & 0x37);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	337 upd78k2_calc_next_int(upd);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	338 break;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	339 case 0x32:
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	340 upd78k2_update_timer1(upd);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	341 upd->crc1 = value;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	342 printf("CRC1 CLR11: %X, CM: %X, CLR10: %X\n", value >> 3 & 1, value >> 2 & 1, value >> 1 & 1);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	343 upd78k2_calc_next_int(upd);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	344 break;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	345 case 0x40:
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	346 upd->puo = value;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	347 printf("PUO: %02X\n", value);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	348 break;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	349 case 0x43:
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	350 upd->pmc3 = value;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	351 printf("PMC3 TO: %X, SO: %X, SCK: %X, TxD: %X, RxD: %X\n", value >> 4, value >> 3 & 1, value >> 2 & 1, value >> 1 & 1, value & 1);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	352 break;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	353 case 0x5D:
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	354 upd78k2_update_timer0(upd);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	355 upd->tmc0 = value;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	356 printf("TMC0 CE0: %X, OVF0: %X - TM3 CE3: %X\n", value >> 3 & 1, value >> 2 & 1, value >> 7 & 1);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	357 if (!(value & 0x8)) {
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	358 upd->tm0 = 0;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	359 }
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	360 upd78k2_calc_next_int(upd);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	361 break;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	362 case 0x5E:
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	363 upd78k2_update_timer1(upd);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	364 upd->prm1 = value;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	365 printf("PRM1: %02X\n", value);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	366 upd78k2_calc_next_int(upd);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	367 break;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	368 case 0x5F:
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	369 upd78k2_update_timer1(upd);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	370 upd->tmc1 = value;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	371 printf("TMC1 CE2: %X, OVF2: %X, CMD2: %X, CE1: %X, OVF1: %X\n", value >> 7, value >> 6 & 1, value >> 5 & 1, value >> 3 & 1, value >> 2 & 1);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	372 upd78k2_calc_next_int(upd);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	373 break;
2705 ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	374 case 0xC4:
ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	375 upd->mm = value;
ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	376 break;
2706 0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop Michael Pavone <pavone@retrodev.com> parents: 2705 diff changeset	377 case 0xE0:
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop Michael Pavone <pavone@retrodev.com> parents: 2705 diff changeset	378 upd->if0 &= 0xFF00;
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop Michael Pavone <pavone@retrodev.com> parents: 2705 diff changeset	379 upd->if0 \|= value;
2713 a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	380 upd78k2_calc_next_int(upd);
2706 0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop Michael Pavone <pavone@retrodev.com> parents: 2705 diff changeset	381 break;
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop Michael Pavone <pavone@retrodev.com> parents: 2705 diff changeset	382 case 0xE1:
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop Michael Pavone <pavone@retrodev.com> parents: 2705 diff changeset	383 upd->if0 &= 0xFF;
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop Michael Pavone <pavone@retrodev.com> parents: 2705 diff changeset	384 upd->if0 \|= value << 8;
2713 a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	385 upd78k2_calc_next_int(upd);
2706 0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop Michael Pavone <pavone@retrodev.com> parents: 2705 diff changeset	386 break;
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop Michael Pavone <pavone@retrodev.com> parents: 2705 diff changeset	387 case 0xE4:
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop Michael Pavone <pavone@retrodev.com> parents: 2705 diff changeset	388 upd->mk0 &= 0xFF00;
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop Michael Pavone <pavone@retrodev.com> parents: 2705 diff changeset	389 upd->mk0 \|= value;
2713 a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	390 printf("MK0: %04X (low: %02X)\n", upd->mk0, value);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	391 upd78k2_sync_cycle(upd, upd->sync_cycle);
2706 0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop Michael Pavone <pavone@retrodev.com> parents: 2705 diff changeset	392 break;
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop Michael Pavone <pavone@retrodev.com> parents: 2705 diff changeset	393 case 0xE5:
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop Michael Pavone <pavone@retrodev.com> parents: 2705 diff changeset	394 upd->mk0 &= 0xFF;
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop Michael Pavone <pavone@retrodev.com> parents: 2705 diff changeset	395 upd->mk0 \|= value << 8;
2713 a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	396 printf("MK0: %04X (hi: %02X)\n", upd->mk0, value);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	397 upd78k2_sync_cycle(upd, upd->sync_cycle);
2706 0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop Michael Pavone <pavone@retrodev.com> parents: 2705 diff changeset	398 break;
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop Michael Pavone <pavone@retrodev.com> parents: 2705 diff changeset	399 case 0xE8:
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop Michael Pavone <pavone@retrodev.com> parents: 2705 diff changeset	400 upd->pr0 &= 0xFF00;
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop Michael Pavone <pavone@retrodev.com> parents: 2705 diff changeset	401 upd->pr0 \|= value;
2713 a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	402 printf("PR0: %04X\n", upd->pr0);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	403 upd78k2_sync_cycle(upd, upd->sync_cycle);
2706 0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop Michael Pavone <pavone@retrodev.com> parents: 2705 diff changeset	404 break;
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop Michael Pavone <pavone@retrodev.com> parents: 2705 diff changeset	405 case 0xE9:
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop Michael Pavone <pavone@retrodev.com> parents: 2705 diff changeset	406 upd->pr0 &= 0xFF;
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop Michael Pavone <pavone@retrodev.com> parents: 2705 diff changeset	407 upd->pr0 \|= value << 8;
2713 a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	408 printf("PR0: %04X\n", upd->pr0);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	409 upd78k2_sync_cycle(upd, upd->sync_cycle);
2706 0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop Michael Pavone <pavone@retrodev.com> parents: 2705 diff changeset	410 break;
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop Michael Pavone <pavone@retrodev.com> parents: 2705 diff changeset	411 case 0xEC:
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop Michael Pavone <pavone@retrodev.com> parents: 2705 diff changeset	412 upd->ism0 &= 0xFF00;
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop Michael Pavone <pavone@retrodev.com> parents: 2705 diff changeset	413 upd->ism0 \|= value;
2713 a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	414 printf("ISM0: %04X\n", upd->ism0);
2706 0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop Michael Pavone <pavone@retrodev.com> parents: 2705 diff changeset	415 break;
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop Michael Pavone <pavone@retrodev.com> parents: 2705 diff changeset	416 case 0xED:
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop Michael Pavone <pavone@retrodev.com> parents: 2705 diff changeset	417 upd->ism0 &= 0xFF;
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop Michael Pavone <pavone@retrodev.com> parents: 2705 diff changeset	418 upd->ism0 \|= value << 8;
2713 a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	419 printf("ISM0: %04X\n", upd->ism0);
2706 0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop Michael Pavone <pavone@retrodev.com> parents: 2705 diff changeset	420 break;
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop Michael Pavone <pavone@retrodev.com> parents: 2705 diff changeset	421 case 0xF4:
2716 033d8d4308e3 Fix enough issues in uPD78K/II core so that LaserActive firmware regularly polls front-panel button state Michael Pavone <pavone@retrodev.com> parents: 2714 diff changeset	422 printf("INTM0: %02X\n", value);
2706 0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop Michael Pavone <pavone@retrodev.com> parents: 2705 diff changeset	423 upd->intm0 = value;
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop Michael Pavone <pavone@retrodev.com> parents: 2705 diff changeset	424 break;
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop Michael Pavone <pavone@retrodev.com> parents: 2705 diff changeset	425 case 0xF5:
2716 033d8d4308e3 Fix enough issues in uPD78K/II core so that LaserActive firmware regularly polls front-panel button state Michael Pavone <pavone@retrodev.com> parents: 2714 diff changeset	426 printf("INTM1: %02X\n", value);
2706 0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop Michael Pavone <pavone@retrodev.com> parents: 2705 diff changeset	427 upd->intm1 = value;
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop Michael Pavone <pavone@retrodev.com> parents: 2705 diff changeset	428 break;
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop Michael Pavone <pavone@retrodev.com> parents: 2705 diff changeset	429 case 0xF8:
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop Michael Pavone <pavone@retrodev.com> parents: 2705 diff changeset	430 upd->ist = value;
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop Michael Pavone <pavone@retrodev.com> parents: 2705 diff changeset	431 break;
2705 ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	432 default:
ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	433 fprintf(stderr, "Unhandled uPD78237 SFR write %02X: %02X\n", address, value);
ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	434 break;
ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	435 }
ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	436 }
ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	437 return context;
ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	438 }
ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	439
ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	440 void init_upd78k2_opts(upd78k2_options opts, memmap_chunk const chunks, uint32_t num_chunks)
ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	441 {
ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	442 memset(opts, 0, sizeof(*opts));
ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	443 opts->gen.memmap = chunks;
ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	444 opts->gen.memmap_chunks = num_chunks;
ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	445 opts->gen.address_mask = 0xFFFFF;
ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	446 opts->gen.max_address = 0xFFFFF;
2713 a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	447 opts->gen.clock_divider = 1;
2705 ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	448 }
ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	449
ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	450 upd78k2_context init_upd78k2_context(upd78k2_options opts)
ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	451 {
ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	452 upd78k2_context *context = calloc(1, sizeof(upd78k2_context));
ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	453 context->opts = opts;
2713 a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	454 memset(context->port_mode, 0xFF, sizeof(context->port_mode));
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	455 context->crc0 = 0x10;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	456 context->mm = 0x20;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	457 context->mk0 = 0xFFFF;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	458 context->pr0 = 0xFFFF;
2705 ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	459 return context;
ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	460 }
ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	461
2706 0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop Michael Pavone <pavone@retrodev.com> parents: 2705 diff changeset	462 void upd78k2_sync_cycle(upd78k2_context *upd, uint32_t target_cycle)
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop Michael Pavone <pavone@retrodev.com> parents: 2705 diff changeset	463 {
2713 a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	464 upd78k2_update_timer0(upd);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	465 upd78k2_update_timer1(upd);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	466 upd->sync_cycle = target_cycle;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	467 upd78k2_calc_next_int(upd);
2706 0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop Michael Pavone <pavone@retrodev.com> parents: 2705 diff changeset	468 }
2713 a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	469
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	470 void upd78k2_calc_vector(upd78k2_context *upd)
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	471 {
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	472 uint32_t pending_enabled = upd->scratch1;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	473 uint32_t vector = 0x6;
2714 d30e7f605ff8 Get uPD78k/II timer interrupts actually working and implement instructions needed for them to run to completion Michael Pavone <pavone@retrodev.com> parents: 2713 diff changeset	474 uint32_t bit = 1;
2713 a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	475 while (pending_enabled)
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	476 {
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	477 if (pending_enabled & 1) {
2714 d30e7f605ff8 Get uPD78k/II timer interrupts actually working and implement instructions needed for them to run to completion Michael Pavone <pavone@retrodev.com> parents: 2713 diff changeset	478 upd->if0 &= ~bit;
2713 a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	479 upd->scratch1 = vector;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	480 return;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	481 }
2714 d30e7f605ff8 Get uPD78k/II timer interrupts actually working and implement instructions needed for them to run to completion Michael Pavone <pavone@retrodev.com> parents: 2713 diff changeset	482 bit <<= 1;
2713 a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	483 pending_enabled >>= 1;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	484 vector += 2;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	485 if (vector == 0xE) {
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	486 vector = 0x14;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	487 } else if (vector == 0x20) {
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	488 vector = 0xE;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	489 } else if (vector == 0x14) {
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	490 vector = 0x20;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	491 }
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	492 }
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	493 fatal_error("upd78k2_calc_vector: %X\n", upd->scratch1);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	494 }

Mercurial > repos > blastem

annotate upd78k2_util.c @ 2716:033d8d4308e3