Mercurial > repos > blastem
annotate z80_to_x86.c @ 651:103d5cabbe14
Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown.
author | Michael Pavone <pavone@retrodev.com> |
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date | Tue, 16 Dec 2014 01:10:54 -0800 |
parents | 2d7e84ae818c |
children | f822d9216968 |
rev | line source |
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1 /* |
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2 Copyright 2013 Michael Pavone |
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The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
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3 This file is part of BlastEm. |
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4 BlastEm is free software distributed under the terms of the GNU General Public License version 3 or greater. See COPYING for full license text. |
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5 */ |
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6 #include "z80inst.h" |
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7 #include "z80_to_x86.h" |
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8 #include "gen_x86.h" |
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9 #include "mem.h" |
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10 #include <stdio.h> |
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11 #include <stdlib.h> |
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12 #include <stddef.h> |
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13 #include <string.h> |
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14 |
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15 #define MODE_UNUSED (MODE_IMMED-1) |
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16 |
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17 #define ZCYCLES RBP |
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18 #define ZLIMIT RDI |
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19 #define SCRATCH1 R13 |
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20 #define SCRATCH2 R14 |
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21 #define CONTEXT RSI |
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22 |
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23 //#define DO_DEBUG_PRINT |
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24 |
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25 #ifdef DO_DEBUG_PRINT |
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26 #define dprintf printf |
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27 #else |
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28 #define dprintf |
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29 #endif |
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30 |
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31 void z80_read_byte(); |
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32 void z80_read_word(); |
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33 void z80_write_byte(); |
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34 void z80_write_word_highfirst(); |
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35 void z80_write_word_lowfirst(); |
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36 void z80_save_context(); |
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37 void z80_native_addr(); |
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38 void z80_do_sync(); |
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39 void z80_handle_cycle_limit_int(); |
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40 void z80_retrans_stub(); |
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41 void z80_io_read(); |
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42 void z80_io_write(); |
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43 void z80_halt(); |
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44 void z80_save_context(); |
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45 void z80_load_context(); |
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46 |
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47 uint8_t * zbreakpoint_patch(z80_context * context, uint16_t address, uint8_t * native); |
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48 |
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49 uint8_t z80_size(z80inst * inst) |
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50 { |
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51 uint8_t reg = (inst->reg & 0x1F); |
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52 if (reg != Z80_UNUSED && reg != Z80_USE_IMMED) { |
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53 return reg < Z80_BC ? SZ_B : SZ_W; |
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54 } |
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55 //TODO: Handle any necessary special cases |
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56 return SZ_B; |
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57 } |
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58 |
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59 uint8_t * zcycles(uint8_t * dst, uint32_t num_cycles) |
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60 { |
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61 return add_ir(dst, num_cycles, ZCYCLES, SZ_D); |
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62 } |
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63 |
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64 uint8_t * z80_check_cycles_int(uint8_t * dst, uint16_t address) |
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65 { |
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66 dst = cmp_rr(dst, ZCYCLES, ZLIMIT, SZ_D); |
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67 uint8_t * jmp_off = dst+1; |
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68 dst = jcc(dst, CC_NC, dst + 7); |
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69 dst = mov_ir(dst, address, SCRATCH1, SZ_W); |
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70 dst = call(dst, (uint8_t *)z80_handle_cycle_limit_int); |
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71 *jmp_off = dst - (jmp_off+1); |
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72 return dst; |
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73 } |
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74 |
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75 uint8_t * translate_z80_reg(z80inst * inst, x86_ea * ea, uint8_t * dst, x86_z80_options * opts) |
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76 { |
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77 if (inst->reg == Z80_USE_IMMED) { |
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78 ea->mode = MODE_IMMED; |
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79 ea->disp = inst->immed; |
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80 } else if ((inst->reg & 0x1F) == Z80_UNUSED) { |
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81 ea->mode = MODE_UNUSED; |
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82 } else { |
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83 ea->mode = MODE_REG_DIRECT; |
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84 if (inst->reg == Z80_IYH) { |
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85 if ((inst->addr_mode & 0x1F) == Z80_REG && inst->ea_reg == Z80_IYL) { |
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86 dst = mov_rr(dst, opts->regs[Z80_IY], SCRATCH1, SZ_W); |
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87 dst = ror_ir(dst, 8, SCRATCH1, SZ_W); |
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88 ea->base = SCRATCH1; |
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89 } else { |
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90 ea->base = opts->regs[Z80_IYL]; |
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91 dst = ror_ir(dst, 8, opts->regs[Z80_IY], SZ_W); |
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92 } |
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93 } else if(opts->regs[inst->reg] >= 0) { |
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94 ea->base = opts->regs[inst->reg]; |
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95 if (ea->base >= AH && ea->base <= BH) { |
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96 if ((inst->addr_mode & 0x1F) == Z80_REG) { |
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97 uint8_t other_reg = opts->regs[inst->ea_reg]; |
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98 if (other_reg >= R8 || (other_reg >= RSP && other_reg <= RDI)) { |
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99 //we can't mix an *H reg with a register that requires the REX prefix |
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100 ea->base = opts->regs[z80_low_reg(inst->reg)]; |
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101 dst = ror_ir(dst, 8, ea->base, SZ_W); |
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102 } |
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103 } else if((inst->addr_mode & 0x1F) != Z80_UNUSED && (inst->addr_mode & 0x1F) != Z80_IMMED) { |
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104 //temp regs require REX prefix too |
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105 ea->base = opts->regs[z80_low_reg(inst->reg)]; |
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106 dst = ror_ir(dst, 8, ea->base, SZ_W); |
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107 } |
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108 } |
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109 } else { |
262
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110 ea->mode = MODE_REG_DISPLACE8; |
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111 ea->base = CONTEXT; |
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112 ea->disp = offsetof(z80_context, regs) + inst->reg; |
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113 } |
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114 } |
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115 return dst; |
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116 } |
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117 |
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118 uint8_t * z80_save_reg(uint8_t * dst, z80inst * inst, x86_z80_options * opts) |
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119 { |
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120 if (inst->reg == Z80_IYH) { |
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121 if ((inst->addr_mode & 0x1F) == Z80_REG && inst->ea_reg == Z80_IYL) { |
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122 dst = ror_ir(dst, 8, opts->regs[Z80_IY], SZ_W); |
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123 dst = mov_rr(dst, SCRATCH1, opts->regs[Z80_IYL], SZ_B); |
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124 dst = ror_ir(dst, 8, opts->regs[Z80_IY], SZ_W); |
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125 } else { |
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126 dst = ror_ir(dst, 8, opts->regs[Z80_IY], SZ_W); |
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127 } |
268
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128 } else if (opts->regs[inst->reg] >= AH && opts->regs[inst->reg] <= BH) { |
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129 if ((inst->addr_mode & 0x1F) == Z80_REG) { |
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130 uint8_t other_reg = opts->regs[inst->ea_reg]; |
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131 if (other_reg >= R8 || (other_reg >= RSP && other_reg <= RDI)) { |
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132 //we can't mix an *H reg with a register that requires the REX prefix |
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133 dst = ror_ir(dst, 8, opts->regs[z80_low_reg(inst->reg)], SZ_W); |
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134 } |
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135 } else if((inst->addr_mode & 0x1F) != Z80_UNUSED && (inst->addr_mode & 0x1F) != Z80_IMMED) { |
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136 //temp regs require REX prefix too |
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137 dst = ror_ir(dst, 8, opts->regs[z80_low_reg(inst->reg)], SZ_W); |
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138 } |
213
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139 } |
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140 return dst; |
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141 } |
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142 |
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143 uint8_t * translate_z80_ea(z80inst * inst, x86_ea * ea, uint8_t * dst, x86_z80_options * opts, uint8_t read, uint8_t modify) |
213
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144 { |
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145 uint8_t size, reg, areg; |
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146 ea->mode = MODE_REG_DIRECT; |
213
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147 areg = read ? SCRATCH1 : SCRATCH2; |
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148 switch(inst->addr_mode & 0x1F) |
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149 { |
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150 case Z80_REG: |
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151 if (inst->ea_reg == Z80_IYH) { |
312
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152 if (inst->reg == Z80_IYL) { |
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153 dst = mov_rr(dst, opts->regs[Z80_IY], SCRATCH1, SZ_W); |
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154 dst = ror_ir(dst, 8, SCRATCH1, SZ_W); |
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155 ea->base = SCRATCH1; |
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156 } else { |
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157 ea->base = opts->regs[Z80_IYL]; |
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158 dst = ror_ir(dst, 8, opts->regs[Z80_IY], SZ_W); |
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159 } |
651
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160 } else if(opts->regs[inst->ea_reg] >= 0) { |
213
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161 ea->base = opts->regs[inst->ea_reg]; |
267
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162 if (ea->base >= AH && ea->base <= BH && inst->reg != Z80_UNUSED && inst->reg != Z80_USE_IMMED) { |
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163 uint8_t other_reg = opts->regs[inst->reg]; |
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164 if (other_reg >= R8 || (other_reg >= RSP && other_reg <= RDI)) { |
267
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165 //we can't mix an *H reg with a register that requires the REX prefix |
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166 ea->base = opts->regs[z80_low_reg(inst->ea_reg)]; |
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167 dst = ror_ir(dst, 8, ea->base, SZ_W); |
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168 } |
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169 } |
651
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170 } else { |
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171 ea->mode = MODE_REG_DISPLACE8; |
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172 ea->base = CONTEXT; |
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173 ea->disp = offsetof(z80_context, regs) + inst->ea_reg; |
213
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174 } |
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175 break; |
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176 case Z80_REG_INDIRECT: |
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177 dst = mov_rr(dst, opts->regs[inst->ea_reg], areg, SZ_W); |
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178 size = z80_size(inst); |
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179 if (read) { |
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180 if (modify) { |
277
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181 //dst = push_r(dst, SCRATCH1); |
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182 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, offsetof(z80_context, scratch1), SZ_W); |
213
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183 } |
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184 if (size == SZ_B) { |
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185 dst = call(dst, (uint8_t *)z80_read_byte); |
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186 } else { |
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187 dst = call(dst, (uint8_t *)z80_read_word); |
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188 } |
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189 if (modify) { |
277
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190 //dst = pop_r(dst, SCRATCH2); |
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191 dst = mov_rdisp8r(dst, CONTEXT, offsetof(z80_context, scratch1), SCRATCH2, SZ_W); |
213
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192 } |
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193 } |
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194 ea->base = SCRATCH1; |
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195 break; |
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196 case Z80_IMMED: |
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197 ea->mode = MODE_IMMED; |
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198 ea->disp = inst->immed; |
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199 break; |
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200 case Z80_IMMED_INDIRECT: |
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201 dst = mov_ir(dst, inst->immed, areg, SZ_W); |
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202 size = z80_size(inst); |
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203 if (read) { |
277
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204 /*if (modify) { |
213
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205 dst = push_r(dst, SCRATCH1); |
277
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206 }*/ |
213
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207 if (size == SZ_B) { |
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208 dst = call(dst, (uint8_t *)z80_read_byte); |
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209 } else { |
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210 dst = call(dst, (uint8_t *)z80_read_word); |
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211 } |
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212 if (modify) { |
277
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213 //dst = pop_r(dst, SCRATCH2); |
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214 dst = mov_ir(dst, inst->immed, SCRATCH2, SZ_W); |
213
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215 } |
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216 } |
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217 ea->base = SCRATCH1; |
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218 break; |
235
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219 case Z80_IX_DISPLACE: |
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220 case Z80_IY_DISPLACE: |
300
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221 reg = opts->regs[(inst->addr_mode & 0x1F) == Z80_IX_DISPLACE ? Z80_IX : Z80_IY]; |
213
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222 dst = mov_rr(dst, reg, areg, SZ_W); |
306
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223 dst = add_ir(dst, inst->ea_reg & 0x80 ? inst->ea_reg - 256 : inst->ea_reg, areg, SZ_W); |
213
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224 size = z80_size(inst); |
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225 if (read) { |
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226 if (modify) { |
277
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227 //dst = push_r(dst, SCRATCH1); |
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228 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, offsetof(z80_context, scratch1), SZ_W); |
213
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229 } |
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230 if (size == SZ_B) { |
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231 dst = call(dst, (uint8_t *)z80_read_byte); |
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232 } else { |
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233 dst = call(dst, (uint8_t *)z80_read_word); |
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234 } |
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235 if (modify) { |
277
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236 //dst = pop_r(dst, SCRATCH2); |
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237 dst = mov_rdisp8r(dst, CONTEXT, offsetof(z80_context, scratch1), SCRATCH2, SZ_W); |
213
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238 } |
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239 } |
269
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268
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240 ea->base = SCRATCH1; |
213
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241 break; |
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242 case Z80_UNUSED: |
235
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243 ea->mode = MODE_UNUSED; |
213
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244 break; |
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245 default: |
300
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246 fprintf(stderr, "Unrecognized Z80 addressing mode %d\n", inst->addr_mode & 0x1F); |
213
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247 exit(1); |
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248 } |
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249 return dst; |
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250 } |
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251 |
235
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|
252 uint8_t * z80_save_ea(uint8_t * dst, z80inst * inst, x86_z80_options * opts) |
213
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253 { |
267
1788e3f29c28
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266
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254 if ((inst->addr_mode & 0x1F) == Z80_REG) { |
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266
diff
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|
255 if (inst->ea_reg == Z80_IYH) { |
312
cf7ecda060c7
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311
diff
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|
256 if (inst->reg == Z80_IYL) { |
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311
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|
257 dst = ror_ir(dst, 8, opts->regs[Z80_IY], SZ_W); |
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|
258 dst = mov_rr(dst, SCRATCH1, opts->regs[Z80_IYL], SZ_B); |
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259 dst = ror_ir(dst, 8, opts->regs[Z80_IY], SZ_W); |
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260 } else { |
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261 dst = ror_ir(dst, 8, opts->regs[Z80_IY], SZ_W); |
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262 } |
267
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263 } else if (inst->reg != Z80_UNUSED && inst->reg != Z80_USE_IMMED && opts->regs[inst->ea_reg] >= AH && opts->regs[inst->ea_reg] <= BH) { |
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|
264 uint8_t other_reg = opts->regs[inst->reg]; |
269
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268
diff
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|
265 if (other_reg >= R8 || (other_reg >= RSP && other_reg <= RDI)) { |
267
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266
diff
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266 //we can't mix an *H reg with a register that requires the REX prefix |
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267 dst = ror_ir(dst, 8, opts->regs[z80_low_reg(inst->ea_reg)], SZ_W); |
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|
268 } |
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|
269 } |
213
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270 } |
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271 return dst; |
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272 } |
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273 |
235
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274 uint8_t * z80_save_result(uint8_t * dst, z80inst * inst) |
213
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275 { |
253
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276 switch(inst->addr_mode & 0x1f) |
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277 { |
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278 case Z80_REG_INDIRECT: |
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279 case Z80_IMMED_INDIRECT: |
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280 case Z80_IX_DISPLACE: |
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281 case Z80_IY_DISPLACE: |
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282 if (z80_size(inst) == SZ_B) { |
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283 dst = call(dst, (uint8_t *)z80_write_byte); |
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284 } else { |
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285 dst = call(dst, (uint8_t *)z80_write_word_lowfirst); |
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286 } |
213
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287 } |
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288 return dst; |
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289 } |
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290 |
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|
291 enum { |
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292 DONT_READ=0, |
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|
293 READ |
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294 }; |
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295 |
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296 enum { |
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297 DONT_MODIFY=0, |
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298 MODIFY |
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299 }; |
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300 |
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301 uint8_t zf_off(uint8_t flag) |
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302 { |
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303 return offsetof(z80_context, flags) + flag; |
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304 } |
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305 |
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306 uint8_t zaf_off(uint8_t flag) |
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307 { |
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308 return offsetof(z80_context, alt_flags) + flag; |
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309 } |
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310 |
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311 uint8_t zar_off(uint8_t reg) |
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312 { |
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313 return offsetof(z80_context, alt_regs) + reg; |
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314 } |
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315 |
235
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316 void z80_print_regs_exit(z80_context * context) |
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317 { |
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318 printf("A: %X\nB: %X\nC: %X\nD: %X\nE: %X\nHL: %X\nIX: %X\nIY: %X\nSP: %X\n\nIM: %d, IFF1: %d, IFF2: %d\n", |
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319 context->regs[Z80_A], context->regs[Z80_B], context->regs[Z80_C], |
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320 context->regs[Z80_D], context->regs[Z80_E], |
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321 (context->regs[Z80_H] << 8) | context->regs[Z80_L], |
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322 (context->regs[Z80_IXH] << 8) | context->regs[Z80_IXL], |
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323 (context->regs[Z80_IYH] << 8) | context->regs[Z80_IYL], |
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324 context->sp, context->im, context->iff1, context->iff2); |
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325 puts("--Alternate Regs--"); |
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326 printf("A: %X\nB: %X\nC: %X\nD: %X\nE: %X\nHL: %X\nIX: %X\nIY: %X\n", |
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327 context->alt_regs[Z80_A], context->alt_regs[Z80_B], context->alt_regs[Z80_C], |
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328 context->alt_regs[Z80_D], context->alt_regs[Z80_E], |
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329 (context->alt_regs[Z80_H] << 8) | context->alt_regs[Z80_L], |
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330 (context->alt_regs[Z80_IXH] << 8) | context->alt_regs[Z80_IXL], |
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331 (context->alt_regs[Z80_IYH] << 8) | context->alt_regs[Z80_IYL]); |
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332 exit(0); |
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333 } |
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334 |
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335 uint8_t * translate_z80inst(z80inst * inst, uint8_t * dst, z80_context * context, uint16_t address, uint8_t interp) |
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336 { |
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337 uint32_t cycles; |
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338 x86_ea src_op, dst_op; |
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339 uint8_t size; |
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340 x86_z80_options *opts = context->options; |
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341 uint8_t * start = dst; |
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342 if (!interp) { |
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343 dst = z80_check_cycles_int(dst, address); |
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344 if (context->breakpoint_flags[address / sizeof(uint8_t)] & (1 << (address % sizeof(uint8_t)))) { |
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345 zbreakpoint_patch(context, address, start); |
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346 } |
626
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347 } |
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348 switch(inst->op) |
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349 { |
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350 case Z80_LD: |
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351 size = z80_size(inst); |
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352 switch (inst->addr_mode & 0x1F) |
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353 { |
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354 case Z80_REG: |
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355 case Z80_REG_INDIRECT: |
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356 cycles = size == SZ_B ? 4 : 6; |
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357 if (inst->ea_reg == Z80_IX || inst->ea_reg == Z80_IY) { |
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358 cycles += 4; |
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359 } |
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360 if (inst->reg == Z80_I || inst->ea_reg == Z80_I) { |
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361 cycles += 5; |
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362 } |
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363 break; |
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364 case Z80_IMMED: |
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365 cycles = size == SZ_B ? 7 : 10; |
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366 break; |
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367 case Z80_IMMED_INDIRECT: |
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368 cycles = 10; |
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369 break; |
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370 case Z80_IX_DISPLACE: |
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371 case Z80_IY_DISPLACE: |
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372 cycles = 16; |
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373 break; |
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374 } |
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375 if ((inst->reg >= Z80_IXL && inst->reg <= Z80_IYH) || inst->reg == Z80_IX || inst->reg == Z80_IY) { |
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376 cycles += 4; |
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377 } |
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378 dst = zcycles(dst, cycles); |
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379 if (inst->addr_mode & Z80_DIR) { |
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380 dst = translate_z80_ea(inst, &dst_op, dst, opts, DONT_READ, MODIFY); |
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381 dst = translate_z80_reg(inst, &src_op, dst, opts); |
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382 } else { |
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383 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
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384 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
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385 } |
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386 if (src_op.mode == MODE_REG_DIRECT) { |
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387 if(dst_op.mode == MODE_REG_DISPLACE8) { |
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388 dst = mov_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, size); |
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389 } else { |
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390 dst = mov_rr(dst, src_op.base, dst_op.base, size); |
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391 } |
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392 } else if(src_op.mode == MODE_IMMED) { |
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393 dst = mov_ir(dst, src_op.disp, dst_op.base, size); |
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394 } else { |
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395 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, size); |
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396 } |
651
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397 if (inst->ea_reg == Z80_I && inst->addr_mode == Z80_REG) { |
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398 //ld a, i sets some flags |
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399 //TODO: Implement half-carry flag |
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400 dst = cmp_ir(dst, 0, dst_op.base, SZ_B); |
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401 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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402 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
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403 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B);; |
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404 dst = mov_rdisp8r(dst, CONTEXT, offsetof(z80_context, iff2), SCRATCH1, SZ_B); |
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405 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, zf_off(ZF_PV), SZ_B); |
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406 } |
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407 dst = z80_save_reg(dst, inst, opts); |
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408 dst = z80_save_ea(dst, inst, opts); |
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409 if (inst->addr_mode & Z80_DIR) { |
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410 dst = z80_save_result(dst, inst); |
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411 } |
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412 break; |
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413 case Z80_PUSH: |
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414 dst = zcycles(dst, (inst->reg == Z80_IX || inst->reg == Z80_IY) ? 9 : 5); |
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415 dst = sub_ir(dst, 2, opts->regs[Z80_SP], SZ_W); |
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416 if (inst->reg == Z80_AF) { |
363 | 417 dst = mov_rr(dst, opts->regs[Z80_A], SCRATCH1, SZ_B); |
418 dst = shl_ir(dst, 8, SCRATCH1, SZ_W); | |
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419 dst = mov_rdisp8r(dst, CONTEXT, zf_off(ZF_S), SCRATCH1, SZ_B); |
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420 dst = shl_ir(dst, 1, SCRATCH1, SZ_B); |
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421 dst = or_rdisp8r(dst, CONTEXT, zf_off(ZF_Z), SCRATCH1, SZ_B); |
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422 dst = shl_ir(dst, 2, SCRATCH1, SZ_B); |
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423 dst = or_rdisp8r(dst, CONTEXT, zf_off(ZF_H), SCRATCH1, SZ_B); |
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424 dst = shl_ir(dst, 2, SCRATCH1, SZ_B); |
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425 dst = or_rdisp8r(dst, CONTEXT, zf_off(ZF_PV), SCRATCH1, SZ_B); |
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426 dst = shl_ir(dst, 1, SCRATCH1, SZ_B); |
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427 dst = or_rdisp8r(dst, CONTEXT, zf_off(ZF_N), SCRATCH1, SZ_B); |
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428 dst = shl_ir(dst, 1, SCRATCH1, SZ_B); |
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429 dst = or_rdisp8r(dst, CONTEXT, zf_off(ZF_C), SCRATCH1, SZ_B); |
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430 } else { |
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431 dst = translate_z80_reg(inst, &src_op, dst, opts); |
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432 dst = mov_rr(dst, src_op.base, SCRATCH1, SZ_W); |
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433 } |
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434 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH2, SZ_W); |
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435 dst = call(dst, (uint8_t *)z80_write_word_highfirst); |
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436 //no call to save_z80_reg needed since there's no chance we'll use the only |
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437 //the upper half of a register pair |
213
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438 break; |
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439 case Z80_POP: |
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440 dst = zcycles(dst, (inst->reg == Z80_IX || inst->reg == Z80_IY) ? 8 : 4); |
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441 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH1, SZ_W); |
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442 dst = call(dst, (uint8_t *)z80_read_word); |
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443 dst = add_ir(dst, 2, opts->regs[Z80_SP], SZ_W); |
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444 if (inst->reg == Z80_AF) { |
505
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The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
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445 |
294 | 446 dst = bt_ir(dst, 0, SCRATCH1, SZ_W); |
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447 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
294 | 448 dst = bt_ir(dst, 1, SCRATCH1, SZ_W); |
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449 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_N)); |
294 | 450 dst = bt_ir(dst, 2, SCRATCH1, SZ_W); |
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451 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_PV)); |
294 | 452 dst = bt_ir(dst, 4, SCRATCH1, SZ_W); |
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453 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_H)); |
294 | 454 dst = bt_ir(dst, 6, SCRATCH1, SZ_W); |
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455 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_Z)); |
294 | 456 dst = bt_ir(dst, 7, SCRATCH1, SZ_W); |
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457 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_S)); |
294 | 458 dst = shr_ir(dst, 8, SCRATCH1, SZ_W); |
459 dst = mov_rr(dst, SCRATCH1, opts->regs[Z80_A], SZ_B); | |
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460 } else { |
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461 dst = translate_z80_reg(inst, &src_op, dst, opts); |
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462 dst = mov_rr(dst, SCRATCH1, src_op.base, SZ_W); |
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463 } |
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464 //no call to save_z80_reg needed since there's no chance we'll use the only |
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465 //the upper half of a register pair |
213
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466 break; |
241
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467 case Z80_EX: |
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468 if (inst->addr_mode == Z80_REG || inst->reg == Z80_HL) { |
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469 cycles = 4; |
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470 } else { |
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471 cycles = 8; |
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472 } |
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473 dst = zcycles(dst, cycles); |
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474 if (inst->addr_mode == Z80_REG) { |
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475 if(inst->reg == Z80_AF) { |
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476 dst = mov_rr(dst, opts->regs[Z80_A], SCRATCH1, SZ_B); |
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477 dst = mov_rdisp8r(dst, CONTEXT, zar_off(Z80_A), opts->regs[Z80_A], SZ_B); |
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478 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, zar_off(Z80_A), SZ_B); |
505
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The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
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479 |
241
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480 //Flags are currently word aligned, so we can move |
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481 //them efficiently a word at a time |
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482 for (int f = ZF_C; f < ZF_NUM; f+=2) { |
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483 dst = mov_rdisp8r(dst, CONTEXT, zf_off(f), SCRATCH1, SZ_W); |
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484 dst = mov_rdisp8r(dst, CONTEXT, zaf_off(f), SCRATCH2, SZ_W); |
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485 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, zaf_off(f), SZ_W); |
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486 dst = mov_rrdisp8(dst, SCRATCH2, CONTEXT, zf_off(f), SZ_W); |
241
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487 } |
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488 } else { |
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489 dst = xchg_rr(dst, opts->regs[Z80_DE], opts->regs[Z80_HL], SZ_W); |
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490 } |
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491 } else { |
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492 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH1, SZ_W); |
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493 dst = call(dst, (uint8_t *)z80_read_byte); |
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494 dst = xchg_rr(dst, opts->regs[inst->reg], SCRATCH1, SZ_B); |
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495 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH2, SZ_W); |
241
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496 dst = call(dst, (uint8_t *)z80_write_byte); |
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497 dst = zcycles(dst, 1); |
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498 uint8_t high_reg = z80_high_reg(inst->reg); |
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499 uint8_t use_reg; |
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500 //even though some of the upper halves can be used directly |
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501 //the limitations on mixing *H regs with the REX prefix |
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502 //prevent us from taking advantage of it |
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503 use_reg = opts->regs[inst->reg]; |
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504 dst = ror_ir(dst, 8, use_reg, SZ_W); |
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505 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH1, SZ_W); |
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506 dst = add_ir(dst, 1, SCRATCH1, SZ_W); |
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507 dst = call(dst, (uint8_t *)z80_read_byte); |
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508 dst = xchg_rr(dst, use_reg, SCRATCH1, SZ_B); |
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509 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH2, SZ_W); |
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510 dst = add_ir(dst, 1, SCRATCH2, SZ_W); |
241
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511 dst = call(dst, (uint8_t *)z80_write_byte); |
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512 //restore reg to normal rotation |
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513 dst = ror_ir(dst, 8, use_reg, SZ_W); |
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514 dst = zcycles(dst, 2); |
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515 } |
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516 break; |
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517 case Z80_EXX: |
241
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518 dst = zcycles(dst, 4); |
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519 dst = mov_rr(dst, opts->regs[Z80_BC], SCRATCH1, SZ_W); |
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520 dst = mov_rr(dst, opts->regs[Z80_HL], SCRATCH2, SZ_W); |
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521 dst = mov_rdisp8r(dst, CONTEXT, zar_off(Z80_C), opts->regs[Z80_BC], SZ_W); |
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522 dst = mov_rdisp8r(dst, CONTEXT, zar_off(Z80_L), opts->regs[Z80_HL], SZ_W); |
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523 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, zar_off(Z80_C), SZ_W); |
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524 dst = mov_rrdisp8(dst, SCRATCH2, CONTEXT, zar_off(Z80_L), SZ_W); |
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525 dst = mov_rr(dst, opts->regs[Z80_DE], SCRATCH1, SZ_W); |
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526 dst = mov_rdisp8r(dst, CONTEXT, zar_off(Z80_E), opts->regs[Z80_DE], SZ_W); |
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527 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, zar_off(Z80_E), SZ_W); |
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528 break; |
272 | 529 case Z80_LDI: { |
530 dst = zcycles(dst, 8); | |
531 dst = mov_rr(dst, opts->regs[Z80_HL], SCRATCH1, SZ_W); | |
532 dst = call(dst, (uint8_t *)z80_read_byte); | |
533 dst = mov_rr(dst, opts->regs[Z80_DE], SCRATCH2, SZ_W); | |
385 | 534 dst = call(dst, (uint8_t *)z80_write_byte); |
272 | 535 dst = zcycles(dst, 2); |
536 dst = add_ir(dst, 1, opts->regs[Z80_DE], SZ_W); | |
537 dst = add_ir(dst, 1, opts->regs[Z80_HL], SZ_W); | |
538 dst = sub_ir(dst, 1, opts->regs[Z80_BC], SZ_W); | |
539 //TODO: Implement half-carry | |
540 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); | |
541 dst = setcc_rdisp8(dst, CC_NZ, CONTEXT, zf_off(ZF_PV)); | |
542 break; | |
543 } | |
261
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544 case Z80_LDIR: { |
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545 dst = zcycles(dst, 8); |
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546 dst = mov_rr(dst, opts->regs[Z80_HL], SCRATCH1, SZ_W); |
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547 dst = call(dst, (uint8_t *)z80_read_byte); |
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548 dst = mov_rr(dst, opts->regs[Z80_DE], SCRATCH2, SZ_W); |
397 | 549 dst = call(dst, (uint8_t *)z80_write_byte); |
261
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550 dst = add_ir(dst, 1, opts->regs[Z80_DE], SZ_W); |
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551 dst = add_ir(dst, 1, opts->regs[Z80_HL], SZ_W); |
505
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552 |
261
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553 dst = sub_ir(dst, 1, opts->regs[Z80_BC], SZ_W); |
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554 uint8_t * cont = dst+1; |
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555 dst = jcc(dst, CC_Z, dst+2); |
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556 dst = zcycles(dst, 7); |
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557 //TODO: Figure out what the flag state should be here |
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558 //TODO: Figure out whether an interrupt can interrupt this |
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559 dst = jmp(dst, start); |
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560 *cont = dst - (cont + 1); |
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561 dst = zcycles(dst, 2); |
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562 //TODO: Implement half-carry |
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563 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
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564 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_PV), SZ_B); |
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565 break; |
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566 } |
273 | 567 case Z80_LDD: { |
568 dst = zcycles(dst, 8); | |
569 dst = mov_rr(dst, opts->regs[Z80_HL], SCRATCH1, SZ_W); | |
570 dst = call(dst, (uint8_t *)z80_read_byte); | |
571 dst = mov_rr(dst, opts->regs[Z80_DE], SCRATCH2, SZ_W); | |
388 | 572 dst = call(dst, (uint8_t *)z80_write_byte); |
273 | 573 dst = zcycles(dst, 2); |
574 dst = sub_ir(dst, 1, opts->regs[Z80_DE], SZ_W); | |
575 dst = sub_ir(dst, 1, opts->regs[Z80_HL], SZ_W); | |
576 dst = sub_ir(dst, 1, opts->regs[Z80_BC], SZ_W); | |
577 //TODO: Implement half-carry | |
578 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); | |
579 dst = setcc_rdisp8(dst, CC_NZ, CONTEXT, zf_off(ZF_PV)); | |
580 break; | |
581 } | |
582 case Z80_LDDR: { | |
583 dst = zcycles(dst, 8); | |
584 dst = mov_rr(dst, opts->regs[Z80_HL], SCRATCH1, SZ_W); | |
585 dst = call(dst, (uint8_t *)z80_read_byte); | |
586 dst = mov_rr(dst, opts->regs[Z80_DE], SCRATCH2, SZ_W); | |
388 | 587 dst = call(dst, (uint8_t *)z80_write_byte); |
273 | 588 dst = sub_ir(dst, 1, opts->regs[Z80_DE], SZ_W); |
589 dst = sub_ir(dst, 1, opts->regs[Z80_HL], SZ_W); | |
505
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590 |
273 | 591 dst = sub_ir(dst, 1, opts->regs[Z80_BC], SZ_W); |
592 uint8_t * cont = dst+1; | |
593 dst = jcc(dst, CC_Z, dst+2); | |
594 dst = zcycles(dst, 7); | |
595 //TODO: Figure out what the flag state should be here | |
596 //TODO: Figure out whether an interrupt can interrupt this | |
597 dst = jmp(dst, start); | |
598 *cont = dst - (cont + 1); | |
599 dst = zcycles(dst, 2); | |
600 //TODO: Implement half-carry | |
601 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); | |
602 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_PV), SZ_B); | |
603 break; | |
604 } | |
605 /*case Z80_CPI: | |
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606 case Z80_CPIR: |
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607 case Z80_CPD: |
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608 case Z80_CPDR: |
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609 break;*/ |
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610 case Z80_ADD: |
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611 cycles = 4; |
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612 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
213
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613 cycles += 12; |
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614 } else if(inst->addr_mode == Z80_IMMED) { |
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615 cycles += 3; |
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616 } else if(z80_size(inst) == SZ_W) { |
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617 cycles += 4; |
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618 } |
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619 dst = zcycles(dst, cycles); |
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620 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
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621 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
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622 if (src_op.mode == MODE_REG_DIRECT) { |
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623 dst = add_rr(dst, src_op.base, dst_op.base, z80_size(inst)); |
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624 } else { |
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625 dst = add_ir(dst, src_op.disp, dst_op.base, z80_size(inst)); |
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changeset
|
626 } |
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|
627 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
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628 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
213
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changeset
|
629 //TODO: Implement half-carry flag |
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|
630 if (z80_size(inst) == SZ_B) { |
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631 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV)); |
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632 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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633 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
213
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|
634 } |
4d4559b04c59
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changeset
|
635 dst = z80_save_reg(dst, inst, opts); |
4d4559b04c59
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|
636 dst = z80_save_ea(dst, inst, opts); |
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|
637 break; |
248
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638 case Z80_ADC: |
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639 cycles = 4; |
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640 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
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641 cycles += 12; |
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642 } else if(inst->addr_mode == Z80_IMMED) { |
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643 cycles += 3; |
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644 } else if(z80_size(inst) == SZ_W) { |
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645 cycles += 4; |
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646 } |
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647 dst = zcycles(dst, cycles); |
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648 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
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649 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
399 | 650 dst = bt_irdisp8(dst, 0, CONTEXT, zf_off(ZF_C), SZ_B); |
248
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651 if (src_op.mode == MODE_REG_DIRECT) { |
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652 dst = adc_rr(dst, src_op.base, dst_op.base, z80_size(inst)); |
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653 } else { |
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654 dst = adc_ir(dst, src_op.disp, dst_op.base, z80_size(inst)); |
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655 } |
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656 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
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657 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
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658 //TODO: Implement half-carry flag |
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659 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV)); |
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660 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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661 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
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662 dst = z80_save_reg(dst, inst, opts); |
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663 dst = z80_save_ea(dst, inst, opts); |
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664 break; |
213
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|
665 case Z80_SUB: |
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666 cycles = 4; |
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667 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
213
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668 cycles += 12; |
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669 } else if(inst->addr_mode == Z80_IMMED) { |
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670 cycles += 3; |
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671 } |
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672 dst = zcycles(dst, cycles); |
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673 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
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674 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
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|
675 if (src_op.mode == MODE_REG_DIRECT) { |
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676 dst = sub_rr(dst, src_op.base, dst_op.base, z80_size(inst)); |
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|
677 } else { |
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|
678 dst = sub_ir(dst, src_op.disp, dst_op.base, z80_size(inst)); |
4d4559b04c59
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|
679 } |
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|
680 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
235
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681 dst = mov_irdisp8(dst, 1, CONTEXT, zf_off(ZF_N), SZ_B); |
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682 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV)); |
213
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|
683 //TODO: Implement half-carry flag |
235
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684 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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685 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
213
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changeset
|
686 dst = z80_save_reg(dst, inst, opts); |
4d4559b04c59
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parents:
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changeset
|
687 dst = z80_save_ea(dst, inst, opts); |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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|
688 break; |
248
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689 case Z80_SBC: |
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690 cycles = 4; |
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691 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
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692 cycles += 12; |
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693 } else if(inst->addr_mode == Z80_IMMED) { |
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694 cycles += 3; |
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695 } else if(z80_size(inst) == SZ_W) { |
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696 cycles += 4; |
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697 } |
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698 dst = zcycles(dst, cycles); |
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|
699 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
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|
700 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
399 | 701 dst = bt_irdisp8(dst, 0, CONTEXT, zf_off(ZF_C), SZ_B); |
248
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|
702 if (src_op.mode == MODE_REG_DIRECT) { |
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703 dst = sbb_rr(dst, src_op.base, dst_op.base, z80_size(inst)); |
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704 } else { |
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|
705 dst = sbb_ir(dst, src_op.disp, dst_op.base, z80_size(inst)); |
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706 } |
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changeset
|
707 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
309
cb6a37861e42
Correctly set the N flag for SBC
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308
diff
changeset
|
708 dst = mov_irdisp8(dst, 1, CONTEXT, zf_off(ZF_N), SZ_B); |
248
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|
709 //TODO: Implement half-carry flag |
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|
710 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV)); |
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|
711 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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|
712 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
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|
713 dst = z80_save_reg(dst, inst, opts); |
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|
714 dst = z80_save_ea(dst, inst, opts); |
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|
715 break; |
213
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diff
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|
716 case Z80_AND: |
236
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diff
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|
717 cycles = 4; |
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|
718 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
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|
719 cycles += 12; |
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|
720 } else if(inst->addr_mode == Z80_IMMED) { |
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|
721 cycles += 3; |
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|
722 } else if(z80_size(inst) == SZ_W) { |
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|
723 cycles += 4; |
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|
724 } |
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725 dst = zcycles(dst, cycles); |
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726 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
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727 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
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728 if (src_op.mode == MODE_REG_DIRECT) { |
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729 dst = and_rr(dst, src_op.base, dst_op.base, z80_size(inst)); |
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730 } else { |
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731 dst = and_ir(dst, src_op.disp, dst_op.base, z80_size(inst)); |
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732 } |
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733 //TODO: Cleanup flags |
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734 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
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735 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
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736 //TODO: Implement half-carry flag |
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737 if (z80_size(inst) == SZ_B) { |
305
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738 dst = setcc_rdisp8(dst, CC_P, CONTEXT, zf_off(ZF_PV)); |
236
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739 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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740 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
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741 } |
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742 dst = z80_save_reg(dst, inst, opts); |
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743 dst = z80_save_ea(dst, inst, opts); |
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744 break; |
213
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745 case Z80_OR: |
236
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746 cycles = 4; |
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747 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
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748 cycles += 12; |
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749 } else if(inst->addr_mode == Z80_IMMED) { |
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750 cycles += 3; |
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751 } else if(z80_size(inst) == SZ_W) { |
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752 cycles += 4; |
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753 } |
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754 dst = zcycles(dst, cycles); |
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755 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
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756 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
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757 if (src_op.mode == MODE_REG_DIRECT) { |
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758 dst = or_rr(dst, src_op.base, dst_op.base, z80_size(inst)); |
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759 } else { |
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760 dst = or_ir(dst, src_op.disp, dst_op.base, z80_size(inst)); |
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761 } |
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762 //TODO: Cleanup flags |
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763 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
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764 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
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765 //TODO: Implement half-carry flag |
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766 if (z80_size(inst) == SZ_B) { |
305
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767 dst = setcc_rdisp8(dst, CC_P, CONTEXT, zf_off(ZF_PV)); |
236
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768 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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769 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
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770 } |
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771 dst = z80_save_reg(dst, inst, opts); |
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772 dst = z80_save_ea(dst, inst, opts); |
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773 break; |
213
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774 case Z80_XOR: |
236
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775 cycles = 4; |
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776 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
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777 cycles += 12; |
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778 } else if(inst->addr_mode == Z80_IMMED) { |
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779 cycles += 3; |
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780 } else if(z80_size(inst) == SZ_W) { |
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781 cycles += 4; |
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782 } |
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783 dst = zcycles(dst, cycles); |
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784 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
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785 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
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786 if (src_op.mode == MODE_REG_DIRECT) { |
295
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787 dst = xor_rr(dst, src_op.base, dst_op.base, z80_size(inst)); |
236
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788 } else { |
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789 dst = xor_ir(dst, src_op.disp, dst_op.base, z80_size(inst)); |
236
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790 } |
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791 //TODO: Cleanup flags |
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792 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
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793 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
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794 //TODO: Implement half-carry flag |
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795 if (z80_size(inst) == SZ_B) { |
304
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303
diff
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|
796 dst = setcc_rdisp8(dst, CC_P, CONTEXT, zf_off(ZF_PV)); |
236
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797 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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798 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
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799 } |
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|
800 dst = z80_save_reg(dst, inst, opts); |
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801 dst = z80_save_ea(dst, inst, opts); |
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diff
changeset
|
802 break; |
242 | 803 case Z80_CP: |
804 cycles = 4; | |
805 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { | |
806 cycles += 12; | |
807 } else if(inst->addr_mode == Z80_IMMED) { | |
808 cycles += 3; | |
809 } | |
810 dst = zcycles(dst, cycles); | |
811 dst = translate_z80_reg(inst, &dst_op, dst, opts); | |
812 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); | |
813 if (src_op.mode == MODE_REG_DIRECT) { | |
814 dst = cmp_rr(dst, src_op.base, dst_op.base, z80_size(inst)); | |
815 } else { | |
816 dst = cmp_ir(dst, src_op.disp, dst_op.base, z80_size(inst)); | |
817 } | |
818 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); | |
819 dst = mov_irdisp8(dst, 1, CONTEXT, zf_off(ZF_N), SZ_B); | |
820 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV)); | |
821 //TODO: Implement half-carry flag | |
822 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); | |
823 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); | |
824 dst = z80_save_reg(dst, inst, opts); | |
825 dst = z80_save_ea(dst, inst, opts); | |
826 break; | |
213
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diff
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|
827 case Z80_INC: |
4d4559b04c59
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Mike Pavone <pavone@retrodev.com>
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diff
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|
828 cycles = 4; |
4d4559b04c59
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diff
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|
829 if (inst->reg == Z80_IX || inst->reg == Z80_IY) { |
4d4559b04c59
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diff
changeset
|
830 cycles += 6; |
4d4559b04c59
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diff
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|
831 } else if(z80_size(inst) == SZ_W) { |
4d4559b04c59
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diff
changeset
|
832 cycles += 2; |
4d4559b04c59
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diff
changeset
|
833 } else if(inst->reg == Z80_IXH || inst->reg == Z80_IXL || inst->reg == Z80_IYH || inst->reg == Z80_IYL || inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
4d4559b04c59
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parents:
diff
changeset
|
834 cycles += 4; |
4d4559b04c59
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diff
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|
835 } |
373
91d28a868551
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Mike Pavone <pavone@retrodev.com>
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372
diff
changeset
|
836 dst = zcycles(dst, cycles); |
213
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diff
changeset
|
837 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
4d4559b04c59
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Mike Pavone <pavone@retrodev.com>
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diff
changeset
|
838 if (dst_op.mode == MODE_UNUSED) { |
4d4559b04c59
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diff
changeset
|
839 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY); |
4d4559b04c59
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diff
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|
840 } |
4d4559b04c59
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parents:
diff
changeset
|
841 dst = add_ir(dst, 1, dst_op.base, z80_size(inst)); |
4d4559b04c59
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changeset
|
842 if (z80_size(inst) == SZ_B) { |
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|
843 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
213
4d4559b04c59
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diff
changeset
|
844 //TODO: Implement half-carry flag |
235
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213
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|
845 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV)); |
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changeset
|
846 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
847 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
848 } |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
849 dst = z80_save_reg(dst, inst, opts); |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
850 dst = z80_save_ea(dst, inst, opts); |
387
582a68a90708
Fix dec and inc when the operand is in memory
Mike Pavone <pavone@retrodev.com>
parents:
385
diff
changeset
|
851 dst = z80_save_result(dst, inst); |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
852 break; |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
853 case Z80_DEC: |
19fb3523a9e5
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Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
854 cycles = 4; |
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parents:
235
diff
changeset
|
855 if (inst->reg == Z80_IX || inst->reg == Z80_IY) { |
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parents:
235
diff
changeset
|
856 cycles += 6; |
19fb3523a9e5
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Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
857 } else if(z80_size(inst) == SZ_W) { |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
858 cycles += 2; |
19fb3523a9e5
Implement more Z80 instructions (untested)
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parents:
235
diff
changeset
|
859 } else if(inst->reg == Z80_IXH || inst->reg == Z80_IXL || inst->reg == Z80_IYH || inst->reg == Z80_IYL || inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
19fb3523a9e5
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Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
860 cycles += 4; |
19fb3523a9e5
Implement more Z80 instructions (untested)
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parents:
235
diff
changeset
|
861 } |
373
91d28a868551
Fix cycle count for inc and dec
Mike Pavone <pavone@retrodev.com>
parents:
372
diff
changeset
|
862 dst = zcycles(dst, cycles); |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
863 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
19fb3523a9e5
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parents:
235
diff
changeset
|
864 if (dst_op.mode == MODE_UNUSED) { |
19fb3523a9e5
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Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
865 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY); |
19fb3523a9e5
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Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
866 } |
19fb3523a9e5
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Mike Pavone <pavone@retrodev.com>
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235
diff
changeset
|
867 dst = sub_ir(dst, 1, dst_op.base, z80_size(inst)); |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
868 if (z80_size(inst) == SZ_B) { |
311
56fcbfb8767a
Set the N flag to the correct value for DEC instructions
Mike Pavone <pavone@retrodev.com>
parents:
310
diff
changeset
|
869 dst = mov_irdisp8(dst, 1, CONTEXT, zf_off(ZF_N), SZ_B); |
236
19fb3523a9e5
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Mike Pavone <pavone@retrodev.com>
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235
diff
changeset
|
870 //TODO: Implement half-carry flag |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
871 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV)); |
19fb3523a9e5
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Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
872 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
873 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
874 } |
19fb3523a9e5
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Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
875 dst = z80_save_reg(dst, inst, opts); |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
876 dst = z80_save_ea(dst, inst, opts); |
387
582a68a90708
Fix dec and inc when the operand is in memory
Mike Pavone <pavone@retrodev.com>
parents:
385
diff
changeset
|
877 dst = z80_save_result(dst, inst); |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
878 break; |
274
be2b845d3e94
Implement CPL and NEG (untested)
Mike Pavone <pavone@retrodev.com>
parents:
273
diff
changeset
|
879 //case Z80_DAA: |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
880 case Z80_CPL: |
274
be2b845d3e94
Implement CPL and NEG (untested)
Mike Pavone <pavone@retrodev.com>
parents:
273
diff
changeset
|
881 dst = zcycles(dst, 4); |
be2b845d3e94
Implement CPL and NEG (untested)
Mike Pavone <pavone@retrodev.com>
parents:
273
diff
changeset
|
882 dst = not_r(dst, opts->regs[Z80_A], SZ_B); |
be2b845d3e94
Implement CPL and NEG (untested)
Mike Pavone <pavone@retrodev.com>
parents:
273
diff
changeset
|
883 //TODO: Implement half-carry flag |
be2b845d3e94
Implement CPL and NEG (untested)
Mike Pavone <pavone@retrodev.com>
parents:
273
diff
changeset
|
884 dst = mov_irdisp8(dst, 1, CONTEXT, zf_off(ZF_N), SZ_B); |
be2b845d3e94
Implement CPL and NEG (untested)
Mike Pavone <pavone@retrodev.com>
parents:
273
diff
changeset
|
885 break; |
be2b845d3e94
Implement CPL and NEG (untested)
Mike Pavone <pavone@retrodev.com>
parents:
273
diff
changeset
|
886 case Z80_NEG: |
be2b845d3e94
Implement CPL and NEG (untested)
Mike Pavone <pavone@retrodev.com>
parents:
273
diff
changeset
|
887 dst = zcycles(dst, 8); |
be2b845d3e94
Implement CPL and NEG (untested)
Mike Pavone <pavone@retrodev.com>
parents:
273
diff
changeset
|
888 dst = neg_r(dst, opts->regs[Z80_A], SZ_B); |
be2b845d3e94
Implement CPL and NEG (untested)
Mike Pavone <pavone@retrodev.com>
parents:
273
diff
changeset
|
889 //TODO: Implement half-carry flag |
be2b845d3e94
Implement CPL and NEG (untested)
Mike Pavone <pavone@retrodev.com>
parents:
273
diff
changeset
|
890 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
be2b845d3e94
Implement CPL and NEG (untested)
Mike Pavone <pavone@retrodev.com>
parents:
273
diff
changeset
|
891 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
be2b845d3e94
Implement CPL and NEG (untested)
Mike Pavone <pavone@retrodev.com>
parents:
273
diff
changeset
|
892 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
be2b845d3e94
Implement CPL and NEG (untested)
Mike Pavone <pavone@retrodev.com>
parents:
273
diff
changeset
|
893 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV)); |
be2b845d3e94
Implement CPL and NEG (untested)
Mike Pavone <pavone@retrodev.com>
parents:
273
diff
changeset
|
894 dst = mov_irdisp8(dst, 1, CONTEXT, zf_off(ZF_N), SZ_B); |
be2b845d3e94
Implement CPL and NEG (untested)
Mike Pavone <pavone@retrodev.com>
parents:
273
diff
changeset
|
895 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
896 case Z80_CCF: |
257 | 897 dst = zcycles(dst, 4); |
898 dst = xor_irdisp8(dst, 1, CONTEXT, zf_off(ZF_C), SZ_B); | |
899 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); | |
900 //TODO: Implement half-carry flag | |
901 break; | |
902 case Z80_SCF: | |
903 dst = zcycles(dst, 4); | |
904 dst = mov_irdisp8(dst, 1, CONTEXT, zf_off(ZF_C), SZ_B); | |
905 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); | |
906 //TODO: Implement half-carry flag | |
907 break; | |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
908 case Z80_NOP: |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
909 if (inst->immed == 42) { |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
910 dst = call(dst, (uint8_t *)z80_save_context); |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
911 dst = mov_rr(dst, CONTEXT, RDI, SZ_Q); |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
912 dst = jmp(dst, (uint8_t *)z80_print_regs_exit); |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
913 } else { |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
914 dst = zcycles(dst, 4 * inst->immed); |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
915 } |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
916 break; |
285
021aeb6df19b
Implement HALT (sort of tested)
Mike Pavone <pavone@retrodev.com>
parents:
284
diff
changeset
|
917 case Z80_HALT: |
021aeb6df19b
Implement HALT (sort of tested)
Mike Pavone <pavone@retrodev.com>
parents:
284
diff
changeset
|
918 dst = zcycles(dst, 4); |
021aeb6df19b
Implement HALT (sort of tested)
Mike Pavone <pavone@retrodev.com>
parents:
284
diff
changeset
|
919 dst = mov_ir(dst, address, SCRATCH1, SZ_W); |
021aeb6df19b
Implement HALT (sort of tested)
Mike Pavone <pavone@retrodev.com>
parents:
284
diff
changeset
|
920 uint8_t * call_inst = dst; |
021aeb6df19b
Implement HALT (sort of tested)
Mike Pavone <pavone@retrodev.com>
parents:
284
diff
changeset
|
921 dst = call(dst, (uint8_t *)z80_halt); |
021aeb6df19b
Implement HALT (sort of tested)
Mike Pavone <pavone@retrodev.com>
parents:
284
diff
changeset
|
922 dst = jmp(dst, call_inst); |
021aeb6df19b
Implement HALT (sort of tested)
Mike Pavone <pavone@retrodev.com>
parents:
284
diff
changeset
|
923 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
924 case Z80_DI: |
243
2f069a0b487e
Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
242
diff
changeset
|
925 dst = zcycles(dst, 4); |
2f069a0b487e
Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
242
diff
changeset
|
926 dst = mov_irdisp8(dst, 0, CONTEXT, offsetof(z80_context, iff1), SZ_B); |
2f069a0b487e
Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
242
diff
changeset
|
927 dst = mov_irdisp8(dst, 0, CONTEXT, offsetof(z80_context, iff2), SZ_B); |
250
5f1b68cecfc7
Implemented basic interrupt support in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
248
diff
changeset
|
928 dst = mov_rdisp8r(dst, CONTEXT, offsetof(z80_context, sync_cycle), ZLIMIT, SZ_D); |
401 | 929 dst = mov_irdisp8(dst, 0xFFFFFFFF, CONTEXT, offsetof(z80_context, int_cycle), SZ_D); |
243
2f069a0b487e
Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
242
diff
changeset
|
930 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
931 case Z80_EI: |
243
2f069a0b487e
Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
242
diff
changeset
|
932 dst = zcycles(dst, 4); |
420
9fb111b5641f
Fix access to int_enable_cycle in EI
Mike Pavone <pavone@retrodev.com>
parents:
401
diff
changeset
|
933 dst = mov_rrdisp32(dst, ZCYCLES, CONTEXT, offsetof(z80_context, int_enable_cycle), SZ_D); |
243
2f069a0b487e
Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
242
diff
changeset
|
934 dst = mov_irdisp8(dst, 1, CONTEXT, offsetof(z80_context, iff1), SZ_B); |
2f069a0b487e
Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
242
diff
changeset
|
935 dst = mov_irdisp8(dst, 1, CONTEXT, offsetof(z80_context, iff2), SZ_B); |
335 | 936 //interrupt enable has a one-instruction latency, minimum instruction duration is 4 cycles |
420
9fb111b5641f
Fix access to int_enable_cycle in EI
Mike Pavone <pavone@retrodev.com>
parents:
401
diff
changeset
|
937 dst = add_irdisp32(dst, 4, CONTEXT, offsetof(z80_context, int_enable_cycle), SZ_D); |
250
5f1b68cecfc7
Implemented basic interrupt support in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
248
diff
changeset
|
938 dst = call(dst, (uint8_t *)z80_do_sync); |
243
2f069a0b487e
Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
242
diff
changeset
|
939 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
940 case Z80_IM: |
243
2f069a0b487e
Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
242
diff
changeset
|
941 dst = zcycles(dst, 4); |
2f069a0b487e
Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
242
diff
changeset
|
942 dst = mov_irdisp8(dst, inst->immed, CONTEXT, offsetof(z80_context, im), SZ_B); |
2f069a0b487e
Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
242
diff
changeset
|
943 break; |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
944 case Z80_RLC: |
275
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
945 cycles = inst->immed == 0 ? 4 : (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8); |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
946 dst = zcycles(dst, cycles); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
947 if (inst->addr_mode != Z80_UNUSED) { |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
948 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
949 dst = translate_z80_reg(inst, &src_op, dst, opts); //For IX/IY variants that also write to a register |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
950 dst = zcycles(dst, 1); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
951 } else { |
302
3b831fe32c15
More fixes for confusion between Z80_UNUSED and MODE_UNUSED
Mike Pavone <pavone@retrodev.com>
parents:
301
diff
changeset
|
952 src_op.mode = MODE_UNUSED; |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
953 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
954 } |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
955 dst = rol_ir(dst, 1, dst_op.base, SZ_B); |
301
6e15509a1257
Compare src_op.mode with the correct constant in shift/rotate instructions
Mike Pavone <pavone@retrodev.com>
parents:
300
diff
changeset
|
956 if (src_op.mode != MODE_UNUSED) { |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
957 dst = mov_rr(dst, dst_op.base, src_op.base, SZ_B); |
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
958 } |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
959 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
960 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
961 //TODO: Implement half-carry flag |
651
103d5cabbe14
Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown.
Michael Pavone <pavone@retrodev.com>
parents:
644
diff
changeset
|
962 if (inst->immed) { |
103d5cabbe14
Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown.
Michael Pavone <pavone@retrodev.com>
parents:
644
diff
changeset
|
963 //rlca does not set these flags |
103d5cabbe14
Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown.
Michael Pavone <pavone@retrodev.com>
parents:
644
diff
changeset
|
964 dst = cmp_ir(dst, 0, dst_op.base, SZ_B); |
103d5cabbe14
Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown.
Michael Pavone <pavone@retrodev.com>
parents:
644
diff
changeset
|
965 dst = setcc_rdisp8(dst, CC_P, CONTEXT, zf_off(ZF_PV)); |
103d5cabbe14
Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown.
Michael Pavone <pavone@retrodev.com>
parents:
644
diff
changeset
|
966 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
103d5cabbe14
Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown.
Michael Pavone <pavone@retrodev.com>
parents:
644
diff
changeset
|
967 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
103d5cabbe14
Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown.
Michael Pavone <pavone@retrodev.com>
parents:
644
diff
changeset
|
968 } |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
969 if (inst->addr_mode != Z80_UNUSED) { |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
970 dst = z80_save_result(dst, inst); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
971 if (src_op.mode != MODE_UNUSED) { |
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
972 dst = z80_save_reg(dst, inst, opts); |
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
973 } |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
974 } else { |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
975 dst = z80_save_reg(dst, inst, opts); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
976 } |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
977 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
978 case Z80_RL: |
275
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
979 cycles = inst->immed == 0 ? 4 : (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8); |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
980 dst = zcycles(dst, cycles); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
981 if (inst->addr_mode != Z80_UNUSED) { |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
982 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
983 dst = translate_z80_reg(inst, &src_op, dst, opts); //For IX/IY variants that also write to a register |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
984 dst = zcycles(dst, 1); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
985 } else { |
302
3b831fe32c15
More fixes for confusion between Z80_UNUSED and MODE_UNUSED
Mike Pavone <pavone@retrodev.com>
parents:
301
diff
changeset
|
986 src_op.mode = MODE_UNUSED; |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
987 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
988 } |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
989 dst = bt_irdisp8(dst, 0, CONTEXT, zf_off(ZF_C), SZ_B); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
990 dst = rcl_ir(dst, 1, dst_op.base, SZ_B); |
301
6e15509a1257
Compare src_op.mode with the correct constant in shift/rotate instructions
Mike Pavone <pavone@retrodev.com>
parents:
300
diff
changeset
|
991 if (src_op.mode != MODE_UNUSED) { |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
992 dst = mov_rr(dst, dst_op.base, src_op.base, SZ_B); |
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
993 } |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
994 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
995 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
996 //TODO: Implement half-carry flag |
651
103d5cabbe14
Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown.
Michael Pavone <pavone@retrodev.com>
parents:
644
diff
changeset
|
997 if (inst->immed) { |
103d5cabbe14
Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown.
Michael Pavone <pavone@retrodev.com>
parents:
644
diff
changeset
|
998 //rla does not set these flags |
103d5cabbe14
Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown.
Michael Pavone <pavone@retrodev.com>
parents:
644
diff
changeset
|
999 dst = cmp_ir(dst, 0, dst_op.base, SZ_B); |
103d5cabbe14
Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown.
Michael Pavone <pavone@retrodev.com>
parents:
644
diff
changeset
|
1000 dst = setcc_rdisp8(dst, CC_P, CONTEXT, zf_off(ZF_PV)); |
103d5cabbe14
Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown.
Michael Pavone <pavone@retrodev.com>
parents:
644
diff
changeset
|
1001 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
103d5cabbe14
Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown.
Michael Pavone <pavone@retrodev.com>
parents:
644
diff
changeset
|
1002 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
103d5cabbe14
Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown.
Michael Pavone <pavone@retrodev.com>
parents:
644
diff
changeset
|
1003 } |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1004 if (inst->addr_mode != Z80_UNUSED) { |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1005 dst = z80_save_result(dst, inst); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1006 if (src_op.mode != MODE_UNUSED) { |
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1007 dst = z80_save_reg(dst, inst, opts); |
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1008 } |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1009 } else { |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1010 dst = z80_save_reg(dst, inst, opts); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1011 } |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1012 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1013 case Z80_RRC: |
275
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1014 cycles = inst->immed == 0 ? 4 : (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8); |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1015 dst = zcycles(dst, cycles); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1016 if (inst->addr_mode != Z80_UNUSED) { |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1017 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1018 dst = translate_z80_reg(inst, &src_op, dst, opts); //For IX/IY variants that also write to a register |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1019 dst = zcycles(dst, 1); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1020 } else { |
302
3b831fe32c15
More fixes for confusion between Z80_UNUSED and MODE_UNUSED
Mike Pavone <pavone@retrodev.com>
parents:
301
diff
changeset
|
1021 src_op.mode = MODE_UNUSED; |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1022 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1023 } |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1024 dst = ror_ir(dst, 1, dst_op.base, SZ_B); |
301
6e15509a1257
Compare src_op.mode with the correct constant in shift/rotate instructions
Mike Pavone <pavone@retrodev.com>
parents:
300
diff
changeset
|
1025 if (src_op.mode != MODE_UNUSED) { |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1026 dst = mov_rr(dst, dst_op.base, src_op.base, SZ_B); |
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1027 } |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1028 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1029 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1030 //TODO: Implement half-carry flag |
651
103d5cabbe14
Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown.
Michael Pavone <pavone@retrodev.com>
parents:
644
diff
changeset
|
1031 if (inst->immed) { |
103d5cabbe14
Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown.
Michael Pavone <pavone@retrodev.com>
parents:
644
diff
changeset
|
1032 //rrca does not set these flags |
103d5cabbe14
Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown.
Michael Pavone <pavone@retrodev.com>
parents:
644
diff
changeset
|
1033 dst = cmp_ir(dst, 0, dst_op.base, SZ_B); |
103d5cabbe14
Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown.
Michael Pavone <pavone@retrodev.com>
parents:
644
diff
changeset
|
1034 dst = setcc_rdisp8(dst, CC_P, CONTEXT, zf_off(ZF_PV)); |
103d5cabbe14
Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown.
Michael Pavone <pavone@retrodev.com>
parents:
644
diff
changeset
|
1035 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
103d5cabbe14
Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown.
Michael Pavone <pavone@retrodev.com>
parents:
644
diff
changeset
|
1036 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
103d5cabbe14
Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown.
Michael Pavone <pavone@retrodev.com>
parents:
644
diff
changeset
|
1037 } |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1038 if (inst->addr_mode != Z80_UNUSED) { |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1039 dst = z80_save_result(dst, inst); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1040 if (src_op.mode != MODE_UNUSED) { |
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1041 dst = z80_save_reg(dst, inst, opts); |
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1042 } |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1043 } else { |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1044 dst = z80_save_reg(dst, inst, opts); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1045 } |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1046 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1047 case Z80_RR: |
275
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1048 cycles = inst->immed == 0 ? 4 : (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8); |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1049 dst = zcycles(dst, cycles); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1050 if (inst->addr_mode != Z80_UNUSED) { |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1051 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1052 dst = translate_z80_reg(inst, &src_op, dst, opts); //For IX/IY variants that also write to a register |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1053 dst = zcycles(dst, 1); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1054 } else { |
302
3b831fe32c15
More fixes for confusion between Z80_UNUSED and MODE_UNUSED
Mike Pavone <pavone@retrodev.com>
parents:
301
diff
changeset
|
1055 src_op.mode = MODE_UNUSED; |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1056 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1057 } |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1058 dst = bt_irdisp8(dst, 0, CONTEXT, zf_off(ZF_C), SZ_B); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1059 dst = rcr_ir(dst, 1, dst_op.base, SZ_B); |
301
6e15509a1257
Compare src_op.mode with the correct constant in shift/rotate instructions
Mike Pavone <pavone@retrodev.com>
parents:
300
diff
changeset
|
1060 if (src_op.mode != MODE_UNUSED) { |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1061 dst = mov_rr(dst, dst_op.base, src_op.base, SZ_B); |
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1062 } |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1063 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1064 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1065 //TODO: Implement half-carry flag |
651
103d5cabbe14
Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown.
Michael Pavone <pavone@retrodev.com>
parents:
644
diff
changeset
|
1066 if (inst->immed) { |
103d5cabbe14
Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown.
Michael Pavone <pavone@retrodev.com>
parents:
644
diff
changeset
|
1067 //rra does not set these flags |
103d5cabbe14
Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown.
Michael Pavone <pavone@retrodev.com>
parents:
644
diff
changeset
|
1068 dst = cmp_ir(dst, 0, dst_op.base, SZ_B); |
103d5cabbe14
Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown.
Michael Pavone <pavone@retrodev.com>
parents:
644
diff
changeset
|
1069 dst = setcc_rdisp8(dst, CC_P, CONTEXT, zf_off(ZF_PV)); |
103d5cabbe14
Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown.
Michael Pavone <pavone@retrodev.com>
parents:
644
diff
changeset
|
1070 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
103d5cabbe14
Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown.
Michael Pavone <pavone@retrodev.com>
parents:
644
diff
changeset
|
1071 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
103d5cabbe14
Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown.
Michael Pavone <pavone@retrodev.com>
parents:
644
diff
changeset
|
1072 } |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1073 if (inst->addr_mode != Z80_UNUSED) { |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1074 dst = z80_save_result(dst, inst); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1075 if (src_op.mode != MODE_UNUSED) { |
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1076 dst = z80_save_reg(dst, inst, opts); |
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1077 } |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1078 } else { |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1079 dst = z80_save_reg(dst, inst, opts); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1080 } |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1081 break; |
275
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1082 case Z80_SLA: |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1083 case Z80_SLL: |
275
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1084 cycles = inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8; |
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1085 dst = zcycles(dst, cycles); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1086 if (inst->addr_mode != Z80_UNUSED) { |
275
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1087 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1088 dst = translate_z80_reg(inst, &src_op, dst, opts); //For IX/IY variants that also write to a register |
275
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1089 dst = zcycles(dst, 1); |
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1090 } else { |
302
3b831fe32c15
More fixes for confusion between Z80_UNUSED and MODE_UNUSED
Mike Pavone <pavone@retrodev.com>
parents:
301
diff
changeset
|
1091 src_op.mode = MODE_UNUSED; |
275
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1092 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1093 } |
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1094 dst = shl_ir(dst, 1, dst_op.base, SZ_B); |
310
bf440db64086
Implement carry flag for shift instructions. Implement weird behavior for bit 0 of SLL. Fix missing break statement in SRL.
Mike Pavone <pavone@retrodev.com>
parents:
309
diff
changeset
|
1095 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
bf440db64086
Implement carry flag for shift instructions. Implement weird behavior for bit 0 of SLL. Fix missing break statement in SRL.
Mike Pavone <pavone@retrodev.com>
parents:
309
diff
changeset
|
1096 if (inst->op == Z80_SLL) { |
bf440db64086
Implement carry flag for shift instructions. Implement weird behavior for bit 0 of SLL. Fix missing break statement in SRL.
Mike Pavone <pavone@retrodev.com>
parents:
309
diff
changeset
|
1097 dst = or_ir(dst, 1, dst_op.base, SZ_B); |
bf440db64086
Implement carry flag for shift instructions. Implement weird behavior for bit 0 of SLL. Fix missing break statement in SRL.
Mike Pavone <pavone@retrodev.com>
parents:
309
diff
changeset
|
1098 } |
301
6e15509a1257
Compare src_op.mode with the correct constant in shift/rotate instructions
Mike Pavone <pavone@retrodev.com>
parents:
300
diff
changeset
|
1099 if (src_op.mode != MODE_UNUSED) { |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1100 dst = mov_rr(dst, dst_op.base, src_op.base, SZ_B); |
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1101 } |
275
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1102 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1103 //TODO: Implement half-carry flag |
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1104 dst = cmp_ir(dst, 0, dst_op.base, SZ_B); |
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1105 dst = setcc_rdisp8(dst, CC_P, CONTEXT, zf_off(ZF_PV)); |
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1106 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1107 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1108 if (inst->addr_mode != Z80_UNUSED) { |
275
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1109 dst = z80_save_result(dst, inst); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1110 if (src_op.mode != MODE_UNUSED) { |
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1111 dst = z80_save_reg(dst, inst, opts); |
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1112 } |
275
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1113 } else { |
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1114 dst = z80_save_reg(dst, inst, opts); |
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1115 } |
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1116 break; |
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1117 case Z80_SRA: |
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1118 cycles = inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8; |
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1119 dst = zcycles(dst, cycles); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1120 if (inst->addr_mode != Z80_UNUSED) { |
275
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1121 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1122 dst = translate_z80_reg(inst, &src_op, dst, opts); //For IX/IY variants that also write to a register |
275
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1123 dst = zcycles(dst, 1); |
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1124 } else { |
302
3b831fe32c15
More fixes for confusion between Z80_UNUSED and MODE_UNUSED
Mike Pavone <pavone@retrodev.com>
parents:
301
diff
changeset
|
1125 src_op.mode = MODE_UNUSED; |
275
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1126 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
1a7d0a964ad2
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1127 } |
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1128 dst = sar_ir(dst, 1, dst_op.base, SZ_B); |
301
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1129 if (src_op.mode != MODE_UNUSED) { |
299
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1130 dst = mov_rr(dst, dst_op.base, src_op.base, SZ_B); |
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1131 } |
310
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1132 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
275
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1133 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
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1134 //TODO: Implement half-carry flag |
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1135 dst = cmp_ir(dst, 0, dst_op.base, SZ_B); |
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1136 dst = setcc_rdisp8(dst, CC_P, CONTEXT, zf_off(ZF_PV)); |
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1137 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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1138 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
299
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1139 if (inst->addr_mode != Z80_UNUSED) { |
275
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1140 dst = z80_save_result(dst, inst); |
299
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1141 if (src_op.mode != MODE_UNUSED) { |
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1142 dst = z80_save_reg(dst, inst, opts); |
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1143 } |
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1144 } else { |
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1145 dst = z80_save_reg(dst, inst, opts); |
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1146 } |
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1147 break; |
213
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1148 case Z80_SRL: |
275
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1149 cycles = inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8; |
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1150 dst = zcycles(dst, cycles); |
299
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1151 if (inst->addr_mode != Z80_UNUSED) { |
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1152 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY); |
299
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1153 dst = translate_z80_reg(inst, &src_op, dst, opts); //For IX/IY variants that also write to a register |
275
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1154 dst = zcycles(dst, 1); |
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1155 } else { |
302
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diff
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1156 src_op.mode = MODE_UNUSED; |
275
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1157 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
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1158 } |
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1159 dst = shr_ir(dst, 1, dst_op.base, SZ_B); |
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1160 if (src_op.mode != MODE_UNUSED) { |
299
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1161 dst = mov_rr(dst, dst_op.base, src_op.base, SZ_B); |
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1162 } |
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1163 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
275
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1164 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
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1165 //TODO: Implement half-carry flag |
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1166 dst = cmp_ir(dst, 0, dst_op.base, SZ_B); |
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1167 dst = setcc_rdisp8(dst, CC_P, CONTEXT, zf_off(ZF_PV)); |
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1168 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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1169 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
299
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1170 if (inst->addr_mode != Z80_UNUSED) { |
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1171 dst = z80_save_result(dst, inst); |
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1172 if (src_op.mode != MODE_UNUSED) { |
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1173 dst = z80_save_reg(dst, inst, opts); |
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1174 } |
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1175 } else { |
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1176 dst = z80_save_reg(dst, inst, opts); |
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1177 } |
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1178 break; |
286 | 1179 case Z80_RLD: |
1180 dst = zcycles(dst, 8); | |
1181 dst = mov_rr(dst, opts->regs[Z80_HL], SCRATCH1, SZ_W); | |
1182 dst = call(dst, (uint8_t *)z80_read_byte); | |
1183 //Before: (HL) = 0x12, A = 0x34 | |
1184 //After: (HL) = 0x24, A = 0x31 | |
1185 dst = mov_rr(dst, opts->regs[Z80_A], SCRATCH2, SZ_B); | |
1186 dst = shl_ir(dst, 4, SCRATCH1, SZ_W); | |
1187 dst = and_ir(dst, 0xF, SCRATCH2, SZ_W); | |
1188 dst = and_ir(dst, 0xFFF, SCRATCH1, SZ_W); | |
1189 dst = and_ir(dst, 0xF0, opts->regs[Z80_A], SZ_B); | |
1190 dst = or_rr(dst, SCRATCH2, SCRATCH1, SZ_W); | |
1191 //SCRATCH1 = 0x0124 | |
1192 dst = ror_ir(dst, 8, SCRATCH1, SZ_W); | |
1193 dst = zcycles(dst, 4); | |
1194 dst = or_rr(dst, SCRATCH1, opts->regs[Z80_A], SZ_B); | |
287
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1195 //set flags |
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1196 //TODO: Implement half-carry flag |
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1197 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
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1198 dst = setcc_rdisp8(dst, CC_P, CONTEXT, zf_off(ZF_PV)); |
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1199 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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1200 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
505
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1201 |
286 | 1202 dst = mov_rr(dst, opts->regs[Z80_HL], SCRATCH2, SZ_W); |
1203 dst = ror_ir(dst, 8, SCRATCH1, SZ_W); | |
1204 dst = call(dst, (uint8_t *)z80_write_byte); | |
1205 break; | |
287
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1206 case Z80_RRD: |
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1207 dst = zcycles(dst, 8); |
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1208 dst = mov_rr(dst, opts->regs[Z80_HL], SCRATCH1, SZ_W); |
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1209 dst = call(dst, (uint8_t *)z80_read_byte); |
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1210 //Before: (HL) = 0x12, A = 0x34 |
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1211 //After: (HL) = 0x41, A = 0x32 |
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1212 dst = movzx_rr(dst, opts->regs[Z80_A], SCRATCH2, SZ_B, SZ_W); |
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1213 dst = ror_ir(dst, 4, SCRATCH1, SZ_W); |
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1214 dst = shl_ir(dst, 4, SCRATCH2, SZ_W); |
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1215 dst = and_ir(dst, 0xF00F, SCRATCH1, SZ_W); |
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1216 dst = and_ir(dst, 0xF0, opts->regs[Z80_A], SZ_B); |
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1217 //SCRATCH1 = 0x2001 |
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1218 //SCRATCH2 = 0x0040 |
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1219 dst = or_rr(dst, SCRATCH2, SCRATCH1, SZ_W); |
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1220 //SCRATCH1 = 0x2041 |
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1221 dst = ror_ir(dst, 8, SCRATCH1, SZ_W); |
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1222 dst = zcycles(dst, 4); |
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1223 dst = shr_ir(dst, 4, SCRATCH1, SZ_B); |
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1224 dst = or_rr(dst, SCRATCH1, opts->regs[Z80_A], SZ_B); |
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1225 //set flags |
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1226 //TODO: Implement half-carry flag |
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1227 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
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1228 dst = setcc_rdisp8(dst, CC_P, CONTEXT, zf_off(ZF_PV)); |
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1229 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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1230 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
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1231 |
287
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1232 dst = mov_rr(dst, opts->regs[Z80_HL], SCRATCH2, SZ_W); |
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1233 dst = ror_ir(dst, 8, SCRATCH1, SZ_W); |
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1234 dst = call(dst, (uint8_t *)z80_write_byte); |
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1235 break; |
308
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1236 case Z80_BIT: { |
239
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1237 cycles = (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) ? 8 : 16; |
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1238 dst = zcycles(dst, cycles); |
308
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307
diff
changeset
|
1239 uint8_t bit; |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
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parents:
307
diff
changeset
|
1240 if ((inst->addr_mode & 0x1F) == Z80_REG && opts->regs[inst->ea_reg] >= AH && opts->regs[inst->ea_reg] <= BH) { |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
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parents:
307
diff
changeset
|
1241 src_op.base = opts->regs[z80_word_reg(inst->ea_reg)]; |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1242 size = SZ_W; |
e0e81551fd7e
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Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1243 bit = inst->immed + 8; |
e0e81551fd7e
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Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1244 } else { |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1245 size = SZ_B; |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1246 bit = inst->immed; |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1247 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1248 } |
239
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
1249 if (inst->addr_mode != Z80_REG) { |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
1250 //Reads normally take 3 cycles, but the read at the end of a bit instruction takes 4 |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
1251 dst = zcycles(dst, 1); |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
1252 } |
308
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Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1253 dst = bt_ir(dst, bit, src_op.base, size); |
303
8290d3086ff0
BIT was setting the zero flag to the opposite of what it should have. This is now fixed.
Mike Pavone <pavone@retrodev.com>
parents:
302
diff
changeset
|
1254 dst = setcc_rdisp8(dst, CC_NC, CONTEXT, zf_off(ZF_Z)); |
307
b6393b89a7e4
Complete flag behavior for Z80 BIT instruction
Mike Pavone <pavone@retrodev.com>
parents:
306
diff
changeset
|
1255 dst = setcc_rdisp8(dst, CC_NC, CONTEXT, zf_off(ZF_PV)); |
b6393b89a7e4
Complete flag behavior for Z80 BIT instruction
Mike Pavone <pavone@retrodev.com>
parents:
306
diff
changeset
|
1256 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
b6393b89a7e4
Complete flag behavior for Z80 BIT instruction
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306
diff
changeset
|
1257 if (inst->immed == 7) { |
308
e0e81551fd7e
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Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1258 dst = cmp_ir(dst, 0, src_op.base, size); |
307
b6393b89a7e4
Complete flag behavior for Z80 BIT instruction
Mike Pavone <pavone@retrodev.com>
parents:
306
diff
changeset
|
1259 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
b6393b89a7e4
Complete flag behavior for Z80 BIT instruction
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306
diff
changeset
|
1260 } else { |
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Complete flag behavior for Z80 BIT instruction
Mike Pavone <pavone@retrodev.com>
parents:
306
diff
changeset
|
1261 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_S), SZ_B); |
b6393b89a7e4
Complete flag behavior for Z80 BIT instruction
Mike Pavone <pavone@retrodev.com>
parents:
306
diff
changeset
|
1262 } |
239
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
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238
diff
changeset
|
1263 break; |
308
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Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1264 } |
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Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1265 case Z80_SET: { |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
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246
diff
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|
1266 cycles = (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) ? 8 : 16; |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
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246
diff
changeset
|
1267 dst = zcycles(dst, cycles); |
308
e0e81551fd7e
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parents:
307
diff
changeset
|
1268 uint8_t bit; |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1269 if ((inst->addr_mode & 0x1F) == Z80_REG && opts->regs[inst->ea_reg] >= AH && opts->regs[inst->ea_reg] <= BH) { |
e0e81551fd7e
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307
diff
changeset
|
1270 src_op.base = opts->regs[z80_word_reg(inst->ea_reg)]; |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
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307
diff
changeset
|
1271 size = SZ_W; |
e0e81551fd7e
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Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1272 bit = inst->immed + 8; |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
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parents:
307
diff
changeset
|
1273 } else { |
e0e81551fd7e
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parents:
307
diff
changeset
|
1274 size = SZ_B; |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1275 bit = inst->immed; |
384
5500d1d1269e
Fix set/res when the operand is in memory
Mike Pavone <pavone@retrodev.com>
parents:
373
diff
changeset
|
1276 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, MODIFY); |
308
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Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
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307
diff
changeset
|
1277 } |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1278 if (inst->reg != Z80_USE_IMMED) { |
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1279 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1280 } |
247
682e505f5757
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Mike Pavone <pavone@retrodev.com>
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246
diff
changeset
|
1281 if (inst->addr_mode != Z80_REG) { |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1282 //Reads normally take 3 cycles, but the read in the middle of a set instruction takes 4 |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1283 dst = zcycles(dst, 1); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1284 } |
308
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1285 dst = bts_ir(dst, bit, src_op.base, size); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
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|
1286 if (inst->reg != Z80_USE_IMMED) { |
308
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1287 if (size == SZ_W) { |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
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parents:
307
diff
changeset
|
1288 if (dst_op.base >= R8) { |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
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parents:
307
diff
changeset
|
1289 dst = ror_ir(dst, 8, src_op.base, SZ_W); |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
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parents:
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diff
changeset
|
1290 dst = mov_rr(dst, opts->regs[z80_low_reg(inst->ea_reg)], dst_op.base, SZ_B); |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
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307
diff
changeset
|
1291 dst = ror_ir(dst, 8, src_op.base, SZ_W); |
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Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1292 } else { |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1293 dst = mov_rr(dst, opts->regs[inst->ea_reg], dst_op.base, SZ_B); |
505
b7b7a1cab44a
The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1294 } |
308
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Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1295 } else { |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
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parents:
307
diff
changeset
|
1296 dst = mov_rr(dst, src_op.base, dst_op.base, SZ_B); |
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Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1297 } |
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parents:
307
diff
changeset
|
1298 } |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
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parents:
307
diff
changeset
|
1299 if ((inst->addr_mode & 0x1F) != Z80_REG) { |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
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parents:
307
diff
changeset
|
1300 dst = z80_save_result(dst, inst); |
e0e81551fd7e
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parents:
307
diff
changeset
|
1301 if (inst->reg != Z80_USE_IMMED) { |
e0e81551fd7e
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307
diff
changeset
|
1302 dst = z80_save_reg(dst, inst, opts); |
e0e81551fd7e
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diff
changeset
|
1303 } |
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parents:
307
diff
changeset
|
1304 } |
e0e81551fd7e
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307
diff
changeset
|
1305 break; |
e0e81551fd7e
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diff
changeset
|
1306 } |
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Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
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parents:
307
diff
changeset
|
1307 case Z80_RES: { |
e0e81551fd7e
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diff
changeset
|
1308 cycles = (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) ? 8 : 16; |
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diff
changeset
|
1309 dst = zcycles(dst, cycles); |
e0e81551fd7e
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diff
changeset
|
1310 uint8_t bit; |
e0e81551fd7e
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diff
changeset
|
1311 if ((inst->addr_mode & 0x1F) == Z80_REG && opts->regs[inst->ea_reg] >= AH && opts->regs[inst->ea_reg] <= BH) { |
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diff
changeset
|
1312 src_op.base = opts->regs[z80_word_reg(inst->ea_reg)]; |
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diff
changeset
|
1313 size = SZ_W; |
e0e81551fd7e
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diff
changeset
|
1314 bit = inst->immed + 8; |
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diff
changeset
|
1315 } else { |
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diff
changeset
|
1316 size = SZ_B; |
e0e81551fd7e
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diff
changeset
|
1317 bit = inst->immed; |
384
5500d1d1269e
Fix set/res when the operand is in memory
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373
diff
changeset
|
1318 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, MODIFY); |
308
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diff
changeset
|
1319 } |
e0e81551fd7e
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diff
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|
1320 if (inst->reg != Z80_USE_IMMED) { |
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changeset
|
1321 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
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changeset
|
1322 } |
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diff
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|
1323 if (inst->addr_mode != Z80_REG) { |
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changeset
|
1324 //Reads normally take 3 cycles, but the read in the middle of a set instruction takes 4 |
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changeset
|
1325 dst = zcycles(dst, 1); |
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changeset
|
1326 } |
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changeset
|
1327 dst = btr_ir(dst, bit, src_op.base, size); |
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changeset
|
1328 if (inst->reg != Z80_USE_IMMED) { |
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changeset
|
1329 if (size == SZ_W) { |
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diff
changeset
|
1330 if (dst_op.base >= R8) { |
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changeset
|
1331 dst = ror_ir(dst, 8, src_op.base, SZ_W); |
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changeset
|
1332 dst = mov_rr(dst, opts->regs[z80_low_reg(inst->ea_reg)], dst_op.base, SZ_B); |
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diff
changeset
|
1333 dst = ror_ir(dst, 8, src_op.base, SZ_W); |
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diff
changeset
|
1334 } else { |
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Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1335 dst = mov_rr(dst, opts->regs[inst->ea_reg], dst_op.base, SZ_B); |
505
b7b7a1cab44a
The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1336 } |
308
e0e81551fd7e
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Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1337 } else { |
e0e81551fd7e
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Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1338 dst = mov_rr(dst, src_op.base, dst_op.base, SZ_B); |
e0e81551fd7e
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Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1339 } |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1340 } |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
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|
1341 if (inst->addr_mode != Z80_REG) { |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1342 dst = z80_save_result(dst, inst); |
299
42e1a986f2d0
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Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1343 if (inst->reg != Z80_USE_IMMED) { |
42e1a986f2d0
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Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1344 dst = z80_save_reg(dst, inst, opts); |
42e1a986f2d0
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Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1345 } |
247
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1346 } |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1347 break; |
308
e0e81551fd7e
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Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1348 } |
236
19fb3523a9e5
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235
diff
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|
1349 case Z80_JP: { |
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235
diff
changeset
|
1350 cycles = 4; |
506
a3b48a57e847
Fix timing of certain ld and jp instructions in the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
505
diff
changeset
|
1351 if (inst->addr_mode != Z80_REG_INDIRECT) { |
236
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235
diff
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|
1352 cycles += 6; |
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235
diff
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|
1353 } else if(inst->ea_reg == Z80_IX || inst->ea_reg == Z80_IY) { |
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diff
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|
1354 cycles += 4; |
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diff
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|
1355 } |
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235
diff
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|
1356 dst = zcycles(dst, cycles); |
239
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
1357 if (inst->addr_mode != Z80_REG_INDIRECT && inst->immed < 0x4000) { |
236
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235
diff
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|
1358 uint8_t * call_dst = z80_get_native_address(context, inst->immed); |
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235
diff
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|
1359 if (!call_dst) { |
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235
diff
changeset
|
1360 opts->deferred = defer_address(opts->deferred, inst->immed, dst + 1); |
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235
diff
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|
1361 //fake address to force large displacement |
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235
diff
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|
1362 call_dst = dst + 256; |
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235
diff
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|
1363 } |
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235
diff
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|
1364 dst = jmp(dst, call_dst); |
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235
diff
changeset
|
1365 } else { |
239
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
1366 if (inst->addr_mode == Z80_REG_INDIRECT) { |
236
19fb3523a9e5
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diff
changeset
|
1367 dst = mov_rr(dst, opts->regs[inst->ea_reg], SCRATCH1, SZ_W); |
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235
diff
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|
1368 } else { |
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235
diff
changeset
|
1369 dst = mov_ir(dst, inst->immed, SCRATCH1, SZ_W); |
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235
diff
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|
1370 } |
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diff
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|
1371 dst = call(dst, (uint8_t *)z80_native_addr); |
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235
diff
changeset
|
1372 dst = jmp_r(dst, SCRATCH1); |
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parents:
235
diff
changeset
|
1373 } |
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parents:
235
diff
changeset
|
1374 break; |
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parents:
235
diff
changeset
|
1375 } |
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parents:
235
diff
changeset
|
1376 case Z80_JPCC: { |
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235
diff
changeset
|
1377 dst = zcycles(dst, 7);//T States: 4,3 |
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Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1378 uint8_t cond = CC_Z; |
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235
diff
changeset
|
1379 switch (inst->reg) |
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235
diff
changeset
|
1380 { |
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235
diff
changeset
|
1381 case Z80_CC_NZ: |
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parents:
235
diff
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|
1382 cond = CC_NZ; |
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235
diff
changeset
|
1383 case Z80_CC_Z: |
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235
diff
changeset
|
1384 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_Z), SZ_B); |
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235
diff
changeset
|
1385 break; |
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235
diff
changeset
|
1386 case Z80_CC_NC: |
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235
diff
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|
1387 cond = CC_NZ; |
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parents:
235
diff
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|
1388 case Z80_CC_C: |
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235
diff
changeset
|
1389 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_C), SZ_B); |
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parents:
235
diff
changeset
|
1390 break; |
238
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1391 case Z80_CC_PO: |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1392 cond = CC_NZ; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1393 case Z80_CC_PE: |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1394 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_PV), SZ_B); |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1395 break; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1396 case Z80_CC_P: |
367
f20562f2a570
Fix P condition in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
366
diff
changeset
|
1397 cond = CC_NZ; |
238
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1398 case Z80_CC_M: |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1399 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_S), SZ_B); |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1400 break; |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
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parents:
235
diff
changeset
|
1401 } |
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Implement more Z80 instructions (untested)
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parents:
235
diff
changeset
|
1402 uint8_t *no_jump_off = dst+1; |
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Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1403 dst = jcc(dst, cond, dst+2); |
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Implement more Z80 instructions (untested)
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parents:
235
diff
changeset
|
1404 dst = zcycles(dst, 5);//T States: 5 |
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Mike Pavone <pavone@retrodev.com>
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235
diff
changeset
|
1405 uint16_t dest_addr = inst->immed; |
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235
diff
changeset
|
1406 if (dest_addr < 0x4000) { |
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235
diff
changeset
|
1407 uint8_t * call_dst = z80_get_native_address(context, dest_addr); |
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235
diff
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|
1408 if (!call_dst) { |
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235
diff
changeset
|
1409 opts->deferred = defer_address(opts->deferred, dest_addr, dst + 1); |
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235
diff
changeset
|
1410 //fake address to force large displacement |
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235
diff
changeset
|
1411 call_dst = dst + 256; |
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235
diff
changeset
|
1412 } |
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235
diff
changeset
|
1413 dst = jmp(dst, call_dst); |
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235
diff
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|
1414 } else { |
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235
diff
changeset
|
1415 dst = mov_ir(dst, dest_addr, SCRATCH1, SZ_W); |
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235
diff
changeset
|
1416 dst = call(dst, (uint8_t *)z80_native_addr); |
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235
diff
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|
1417 dst = jmp_r(dst, SCRATCH1); |
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235
diff
changeset
|
1418 } |
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235
diff
changeset
|
1419 *no_jump_off = dst - (no_jump_off+1); |
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235
diff
changeset
|
1420 break; |
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235
diff
changeset
|
1421 } |
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235
diff
changeset
|
1422 case Z80_JR: { |
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235
diff
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|
1423 dst = zcycles(dst, 12);//T States: 4,3,5 |
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235
diff
changeset
|
1424 uint16_t dest_addr = address + inst->immed + 2; |
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235
diff
changeset
|
1425 if (dest_addr < 0x4000) { |
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235
diff
changeset
|
1426 uint8_t * call_dst = z80_get_native_address(context, dest_addr); |
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235
diff
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|
1427 if (!call_dst) { |
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235
diff
changeset
|
1428 opts->deferred = defer_address(opts->deferred, dest_addr, dst + 1); |
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diff
changeset
|
1429 //fake address to force large displacement |
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235
diff
changeset
|
1430 call_dst = dst + 256; |
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235
diff
changeset
|
1431 } |
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diff
changeset
|
1432 dst = jmp(dst, call_dst); |
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235
diff
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|
1433 } else { |
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diff
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|
1434 dst = mov_ir(dst, dest_addr, SCRATCH1, SZ_W); |
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diff
changeset
|
1435 dst = call(dst, (uint8_t *)z80_native_addr); |
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235
diff
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|
1436 dst = jmp_r(dst, SCRATCH1); |
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diff
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|
1437 } |
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diff
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|
1438 break; |
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diff
changeset
|
1439 } |
235
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213
diff
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|
1440 case Z80_JRCC: { |
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diff
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|
1441 dst = zcycles(dst, 7);//T States: 4,3 |
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213
diff
changeset
|
1442 uint8_t cond = CC_Z; |
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213
diff
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|
1443 switch (inst->reg) |
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213
diff
changeset
|
1444 { |
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213
diff
changeset
|
1445 case Z80_CC_NZ: |
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changeset
|
1446 cond = CC_NZ; |
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|
1447 case Z80_CC_Z: |
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diff
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|
1448 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_Z), SZ_B); |
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Get Z80 core working for simple programs
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213
diff
changeset
|
1449 break; |
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Get Z80 core working for simple programs
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diff
changeset
|
1450 case Z80_CC_NC: |
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Get Z80 core working for simple programs
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213
diff
changeset
|
1451 cond = CC_NZ; |
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Get Z80 core working for simple programs
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213
diff
changeset
|
1452 case Z80_CC_C: |
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Get Z80 core working for simple programs
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diff
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|
1453 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_C), SZ_B); |
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Get Z80 core working for simple programs
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213
diff
changeset
|
1454 break; |
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Get Z80 core working for simple programs
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213
diff
changeset
|
1455 } |
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Get Z80 core working for simple programs
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213
diff
changeset
|
1456 uint8_t *no_jump_off = dst+1; |
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Get Z80 core working for simple programs
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213
diff
changeset
|
1457 dst = jcc(dst, cond, dst+2); |
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Get Z80 core working for simple programs
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213
diff
changeset
|
1458 dst = zcycles(dst, 5);//T States: 5 |
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Get Z80 core working for simple programs
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213
diff
changeset
|
1459 uint16_t dest_addr = address + inst->immed + 2; |
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Get Z80 core working for simple programs
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213
diff
changeset
|
1460 if (dest_addr < 0x4000) { |
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Get Z80 core working for simple programs
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213
diff
changeset
|
1461 uint8_t * call_dst = z80_get_native_address(context, dest_addr); |
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Get Z80 core working for simple programs
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213
diff
changeset
|
1462 if (!call_dst) { |
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Get Z80 core working for simple programs
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213
diff
changeset
|
1463 opts->deferred = defer_address(opts->deferred, dest_addr, dst + 1); |
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Get Z80 core working for simple programs
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213
diff
changeset
|
1464 //fake address to force large displacement |
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Get Z80 core working for simple programs
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213
diff
changeset
|
1465 call_dst = dst + 256; |
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213
diff
changeset
|
1466 } |
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changeset
|
1467 dst = jmp(dst, call_dst); |
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Get Z80 core working for simple programs
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diff
changeset
|
1468 } else { |
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|
1469 dst = mov_ir(dst, dest_addr, SCRATCH1, SZ_W); |
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Get Z80 core working for simple programs
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|
1470 dst = call(dst, (uint8_t *)z80_native_addr); |
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|
1471 dst = jmp_r(dst, SCRATCH1); |
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changeset
|
1472 } |
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changeset
|
1473 *no_jump_off = dst - (no_jump_off+1); |
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Get Z80 core working for simple programs
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213
diff
changeset
|
1474 break; |
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diff
changeset
|
1475 } |
239
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
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|
1476 case Z80_DJNZ: |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
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|
1477 dst = zcycles(dst, 8);//T States: 5,3 |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
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changeset
|
1478 dst = sub_ir(dst, 1, opts->regs[Z80_B], SZ_B); |
a5bea9711a46
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238
diff
changeset
|
1479 uint8_t *no_jump_off = dst+1; |
a5bea9711a46
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238
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|
1480 dst = jcc(dst, CC_Z, dst+2); |
a5bea9711a46
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238
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|
1481 dst = zcycles(dst, 5);//T States: 5 |
a5bea9711a46
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238
diff
changeset
|
1482 uint16_t dest_addr = address + inst->immed + 2; |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
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238
diff
changeset
|
1483 if (dest_addr < 0x4000) { |
a5bea9711a46
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238
diff
changeset
|
1484 uint8_t * call_dst = z80_get_native_address(context, dest_addr); |
a5bea9711a46
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diff
changeset
|
1485 if (!call_dst) { |
a5bea9711a46
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238
diff
changeset
|
1486 opts->deferred = defer_address(opts->deferred, dest_addr, dst + 1); |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
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238
diff
changeset
|
1487 //fake address to force large displacement |
a5bea9711a46
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Mike Pavone <pavone@retrodev.com>
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238
diff
changeset
|
1488 call_dst = dst + 256; |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
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238
diff
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|
1489 } |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
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238
diff
changeset
|
1490 dst = jmp(dst, call_dst); |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
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238
diff
changeset
|
1491 } else { |
a5bea9711a46
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Mike Pavone <pavone@retrodev.com>
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238
diff
changeset
|
1492 dst = mov_ir(dst, dest_addr, SCRATCH1, SZ_W); |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
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238
diff
changeset
|
1493 dst = call(dst, (uint8_t *)z80_native_addr); |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
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238
diff
changeset
|
1494 dst = jmp_r(dst, SCRATCH1); |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
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238
diff
changeset
|
1495 } |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
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238
diff
changeset
|
1496 *no_jump_off = dst - (no_jump_off+1); |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
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238
diff
changeset
|
1497 break; |
235
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Get Z80 core working for simple programs
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213
diff
changeset
|
1498 case Z80_CALL: { |
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Get Z80 core working for simple programs
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diff
changeset
|
1499 dst = zcycles(dst, 11);//T States: 4,3,4 |
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Get Z80 core working for simple programs
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213
diff
changeset
|
1500 dst = sub_ir(dst, 2, opts->regs[Z80_SP], SZ_W); |
253
3b34deba4ca0
Squashing some bugs introduced when I switched the register assignments for z80_write_byte around.
Mike Pavone <pavone@retrodev.com>
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252
diff
changeset
|
1501 dst = mov_ir(dst, address + 3, SCRATCH1, SZ_W); |
3b34deba4ca0
Squashing some bugs introduced when I switched the register assignments for z80_write_byte around.
Mike Pavone <pavone@retrodev.com>
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252
diff
changeset
|
1502 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH2, SZ_W); |
235
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Get Z80 core working for simple programs
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213
diff
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|
1503 dst = call(dst, (uint8_t *)z80_write_word_highfirst);//T States: 3, 3 |
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Get Z80 core working for simple programs
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213
diff
changeset
|
1504 if (inst->immed < 0x4000) { |
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Get Z80 core working for simple programs
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213
diff
changeset
|
1505 uint8_t * call_dst = z80_get_native_address(context, inst->immed); |
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Get Z80 core working for simple programs
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213
diff
changeset
|
1506 if (!call_dst) { |
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Get Z80 core working for simple programs
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213
diff
changeset
|
1507 opts->deferred = defer_address(opts->deferred, inst->immed, dst + 1); |
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Get Z80 core working for simple programs
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213
diff
changeset
|
1508 //fake address to force large displacement |
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Get Z80 core working for simple programs
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213
diff
changeset
|
1509 call_dst = dst + 256; |
d9bf8e61c33c
Get Z80 core working for simple programs
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213
diff
changeset
|
1510 } |
d9bf8e61c33c
Get Z80 core working for simple programs
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213
diff
changeset
|
1511 dst = jmp(dst, call_dst); |
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Get Z80 core working for simple programs
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213
diff
changeset
|
1512 } else { |
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Get Z80 core working for simple programs
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213
diff
changeset
|
1513 dst = mov_ir(dst, inst->immed, SCRATCH1, SZ_W); |
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Get Z80 core working for simple programs
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213
diff
changeset
|
1514 dst = call(dst, (uint8_t *)z80_native_addr); |
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Get Z80 core working for simple programs
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213
diff
changeset
|
1515 dst = jmp_r(dst, SCRATCH1); |
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Get Z80 core working for simple programs
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213
diff
changeset
|
1516 } |
d9bf8e61c33c
Get Z80 core working for simple programs
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213
diff
changeset
|
1517 break; |
d9bf8e61c33c
Get Z80 core working for simple programs
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213
diff
changeset
|
1518 } |
238
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1519 case Z80_CALLCC: |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1520 dst = zcycles(dst, 10);//T States: 4,3,3 (false case) |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
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236
diff
changeset
|
1521 uint8_t cond = CC_Z; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
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236
diff
changeset
|
1522 switch (inst->reg) |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1523 { |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1524 case Z80_CC_NZ: |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
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236
diff
changeset
|
1525 cond = CC_NZ; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1526 case Z80_CC_Z: |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
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236
diff
changeset
|
1527 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_Z), SZ_B); |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
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236
diff
changeset
|
1528 break; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1529 case Z80_CC_NC: |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
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236
diff
changeset
|
1530 cond = CC_NZ; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
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236
diff
changeset
|
1531 case Z80_CC_C: |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
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236
diff
changeset
|
1532 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_C), SZ_B); |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
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236
diff
changeset
|
1533 break; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1534 case Z80_CC_PO: |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
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236
diff
changeset
|
1535 cond = CC_NZ; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
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236
diff
changeset
|
1536 case Z80_CC_PE: |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
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236
diff
changeset
|
1537 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_PV), SZ_B); |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
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236
diff
changeset
|
1538 break; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
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parents:
236
diff
changeset
|
1539 case Z80_CC_P: |
367
f20562f2a570
Fix P condition in Z80 core
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parents:
366
diff
changeset
|
1540 cond = CC_NZ; |
238
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
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236
diff
changeset
|
1541 case Z80_CC_M: |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
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diff
changeset
|
1542 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_S), SZ_B); |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
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236
diff
changeset
|
1543 break; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
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236
diff
changeset
|
1544 } |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
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236
diff
changeset
|
1545 uint8_t *no_call_off = dst+1; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
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236
diff
changeset
|
1546 dst = jcc(dst, cond, dst+2); |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
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236
diff
changeset
|
1547 dst = zcycles(dst, 1);//Last of the above T states takes an extra cycle in the true case |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
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236
diff
changeset
|
1548 dst = sub_ir(dst, 2, opts->regs[Z80_SP], SZ_W); |
253
3b34deba4ca0
Squashing some bugs introduced when I switched the register assignments for z80_write_byte around.
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252
diff
changeset
|
1549 dst = mov_ir(dst, address + 3, SCRATCH1, SZ_W); |
3b34deba4ca0
Squashing some bugs introduced when I switched the register assignments for z80_write_byte around.
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252
diff
changeset
|
1550 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH2, SZ_W); |
238
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
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236
diff
changeset
|
1551 dst = call(dst, (uint8_t *)z80_write_word_highfirst);//T States: 3, 3 |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1552 if (inst->immed < 0x4000) { |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1553 uint8_t * call_dst = z80_get_native_address(context, inst->immed); |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1554 if (!call_dst) { |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1555 opts->deferred = defer_address(opts->deferred, inst->immed, dst + 1); |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1556 //fake address to force large displacement |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1557 call_dst = dst + 256; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1558 } |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1559 dst = jmp(dst, call_dst); |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1560 } else { |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1561 dst = mov_ir(dst, inst->immed, SCRATCH1, SZ_W); |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1562 dst = call(dst, (uint8_t *)z80_native_addr); |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1563 dst = jmp_r(dst, SCRATCH1); |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1564 } |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1565 *no_call_off = dst - (no_call_off+1); |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1566 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1567 case Z80_RET: |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1568 dst = zcycles(dst, 4);//T States: 4 |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1569 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH1, SZ_W); |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1570 dst = call(dst, (uint8_t *)z80_read_word);//T STates: 3, 3 |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1571 dst = add_ir(dst, 2, opts->regs[Z80_SP], SZ_W); |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1572 dst = call(dst, (uint8_t *)z80_native_addr); |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1573 dst = jmp_r(dst, SCRATCH1); |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1574 break; |
246
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1575 case Z80_RETCC: { |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1576 dst = zcycles(dst, 5);//T States: 5 |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1577 uint8_t cond = CC_Z; |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1578 switch (inst->reg) |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1579 { |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1580 case Z80_CC_NZ: |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1581 cond = CC_NZ; |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1582 case Z80_CC_Z: |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1583 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_Z), SZ_B); |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1584 break; |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1585 case Z80_CC_NC: |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1586 cond = CC_NZ; |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1587 case Z80_CC_C: |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1588 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_C), SZ_B); |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1589 break; |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1590 case Z80_CC_PO: |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1591 cond = CC_NZ; |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1592 case Z80_CC_PE: |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1593 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_PV), SZ_B); |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1594 break; |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1595 case Z80_CC_P: |
367
f20562f2a570
Fix P condition in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
366
diff
changeset
|
1596 cond = CC_NZ; |
246
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1597 case Z80_CC_M: |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1598 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_S), SZ_B); |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1599 break; |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1600 } |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1601 uint8_t *no_call_off = dst+1; |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1602 dst = jcc(dst, cond, dst+2); |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1603 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH1, SZ_W); |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1604 dst = call(dst, (uint8_t *)z80_read_word);//T STates: 3, 3 |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1605 dst = add_ir(dst, 2, opts->regs[Z80_SP], SZ_W); |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1606 dst = call(dst, (uint8_t *)z80_native_addr); |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1607 dst = jmp_r(dst, SCRATCH1); |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1608 *no_call_off = dst - (no_call_off+1); |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1609 break; |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1610 } |
283
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1611 case Z80_RETI: |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1612 //For some systems, this may need a callback for signalling interrupt routine completion |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1613 dst = zcycles(dst, 8);//T States: 4, 4 |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1614 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH1, SZ_W); |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1615 dst = call(dst, (uint8_t *)z80_read_word);//T STates: 3, 3 |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1616 dst = add_ir(dst, 2, opts->regs[Z80_SP], SZ_W); |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1617 dst = call(dst, (uint8_t *)z80_native_addr); |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1618 dst = jmp_r(dst, SCRATCH1); |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1619 break; |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1620 case Z80_RETN: |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1621 dst = zcycles(dst, 8);//T States: 4, 4 |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1622 dst = mov_rdisp8r(dst, CONTEXT, offsetof(z80_context, iff2), SCRATCH2, SZ_B); |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1623 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH1, SZ_W); |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1624 dst = mov_rrdisp8(dst, SCRATCH2, CONTEXT, offsetof(z80_context, iff1), SZ_B); |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1625 dst = call(dst, (uint8_t *)z80_read_word);//T STates: 3, 3 |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1626 dst = add_ir(dst, 2, opts->regs[Z80_SP], SZ_W); |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1627 dst = call(dst, (uint8_t *)z80_native_addr); |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1628 dst = jmp_r(dst, SCRATCH1); |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1629 break; |
241
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1630 case Z80_RST: { |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1631 //RST is basically CALL to an address in page 0 |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1632 dst = zcycles(dst, 5);//T States: 5 |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1633 dst = sub_ir(dst, 2, opts->regs[Z80_SP], SZ_W); |
315
684e71e9f0d0
Fix return address for RST
Mike Pavone <pavone@retrodev.com>
parents:
314
diff
changeset
|
1634 dst = mov_ir(dst, address + 1, SCRATCH1, SZ_W); |
253
3b34deba4ca0
Squashing some bugs introduced when I switched the register assignments for z80_write_byte around.
Mike Pavone <pavone@retrodev.com>
parents:
252
diff
changeset
|
1635 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH2, SZ_W); |
241
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1636 dst = call(dst, (uint8_t *)z80_write_word_highfirst);//T States: 3, 3 |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1637 uint8_t * call_dst = z80_get_native_address(context, inst->immed); |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1638 if (!call_dst) { |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1639 opts->deferred = defer_address(opts->deferred, inst->immed, dst + 1); |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1640 //fake address to force large displacement |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1641 call_dst = dst + 256; |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1642 } |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1643 dst = jmp(dst, call_dst); |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1644 break; |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1645 } |
284
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1646 case Z80_IN: |
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1647 dst = zcycles(dst, inst->reg == Z80_A ? 7 : 8);//T States: 4 3/4 |
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1648 if (inst->addr_mode == Z80_IMMED_INDIRECT) { |
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1649 dst = mov_ir(dst, inst->immed, SCRATCH1, SZ_B); |
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1650 } else { |
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1651 dst = mov_rr(dst, opts->regs[Z80_C], SCRATCH1, SZ_B); |
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1652 } |
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1653 dst = call(dst, (uint8_t *)z80_io_read); |
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1654 translate_z80_reg(inst, &dst_op, dst, opts); |
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1655 dst = mov_rr(dst, SCRATCH1, dst_op.base, SZ_B); |
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1656 dst = z80_save_reg(dst, inst, opts); |
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1657 break; |
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1658 /*case Z80_INI: |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1659 case Z80_INIR: |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1660 case Z80_IND: |
284
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1661 case Z80_INDR:*/ |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1662 case Z80_OUT: |
284
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1663 dst = zcycles(dst, inst->reg == Z80_A ? 7 : 8);//T States: 4 3/4 |
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1664 if ((inst->addr_mode & 0x1F) == Z80_IMMED_INDIRECT) { |
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1665 dst = mov_ir(dst, inst->immed, SCRATCH2, SZ_B); |
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1666 } else { |
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1667 dst = mov_rr(dst, opts->regs[Z80_C], SCRATCH2, SZ_B); |
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1668 } |
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1669 translate_z80_reg(inst, &src_op, dst, opts); |
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1670 dst = mov_rr(dst, dst_op.base, SCRATCH1, SZ_B); |
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1671 dst = call(dst, (uint8_t *)z80_io_write); |
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1672 dst = z80_save_reg(dst, inst, opts); |
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1673 break; |
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1674 /*case Z80_OUTI: |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1675 case Z80_OTIR: |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1676 case Z80_OUTD: |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1677 case Z80_OTDR:*/ |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1678 default: { |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1679 char disbuf[80]; |
314
54c0e5f22198
Show absolute addresses for JR, JRCC and DJNZ in Z80 disassembler
Mike Pavone <pavone@retrodev.com>
parents:
313
diff
changeset
|
1680 z80_disasm(inst, disbuf, address); |
424
7e8e179116af
Add support for loading GST format savestates
Mike Pavone <pavone@retrodev.com>
parents:
420
diff
changeset
|
1681 fprintf(stderr, "unimplemented instruction: %s at %X\n", disbuf, address); |
259
d9417261366f
Fix a remaining z80_write reg swap bug. Properly initialize the native map slots. Reset appropriate regs when z80_reset is called.
Mike Pavone <pavone@retrodev.com>
parents:
257
diff
changeset
|
1682 FILE * f = fopen("zram.bin", "wb"); |
d9417261366f
Fix a remaining z80_write reg swap bug. Properly initialize the native map slots. Reset appropriate regs when z80_reset is called.
Mike Pavone <pavone@retrodev.com>
parents:
257
diff
changeset
|
1683 fwrite(context->mem_pointers[0], 1, 8 * 1024, f); |
d9417261366f
Fix a remaining z80_write reg swap bug. Properly initialize the native map slots. Reset appropriate regs when z80_reset is called.
Mike Pavone <pavone@retrodev.com>
parents:
257
diff
changeset
|
1684 fclose(f); |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1685 exit(1); |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1686 } |
235
d9bf8e61c33c
Get Z80 core working for simple programs
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parents:
213
diff
changeset
|
1687 } |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1688 return dst; |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1689 } |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1690 |
627
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1691 uint8_t * z80_interp_handler(uint8_t opcode, z80_context * context) |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1692 { |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1693 if (!context->interp_code[opcode]) { |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1694 if (opcode == 0xCB || (opcode >= 0xDD && opcode & 0xF == 0xD)) { |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1695 fprintf(stderr, "Encountered prefix byte %X at address %X. Z80 interpeter doesn't support those yet.", opcode, context->pc); |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1696 exit(1); |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1697 } |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1698 uint8_t codebuf[8]; |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1699 memset(codebuf, 0, sizeof(codebuf)); |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1700 codebuf[0] = opcode; |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1701 z80inst inst; |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1702 uint8_t * after = z80_decode(codebuf, &inst); |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1703 if (after - codebuf > 1) { |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1704 fprintf(stderr, "Encountered multi-byte Z80 instruction at %X. Z80 interpeter doesn't support those yet.", context->pc); |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1705 exit(1); |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1706 } |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1707 x86_z80_options * opts = context->options; |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1708 if (opts->code_end - opts->cur_code < ZMAX_NATIVE_SIZE) { |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1709 size_t size = 1024*1024; |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1710 opts->cur_code = alloc_code(&size); |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1711 opts->code_end = opts->cur_code + size; |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1712 } |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1713 context->interp_code[opcode] = opts->cur_code; |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1714 opts->cur_code = translate_z80inst(&inst, opts->cur_code, context, 0, 1); |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1715 opts->cur_code = mov_rdisp8r(opts->cur_code, CONTEXT, offsetof(z80_context, pc), SCRATCH1, SZ_W); |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1716 opts->cur_code = add_ir(opts->cur_code, after - codebuf, SCRATCH1, SZ_W); |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1717 opts->cur_code = call(opts->cur_code, (uint8_t *)z80_native_addr); |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1718 opts->cur_code = jmp_r(opts->cur_code, SCRATCH1); |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1719 } |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1720 return context->interp_code[opcode]; |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1721 } |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1722 |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1723 uint8_t * z80_make_interp_stub(z80_context * context, uint16_t address) |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1724 { |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1725 x86_z80_options *opts = context->options; |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1726 uint8_t *dst = opts->cur_code; |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1727 //TODO: make this play well with the breakpoint code |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1728 dst = mov_ir(dst, address, SCRATCH1, SZ_W); |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1729 dst = call(dst, (uint8_t *)z80_read_byte); |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1730 //normal opcode fetch is already factored into instruction timing |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1731 //back out the base 3 cycles from a read here |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1732 //not quite perfect, but it will have to do for now |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1733 dst = sub_ir(dst, 3, ZCYCLES, SZ_D); |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1734 dst = z80_check_cycles_int(dst, address); |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1735 dst = call(dst, (uint8_t *)z80_save_context); |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1736 dst = mov_rr(dst, SCRATCH1, RDI, SZ_B); |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1737 dst = mov_irdisp8(dst, address, CONTEXT, offsetof(z80_context, pc), SZ_W); |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1738 dst = push_r(dst, CONTEXT); |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1739 dst = call(dst, (uint8_t *)z80_interp_handler); |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1740 dst = mov_rr(dst, RAX, SCRATCH1, SZ_Q); |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1741 dst = pop_r(dst, CONTEXT); |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1742 dst = call(dst, (uint8_t *)z80_load_context); |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1743 dst = jmp_r(dst, SCRATCH1); |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1744 opts->code_end = dst; |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1745 return dst; |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1746 } |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1747 |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1748 |
235
d9bf8e61c33c
Get Z80 core working for simple programs
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parents:
213
diff
changeset
|
1749 uint8_t * z80_get_native_address(z80_context * context, uint32_t address) |
d9bf8e61c33c
Get Z80 core working for simple programs
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parents:
213
diff
changeset
|
1750 { |
d9bf8e61c33c
Get Z80 core working for simple programs
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parents:
213
diff
changeset
|
1751 native_map_slot *map; |
d9bf8e61c33c
Get Z80 core working for simple programs
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parents:
213
diff
changeset
|
1752 if (address < 0x4000) { |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1753 address &= 0x1FFF; |
d9bf8e61c33c
Get Z80 core working for simple programs
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parents:
213
diff
changeset
|
1754 map = context->static_code_map; |
d9bf8e61c33c
Get Z80 core working for simple programs
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parents:
213
diff
changeset
|
1755 } else { |
627
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1756 address -= 0x4000; |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1757 map = context->banked_code_map; |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1758 } |
268
6c2d7e003a55
Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset
Mike Pavone <pavone@retrodev.com>
parents:
267
diff
changeset
|
1759 if (!map->base || !map->offsets || map->offsets[address] == INVALID_OFFSET || map->offsets[address] == EXTENSION_WORD) { |
313
a13329645ea3
Fix terminal instruction detection in disassembler
Mike Pavone <pavone@retrodev.com>
parents:
312
diff
changeset
|
1760 //dprintf("z80_get_native_address: %X NULL\n", address); |
235
d9bf8e61c33c
Get Z80 core working for simple programs
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parents:
213
diff
changeset
|
1761 return NULL; |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1762 } |
313
a13329645ea3
Fix terminal instruction detection in disassembler
Mike Pavone <pavone@retrodev.com>
parents:
312
diff
changeset
|
1763 //dprintf("z80_get_native_address: %X %p\n", address, map->base + map->offsets[address]); |
235
d9bf8e61c33c
Get Z80 core working for simple programs
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parents:
213
diff
changeset
|
1764 return map->base + map->offsets[address]; |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1765 } |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1766 |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1767 uint8_t z80_get_native_inst_size(x86_z80_options * opts, uint32_t address) |
235
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Get Z80 core working for simple programs
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213
diff
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|
1768 { |
627
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Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
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626
diff
changeset
|
1769 //TODO: Fix for addresses >= 0x4000 |
252
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Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1770 if (address >= 0x4000) { |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1771 return 0; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1772 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1773 return opts->ram_inst_sizes[address & 0x1FFF]; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1774 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1775 |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
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250
diff
changeset
|
1776 void z80_map_native_address(z80_context * context, uint32_t address, uint8_t * native_address, uint8_t size, uint8_t native_size) |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
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250
diff
changeset
|
1777 { |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1778 uint32_t orig_address = address; |
235
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Get Z80 core working for simple programs
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213
diff
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|
1779 native_map_slot *map; |
252
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Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
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250
diff
changeset
|
1780 x86_z80_options * opts = context->options; |
235
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Get Z80 core working for simple programs
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diff
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|
1781 if (address < 0x4000) { |
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Get Z80 core working for simple programs
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diff
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|
1782 address &= 0x1FFF; |
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Get Z80 core working for simple programs
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diff
changeset
|
1783 map = context->static_code_map; |
252
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Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
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diff
changeset
|
1784 opts->ram_inst_sizes[address] = native_size; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
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diff
changeset
|
1785 context->ram_code_flags[(address & 0x1C00) >> 10] |= 1 << ((address & 0x380) >> 7); |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1786 context->ram_code_flags[((address + size) & 0x1C00) >> 10] |= 1 << (((address + size) & 0x380) >> 7); |
627
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
1787 } else { |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
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626
diff
changeset
|
1788 //HERE |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
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diff
changeset
|
1789 address -= 0x4000; |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
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diff
changeset
|
1790 map = context->banked_code_map; |
235
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Get Z80 core working for simple programs
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|
1791 if (!map->offsets) { |
627
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Michael Pavone <pavone@retrodev.com>
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diff
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|
1792 map->offsets = malloc(sizeof(int32_t) * 0xC000); |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
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|
1793 memset(map->offsets, 0xFF, sizeof(int32_t) * 0xC000); |
235
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Get Z80 core working for simple programs
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|
1794 } |
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Get Z80 core working for simple programs
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213
diff
changeset
|
1795 } |
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Get Z80 core working for simple programs
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|
1796 if (!map->base) { |
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|
1797 map->base = native_address; |
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|
1798 } |
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diff
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|
1799 map->offsets[address] = native_address - map->base; |
253
3b34deba4ca0
Squashing some bugs introduced when I switched the register assignments for z80_write_byte around.
Mike Pavone <pavone@retrodev.com>
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252
diff
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|
1800 for(--size, orig_address++; size; --size, orig_address++) { |
252
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diff
changeset
|
1801 address = orig_address; |
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|
1802 if (address < 0x4000) { |
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changeset
|
1803 address &= 0x1FFF; |
63b9a500a00b
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diff
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|
1804 map = context->static_code_map; |
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diff
changeset
|
1805 } else { |
627
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Michael Pavone <pavone@retrodev.com>
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diff
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|
1806 address -= 0x4000; |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
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diff
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|
1807 map = context->banked_code_map; |
252
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|
1808 } |
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Mike Pavone <pavone@retrodev.com>
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diff
changeset
|
1809 if (!map->offsets) { |
627
c5820734a5b6
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Michael Pavone <pavone@retrodev.com>
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diff
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|
1810 map->offsets = malloc(sizeof(int32_t) * 0xC000); |
c5820734a5b6
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Michael Pavone <pavone@retrodev.com>
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|
1811 memset(map->offsets, 0xFF, sizeof(int32_t) * 0xC000); |
252
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|
1812 } |
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Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
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diff
changeset
|
1813 map->offsets[address] = EXTENSION_WORD; |
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|
1814 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
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|
1815 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
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changeset
|
1816 |
63b9a500a00b
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|
1817 #define INVALID_INSTRUCTION_START 0xFEEDFEED |
63b9a500a00b
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|
1818 |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
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|
1819 uint32_t z80_get_instruction_start(native_map_slot * static_code_map, uint32_t address) |
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Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
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|
1820 { |
627
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Michael Pavone <pavone@retrodev.com>
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diff
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|
1821 //TODO: Fixme for address >= 0x4000 |
252
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|
1822 if (!static_code_map->base || address >= 0x4000) { |
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Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
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diff
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|
1823 return INVALID_INSTRUCTION_START; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
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diff
changeset
|
1824 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
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250
diff
changeset
|
1825 address &= 0x1FFF; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1826 if (static_code_map->offsets[address] == INVALID_OFFSET) { |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
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250
diff
changeset
|
1827 return INVALID_INSTRUCTION_START; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
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250
diff
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|
1828 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
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diff
changeset
|
1829 while (static_code_map->offsets[address] == EXTENSION_WORD) { |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
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diff
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|
1830 --address; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
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250
diff
changeset
|
1831 address &= 0x1FFF; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
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250
diff
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|
1832 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1833 return address; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
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250
diff
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|
1834 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
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250
diff
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|
1835 |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
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250
diff
changeset
|
1836 z80_context * z80_handle_code_write(uint32_t address, z80_context * context) |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
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250
diff
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|
1837 { |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
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250
diff
changeset
|
1838 uint32_t inst_start = z80_get_instruction_start(context->static_code_map, address); |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
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diff
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|
1839 if (inst_start != INVALID_INSTRUCTION_START) { |
63b9a500a00b
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|
1840 uint8_t * dst = z80_get_native_address(context, inst_start); |
268
6c2d7e003a55
Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset
Mike Pavone <pavone@retrodev.com>
parents:
267
diff
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|
1841 dprintf("patching code at %p for Z80 instruction at %X due to write to %X\n", dst, inst_start, address); |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
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diff
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|
1842 dst = mov_ir(dst, inst_start, SCRATCH1, SZ_D); |
390
561fe3ea3fc8
Use a call instruction to figure out the original native address when retranslating so that it does not get lost when the byte transforms from a instruction word to extension word
Mike Pavone <pavone@retrodev.com>
parents:
389
diff
changeset
|
1843 dst = call(dst, (uint8_t *)z80_retrans_stub); |
252
63b9a500a00b
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|
1844 } |
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|
1845 return context; |
63b9a500a00b
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diff
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|
1846 } |
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250
diff
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|
1847 |
264
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|
1848 uint8_t * z80_get_native_address_trans(z80_context * context, uint32_t address) |
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262
diff
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|
1849 { |
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262
diff
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|
1850 uint8_t * addr = z80_get_native_address(context, address); |
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262
diff
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|
1851 if (!addr) { |
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diff
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|
1852 translate_z80_stream(context, address); |
8fd6652e56f8
Fix a crash bug in instruction retranslation
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262
diff
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|
1853 addr = z80_get_native_address(context, address); |
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262
diff
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|
1854 if (!addr) { |
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Fix a crash bug in instruction retranslation
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262
diff
changeset
|
1855 printf("Failed to translate %X to native code\n", address); |
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Fix a crash bug in instruction retranslation
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262
diff
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|
1856 } |
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262
diff
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|
1857 } |
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Fix a crash bug in instruction retranslation
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262
diff
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|
1858 return addr; |
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262
diff
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|
1859 } |
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262
diff
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|
1860 |
266
376df762ddf5
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264
diff
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|
1861 void z80_handle_deferred(z80_context * context) |
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
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264
diff
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|
1862 { |
376df762ddf5
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Mike Pavone <pavone@retrodev.com>
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264
diff
changeset
|
1863 x86_z80_options * opts = context->options; |
376df762ddf5
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parents:
264
diff
changeset
|
1864 process_deferred(&opts->deferred, context, (native_addr_func)z80_get_native_address); |
376df762ddf5
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parents:
264
diff
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|
1865 if (opts->deferred) { |
376df762ddf5
Fix some more retranslation bugs in the Z80 core
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parents:
264
diff
changeset
|
1866 translate_z80_stream(context, opts->deferred->address); |
376df762ddf5
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parents:
264
diff
changeset
|
1867 } |
376df762ddf5
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264
diff
changeset
|
1868 } |
376df762ddf5
Fix some more retranslation bugs in the Z80 core
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264
diff
changeset
|
1869 |
390
561fe3ea3fc8
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diff
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|
1870 void * z80_retranslate_inst(uint32_t address, z80_context * context, uint8_t * orig_start) |
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|
1871 { |
266
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diff
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|
1872 char disbuf[80]; |
252
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diff
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|
1873 x86_z80_options * opts = context->options; |
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|
1874 uint8_t orig_size = z80_get_native_inst_size(opts, address); |
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|
1875 uint32_t orig = address; |
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diff
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|
1876 address &= 0x1FFF; |
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|
1877 uint8_t * dst = opts->cur_code; |
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|
1878 uint8_t * dst_end = opts->code_end; |
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|
1879 uint8_t *after, *inst = context->mem_pointers[0] + address; |
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1880 z80inst instbuf; |
268
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1881 dprintf("Retranslating code at Z80 address %X, native address %p\n", address, orig_start); |
252
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1882 after = z80_decode(inst, &instbuf); |
268
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|
1883 #ifdef DO_DEBUG_PRINT |
314
54c0e5f22198
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diff
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|
1884 z80_disasm(&instbuf, disbuf, address); |
266
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|
1885 if (instbuf.op == Z80_NOP) { |
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|
1886 printf("%X\t%s(%d)\n", address, disbuf, instbuf.immed); |
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1887 } else { |
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1888 printf("%X\t%s\n", address, disbuf); |
267
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|
1889 } |
268
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|
1890 #endif |
252
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|
1891 if (orig_size != ZMAX_NATIVE_SIZE) { |
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1892 if (dst_end - dst < ZMAX_NATIVE_SIZE) { |
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|
1893 size_t size = 1024*1024; |
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|
1894 dst = alloc_code(&size); |
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|
1895 opts->code_end = dst_end = dst + size; |
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1896 opts->cur_code = dst; |
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1897 } |
282
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|
1898 deferred_addr * orig_deferred = opts->deferred; |
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|
1899 uint8_t * native_end = translate_z80inst(&instbuf, dst, context, address, 0); |
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1900 /* |
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1901 if ((native_end - dst) <= orig_size) { |
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1902 uint8_t * native_next = z80_get_native_address(context, address + after-inst); |
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1903 if (native_next && ((native_next == orig_start + orig_size) || (orig_size - (native_end - dst)) > 5)) { |
282
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1904 remove_deferred_until(&opts->deferred, orig_deferred); |
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1905 native_end = translate_z80inst(&instbuf, orig_start, context, address, 0); |
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1906 if (native_next == orig_start + orig_size && (native_next-native_end) < 2) { |
264
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1907 while (native_end < orig_start + orig_size) { |
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1908 *(native_end++) = 0x90; //NOP |
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1909 } |
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1910 } else { |
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1911 jmp(native_end, native_next); |
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1912 } |
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1913 z80_handle_deferred(context); |
264
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1914 return orig_start; |
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1915 } |
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1916 } |
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1917 */ |
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1918 z80_map_native_address(context, address, dst, after-inst, ZMAX_NATIVE_SIZE); |
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1919 opts->cur_code = dst+ZMAX_NATIVE_SIZE; |
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1920 jmp(orig_start, dst); |
283
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1921 if (!z80_is_terminal(&instbuf)) { |
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1922 jmp(native_end, z80_get_native_address_trans(context, address + after-inst)); |
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1923 } |
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1924 z80_handle_deferred(context); |
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1925 return dst; |
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1926 } else { |
627
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1927 dst = translate_z80inst(&instbuf, orig_start, context, address, 0); |
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1928 if (!z80_is_terminal(&instbuf)) { |
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1929 dst = jmp(dst, z80_get_native_address_trans(context, address + after-inst)); |
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1930 } |
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1931 z80_handle_deferred(context); |
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1932 return orig_start; |
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1933 } |
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1934 } |
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1935 |
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1936 void translate_z80_stream(z80_context * context, uint32_t address) |
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1937 { |
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1938 char disbuf[80]; |
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1939 if (z80_get_native_address(context, address)) { |
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1940 return; |
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1941 } |
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1942 x86_z80_options * opts = context->options; |
505
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The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
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1943 uint32_t start_address = address; |
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1944 uint8_t * encoded = NULL, *next; |
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1945 if (address < 0x4000) { |
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1946 encoded = context->mem_pointers[0] + (address & 0x1FFF); |
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1947 } |
627
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1948 |
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1949 while (encoded != NULL || address >= 0x4000) |
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1950 { |
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1951 z80inst inst; |
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1952 dprintf("translating Z80 code at address %X\n", address); |
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1953 do { |
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1954 if (opts->code_end-opts->cur_code < ZMAX_NATIVE_SIZE) { |
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1955 if (opts->code_end-opts->cur_code < 5) { |
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1956 puts("out of code memory, not enough space for jmp to next chunk"); |
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1957 exit(1); |
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1958 } |
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1959 size_t size = 1024*1024; |
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1960 opts->cur_code = alloc_code(&size); |
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1961 opts->code_end = opts->cur_code + size; |
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1962 jmp(opts->cur_code, opts->cur_code); |
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1963 } |
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1964 if (address >= 0x4000) { |
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1965 uint8_t *native_start = opts->cur_code; |
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1966 uint8_t *after = z80_make_interp_stub(context, address); |
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1967 z80_map_native_address(context, address, opts->cur_code, 1, after - native_start); |
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1968 break; |
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1969 } |
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1970 uint8_t * existing = z80_get_native_address(context, address); |
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1971 if (existing) { |
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1972 opts->cur_code = jmp(opts->cur_code, existing); |
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1973 break; |
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1974 } |
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1975 next = z80_decode(encoded, &inst); |
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1976 #ifdef DO_DEBUG_PRINT |
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1977 z80_disasm(&inst, disbuf, address); |
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1978 if (inst.op == Z80_NOP) { |
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1979 printf("%X\t%s(%d)\n", address, disbuf, inst.immed); |
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1980 } else { |
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1981 printf("%X\t%s\n", address, disbuf); |
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1982 } |
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1983 #endif |
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1984 uint8_t *after = translate_z80inst(&inst, opts->cur_code, context, address, 0); |
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1985 z80_map_native_address(context, address, opts->cur_code, next-encoded, after - opts->cur_code); |
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1986 opts->cur_code = after; |
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1987 address += next-encoded; |
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1988 if (address > 0xFFFF) { |
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1989 address &= 0xFFFF; |
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The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
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1990 |
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1991 } else { |
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1992 encoded = next; |
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1993 } |
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1994 } while (!z80_is_terminal(&inst)); |
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1995 process_deferred(&opts->deferred, context, (native_addr_func)z80_get_native_address); |
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1996 if (opts->deferred) { |
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1997 address = opts->deferred->address; |
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1998 dprintf("defferred address: %X\n", address); |
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1999 if (address < 0x4000) { |
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2000 encoded = context->mem_pointers[0] + (address & 0x1FFF); |
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2001 } else { |
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2002 encoded = NULL; |
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2003 } |
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2004 } else { |
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2005 encoded = NULL; |
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2006 address = 0; |
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2007 } |
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2008 } |
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2009 } |
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2010 |
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2011 void init_x86_z80_opts(x86_z80_options * options) |
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2012 { |
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2013 options->flags = 0; |
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2014 options->regs[Z80_B] = BH; |
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2015 options->regs[Z80_C] = RBX; |
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2016 options->regs[Z80_D] = CH; |
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2017 options->regs[Z80_E] = RCX; |
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2018 options->regs[Z80_H] = AH; |
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2019 options->regs[Z80_L] = RAX; |
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2020 options->regs[Z80_IXH] = DH; |
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2021 options->regs[Z80_IXL] = RDX; |
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2022 options->regs[Z80_IYH] = -1; |
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2023 options->regs[Z80_IYL] = R8; |
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2024 options->regs[Z80_I] = -1; |
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2025 options->regs[Z80_R] = -1; |
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2026 options->regs[Z80_A] = R10; |
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2027 options->regs[Z80_BC] = RBX; |
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2028 options->regs[Z80_DE] = RCX; |
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2029 options->regs[Z80_HL] = RAX; |
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2030 options->regs[Z80_SP] = R9; |
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2031 options->regs[Z80_AF] = -1; |
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2032 options->regs[Z80_IX] = RDX; |
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2033 options->regs[Z80_IY] = R8; |
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2034 size_t size = 1024 * 1024; |
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2035 options->cur_code = alloc_code(&size); |
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2036 options->code_end = options->cur_code + size; |
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2037 options->ram_inst_sizes = malloc(sizeof(uint8_t) * 0x2000); |
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2038 memset(options->ram_inst_sizes, 0, sizeof(uint8_t) * 0x2000); |
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2039 options->deferred = NULL; |
213
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2040 } |
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2041 |
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2042 void init_z80_context(z80_context * context, x86_z80_options * options) |
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2043 { |
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2044 memset(context, 0, sizeof(*context)); |
360
c42fae88d346
Fix sizeof expression passed to malloc in z80_init to avoid a minor memory error
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|
2045 context->static_code_map = malloc(sizeof(*context->static_code_map)); |
259
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2046 context->static_code_map->base = NULL; |
235
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2047 context->static_code_map->offsets = malloc(sizeof(int32_t) * 0x2000); |
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2048 memset(context->static_code_map->offsets, 0xFF, sizeof(int32_t) * 0x2000); |
627
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|
2049 context->banked_code_map = malloc(sizeof(native_map_slot)); |
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|
2050 memset(context->banked_code_map, 0, sizeof(native_map_slot)); |
235
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2051 context->options = options; |
625
6aa2a8ab9c70
Slight cleanup of vint handling on the Z80
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506
diff
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|
2052 context->int_cycle = 0xFFFFFFFF; |
628 | 2053 context->int_pulse_start = 0xFFFFFFFF; |
2054 context->int_pulse_end = 0xFFFFFFFF; | |
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2055 } |
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2056 |
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2057 void z80_reset(z80_context * context) |
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2058 { |
259
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2059 context->im = 0; |
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2060 context->iff1 = context->iff2 = 0; |
235
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2061 context->native_pc = z80_get_native_address_trans(context, 0); |
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2062 context->extra_pc = NULL; |
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2063 } |
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2064 |
626
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|
2065 uint8_t * zbreakpoint_patch(z80_context * context, uint16_t address, uint8_t * native) |
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2066 { |
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Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
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|
2067 native = mov_ir(native, address, SCRATCH1, SZ_W); |
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|
2068 native = call(native, context->bp_stub); |
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2069 return native; |
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2070 } |
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2071 |
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|
2072 void zcreate_stub(z80_context * context) |
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|
2073 { |
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|
2074 x86_z80_options * opts = context->options; |
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|
2075 uint8_t * dst = opts->cur_code; |
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|
2076 uint8_t * dst_end = opts->code_end; |
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|
2077 if (dst_end - dst < 128) { |
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|
2078 size_t size = 1024*1024; |
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|
2079 dst = alloc_code(&size); |
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changeset
|
2080 opts->code_end = dst_end = dst + size; |
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|
2081 } |
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changeset
|
2082 context->bp_stub = dst; |
7c46891a29b1
Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents:
625
diff
changeset
|
2083 |
7c46891a29b1
Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents:
625
diff
changeset
|
2084 //Calculate length of prologue |
7c46891a29b1
Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents:
625
diff
changeset
|
2085 int check_int_size = z80_check_cycles_int(dst, 0) - dst; |
7c46891a29b1
Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents:
625
diff
changeset
|
2086 |
7c46891a29b1
Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents:
625
diff
changeset
|
2087 //Calculate length of patch |
7c46891a29b1
Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents:
625
diff
changeset
|
2088 int patch_size = zbreakpoint_patch(context, 0, dst) - dst; |
7c46891a29b1
Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents:
625
diff
changeset
|
2089 |
7c46891a29b1
Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents:
625
diff
changeset
|
2090 //Save context and call breakpoint handler |
7c46891a29b1
Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents:
625
diff
changeset
|
2091 dst = call(dst, (uint8_t *)z80_save_context); |
7c46891a29b1
Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents:
625
diff
changeset
|
2092 dst = push_r(dst, SCRATCH1); |
7c46891a29b1
Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents:
625
diff
changeset
|
2093 dst = mov_rr(dst, CONTEXT, RDI, SZ_Q); |
7c46891a29b1
Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents:
625
diff
changeset
|
2094 dst = mov_rr(dst, SCRATCH1, RSI, SZ_W); |
7c46891a29b1
Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents:
625
diff
changeset
|
2095 dst = call(dst, context->bp_handler); |
7c46891a29b1
Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents:
625
diff
changeset
|
2096 dst = mov_rr(dst, RAX, CONTEXT, SZ_Q); |
7c46891a29b1
Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents:
625
diff
changeset
|
2097 //Restore context |
7c46891a29b1
Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents:
625
diff
changeset
|
2098 dst = call(dst, (uint8_t *)z80_load_context); |
7c46891a29b1
Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents:
625
diff
changeset
|
2099 dst = pop_r(dst, SCRATCH1); |
7c46891a29b1
Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents:
625
diff
changeset
|
2100 //do prologue stuff |
7c46891a29b1
Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents:
625
diff
changeset
|
2101 dst = cmp_rr(dst, ZCYCLES, ZLIMIT, SZ_D); |
7c46891a29b1
Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents:
625
diff
changeset
|
2102 uint8_t * jmp_off = dst+1; |
7c46891a29b1
Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents:
625
diff
changeset
|
2103 dst = jcc(dst, CC_NC, dst + 7); |
7c46891a29b1
Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents:
625
diff
changeset
|
2104 dst = pop_r(dst, SCRATCH1); |
7c46891a29b1
Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents:
625
diff
changeset
|
2105 dst = add_ir(dst, check_int_size - patch_size, SCRATCH1, SZ_Q); |
7c46891a29b1
Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents:
625
diff
changeset
|
2106 dst = push_r(dst, SCRATCH1); |
7c46891a29b1
Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents:
625
diff
changeset
|
2107 dst = jmp(dst, (uint8_t *)z80_handle_cycle_limit_int); |
7c46891a29b1
Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents:
625
diff
changeset
|
2108 *jmp_off = dst - (jmp_off+1); |
7c46891a29b1
Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents:
625
diff
changeset
|
2109 //jump back to body of translated instruction |
7c46891a29b1
Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents:
625
diff
changeset
|
2110 dst = pop_r(dst, SCRATCH1); |
7c46891a29b1
Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents:
625
diff
changeset
|
2111 dst = add_ir(dst, check_int_size - patch_size, SCRATCH1, SZ_Q); |
7c46891a29b1
Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents:
625
diff
changeset
|
2112 dst = jmp_r(dst, SCRATCH1); |
7c46891a29b1
Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents:
625
diff
changeset
|
2113 opts->cur_code = dst; |
7c46891a29b1
Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents:
625
diff
changeset
|
2114 } |
7c46891a29b1
Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents:
625
diff
changeset
|
2115 |
366
836585d389b8
Partial implementation of Z80 debugger
Mike Pavone <pavone@retrodev.com>
parents:
363
diff
changeset
|
2116 void zinsert_breakpoint(z80_context * context, uint16_t address, uint8_t * bp_handler) |
836585d389b8
Partial implementation of Z80 debugger
Mike Pavone <pavone@retrodev.com>
parents:
363
diff
changeset
|
2117 { |
626
7c46891a29b1
Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents:
625
diff
changeset
|
2118 context->bp_handler = bp_handler; |
7c46891a29b1
Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents:
625
diff
changeset
|
2119 uint8_t bit = 1 << (address % sizeof(uint8_t)); |
7c46891a29b1
Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents:
625
diff
changeset
|
2120 if (!(bit & context->breakpoint_flags[address / sizeof(uint8_t)])) { |
7c46891a29b1
Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents:
625
diff
changeset
|
2121 context->breakpoint_flags[address / sizeof(uint8_t)] |= bit; |
7c46891a29b1
Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents:
625
diff
changeset
|
2122 if (!context->bp_stub) { |
7c46891a29b1
Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents:
625
diff
changeset
|
2123 zcreate_stub(context); |
366
836585d389b8
Partial implementation of Z80 debugger
Mike Pavone <pavone@retrodev.com>
parents:
363
diff
changeset
|
2124 } |
626
7c46891a29b1
Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents:
625
diff
changeset
|
2125 uint8_t * native = z80_get_native_address(context, address); |
7c46891a29b1
Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents:
625
diff
changeset
|
2126 if (native) { |
7c46891a29b1
Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents:
625
diff
changeset
|
2127 zbreakpoint_patch(context, address, native); |
7c46891a29b1
Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents:
625
diff
changeset
|
2128 } |
366
836585d389b8
Partial implementation of Z80 debugger
Mike Pavone <pavone@retrodev.com>
parents:
363
diff
changeset
|
2129 } |
836585d389b8
Partial implementation of Z80 debugger
Mike Pavone <pavone@retrodev.com>
parents:
363
diff
changeset
|
2130 } |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
2131 |
366
836585d389b8
Partial implementation of Z80 debugger
Mike Pavone <pavone@retrodev.com>
parents:
363
diff
changeset
|
2132 void zremove_breakpoint(z80_context * context, uint16_t address) |
836585d389b8
Partial implementation of Z80 debugger
Mike Pavone <pavone@retrodev.com>
parents:
363
diff
changeset
|
2133 { |
651
103d5cabbe14
Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown.
Michael Pavone <pavone@retrodev.com>
parents:
644
diff
changeset
|
2134 context->breakpoint_flags[address / sizeof(uint8_t)] &= ~(1 << (address % sizeof(uint8_t))); |
366
836585d389b8
Partial implementation of Z80 debugger
Mike Pavone <pavone@retrodev.com>
parents:
363
diff
changeset
|
2135 uint8_t * native = z80_get_native_address(context, address); |
626
7c46891a29b1
Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents:
625
diff
changeset
|
2136 if (native) { |
7c46891a29b1
Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents:
625
diff
changeset
|
2137 z80_check_cycles_int(native, address); |
7c46891a29b1
Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents:
625
diff
changeset
|
2138 } |
366
836585d389b8
Partial implementation of Z80 debugger
Mike Pavone <pavone@retrodev.com>
parents:
363
diff
changeset
|
2139 } |
836585d389b8
Partial implementation of Z80 debugger
Mike Pavone <pavone@retrodev.com>
parents:
363
diff
changeset
|
2140 |
836585d389b8
Partial implementation of Z80 debugger
Mike Pavone <pavone@retrodev.com>
parents:
363
diff
changeset
|
2141 |