repos/blastem: blastem.c annotate

annotate blastem.c @ 153:42c031184e8a

Implement access to Z80 RAM

author	Mike Pavone <pavone@retrodev.com>
date	Fri, 04 Jan 2013 21:47:09 -0800
parents	139e5dcd6aa3
children	a2ab895d9708

rev	line source
88 c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	1 #include "68kinst.h"
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	2 #include "m68k_to_x86.h"
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	3 #include "mem.h"
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	4 #include "vdp.h"
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	5 #include "render.h"
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	6 #include "blastem.h"
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	7 #include <stdio.h>
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	8 #include <stdlib.h>
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	9
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	10 #define CARTRIDGE_WORDS 0x200000
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	11 #define RAM_WORDS 32 * 1024
153 42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	12 #define Z80_RAM_BYTES 8 * 1024
88 c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	13 #define MCLKS_PER_68K 7
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	14 //TODO: Figure out the exact value for this
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	15 #define MCLKS_PER_FRAME (MCLKS_LINE*262)
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	16 #define CYCLE_NEVER 0xFFFFFFFF
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	17
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	18 uint16_t cart[CARTRIDGE_WORDS];
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	19 uint16_t ram[RAM_WORDS];
153 42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	20 uint8_t z80_ram[Z80_RAM_BYTES];
88 c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	21
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	22 io_port gamepad_1;
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	23 io_port gamepad_2;
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	24
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	25 #ifndef MIN
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	26 #define MIN(a,b) ((a) < (b) ? (a) : (b))
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	27 #endif
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	28
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	29 int load_rom(char * filename)
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	30 {
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	31 FILE * f = fopen(filename, "rb");
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	32 if (!f) {
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	33 return 0;
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	34 }
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	35 fseek(f, 0, SEEK_END);
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	36 long filesize = ftell(f);
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	37 fseek(f, 0, SEEK_SET);
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	38 fread(cart, 2, MIN(filesize/2, CARTRIDGE_WORDS), f);
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	39 fclose(f);
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	40 for(unsigned short * cur = cart; cur - cart < (filesize/2); ++cur)
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	41 {
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	42 cur = (cur >> 8) \| (*cur << 8);
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	43 }
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	44 //TODO: Mirror ROM
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	45 return 1;
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	46 }
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	47
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	48 uint16_t read_dma_value(uint32_t address)
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	49 {
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	50 //addresses here are word addresses (i.e. bit 0 corresponds to A1), so no need to do div by 2
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	51 if (address < 0x200000) {
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	52 return cart[address];
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	53 } else if(address >= 0x700000) {
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	54 return ram[address & 0x7FFF];
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	55 }
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	56 //TODO: Figure out what happens when you try to DMA from weird adresses like IO or banked Z80 area
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	57 return 0;
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	58 }
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	59
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	60 #define VINT_CYCLE ((MCLKS_LINE * 226)/MCLKS_PER_68K)
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	61
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	62 m68k_context * sync_components(m68k_context * context)
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	63 {
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	64 //TODO: Handle sync targets smaller than a single frame
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	65 vdp_context * v_context = context->next_context;
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	66 uint32_t mclks = context->current_cycle * MCLKS_PER_68K;
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	67 if (mclks >= MCLKS_PER_FRAME) {
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	68 //printf("reached frame end \| 68K Cycles: %d, MCLK Cycles: %d\n", context->current_cycle, mclks);
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	69 vdp_run_context(v_context, MCLKS_PER_FRAME);
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	70 wait_render_frame(v_context);
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	71 mclks -= MCLKS_PER_FRAME;
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	72 vdp_adjust_cycles(v_context, MCLKS_PER_FRAME);
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	73 io_adjust_cycles(&gamepad_1, context->current_cycle, MCLKS_PER_FRAME/MCLKS_PER_68K);
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	74 io_adjust_cycles(&gamepad_2, context->current_cycle, MCLKS_PER_FRAME/MCLKS_PER_68K);
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	75 context->current_cycle -= MCLKS_PER_FRAME/MCLKS_PER_68K;
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	76 if (mclks) {
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	77 vdp_run_context(v_context, mclks);
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	78 }
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	79 if (v_context->regs[REG_MODE_2] & 0x20 && ((context->status & 0x7) < 6)) {
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	80 if (context->int_cycle > VINT_CYCLE) {
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	81 context->int_cycle = VINT_CYCLE;
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	82 context->int_num = 6;
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	83 if (context->int_cycle < context->sync_cycle) {
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	84 context->target_cycle = context->int_cycle;
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	85 }
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	86 }
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	87 } else {
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	88 context->int_cycle = 0xFFFFFFFF;
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	89 context->target_cycle = context->sync_cycle;
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	90 }
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	91 } else {
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	92 //printf("running VDP for %d cycles\n", mclks - v_context->cycles);
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	93 vdp_run_context(v_context, mclks);
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	94 if (v_context->regs[REG_MODE_2] & 0x20 && ((context->status & 0x7) < 6)) {
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	95 if (context->int_cycle > VINT_CYCLE) {
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	96 context->int_cycle = VINT_CYCLE;
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	97 context->int_num = 6;
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	98 if (context->int_cycle < context->sync_cycle && context->int_cycle < context->current_cycle) {
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	99 context->target_cycle = context->int_cycle;
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	100 }
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	101 }
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	102 if (context->int_cycle <= context->current_cycle) {
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	103 context->int_cycle = CYCLE_NEVER;
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	104 context->target_cycle = context->sync_cycle;
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	105 }
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	106 } else {
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	107 context->int_cycle = CYCLE_NEVER;
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	108 context->target_cycle = context->sync_cycle;
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	109 }
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	110 }
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	111 return context;
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	112 }
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	113
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	114 m68k_context * vdp_port_write(uint32_t vdp_port, m68k_context * context, uint16_t value)
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	115 {
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	116 //printf("vdp_port write: %X, value: %X, cycle: %d\n", vdp_port, value, context->current_cycle);
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	117 sync_components(context);
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	118 vdp_context * v_context = context->next_context;
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	119 if (vdp_port < 0x10) {
149 139e5dcd6aa3 Make writes to control and data port block when DMA is in progress Mike Pavone <pavone@retrodev.com> parents: 144 diff changeset	120 int blocked;
88 c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	121 if (vdp_port < 4) {
149 139e5dcd6aa3 Make writes to control and data port block when DMA is in progress Mike Pavone <pavone@retrodev.com> parents: 144 diff changeset	122 while (vdp_data_port_write(v_context, value) < 0) {
88 c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	123 while(v_context->flags & FLAG_DMA_RUN) {
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	124 vdp_run_dma_done(v_context, MCLKS_PER_FRAME);
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	125 if (v_context->cycles >= MCLKS_PER_FRAME) {
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	126 wait_render_frame(v_context);
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	127 vdp_adjust_cycles(v_context, MCLKS_PER_FRAME);
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	128 io_adjust_cycles(&gamepad_1, v_context->cycles/MCLKS_PER_68K, MCLKS_PER_FRAME/MCLKS_PER_68K);
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	129 io_adjust_cycles(&gamepad_2, v_context->cycles/MCLKS_PER_68K, MCLKS_PER_FRAME/MCLKS_PER_68K);
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	130 }
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	131 }
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	132 context->current_cycle = v_context->cycles / MCLKS_PER_68K;
149 139e5dcd6aa3 Make writes to control and data port block when DMA is in progress Mike Pavone <pavone@retrodev.com> parents: 144 diff changeset	133 }
139e5dcd6aa3 Make writes to control and data port block when DMA is in progress Mike Pavone <pavone@retrodev.com> parents: 144 diff changeset	134 } else if(vdp_port < 8) {
139e5dcd6aa3 Make writes to control and data port block when DMA is in progress Mike Pavone <pavone@retrodev.com> parents: 144 diff changeset	135 blocked = vdp_control_port_write(v_context, value);
139e5dcd6aa3 Make writes to control and data port block when DMA is in progress Mike Pavone <pavone@retrodev.com> parents: 144 diff changeset	136 if (blocked) {
139e5dcd6aa3 Make writes to control and data port block when DMA is in progress Mike Pavone <pavone@retrodev.com> parents: 144 diff changeset	137 while (blocked) {
139e5dcd6aa3 Make writes to control and data port block when DMA is in progress Mike Pavone <pavone@retrodev.com> parents: 144 diff changeset	138 while(v_context->flags & FLAG_DMA_RUN) {
139e5dcd6aa3 Make writes to control and data port block when DMA is in progress Mike Pavone <pavone@retrodev.com> parents: 144 diff changeset	139 vdp_run_dma_done(v_context, MCLKS_PER_FRAME);
139e5dcd6aa3 Make writes to control and data port block when DMA is in progress Mike Pavone <pavone@retrodev.com> parents: 144 diff changeset	140 if (v_context->cycles >= MCLKS_PER_FRAME) {
139e5dcd6aa3 Make writes to control and data port block when DMA is in progress Mike Pavone <pavone@retrodev.com> parents: 144 diff changeset	141 wait_render_frame(v_context);
139e5dcd6aa3 Make writes to control and data port block when DMA is in progress Mike Pavone <pavone@retrodev.com> parents: 144 diff changeset	142 vdp_adjust_cycles(v_context, MCLKS_PER_FRAME);
139e5dcd6aa3 Make writes to control and data port block when DMA is in progress Mike Pavone <pavone@retrodev.com> parents: 144 diff changeset	143 io_adjust_cycles(&gamepad_1, v_context->cycles/MCLKS_PER_68K, MCLKS_PER_FRAME/MCLKS_PER_68K);
139e5dcd6aa3 Make writes to control and data port block when DMA is in progress Mike Pavone <pavone@retrodev.com> parents: 144 diff changeset	144 io_adjust_cycles(&gamepad_2, v_context->cycles/MCLKS_PER_68K, MCLKS_PER_FRAME/MCLKS_PER_68K);
139e5dcd6aa3 Make writes to control and data port block when DMA is in progress Mike Pavone <pavone@retrodev.com> parents: 144 diff changeset	145 }
139e5dcd6aa3 Make writes to control and data port block when DMA is in progress Mike Pavone <pavone@retrodev.com> parents: 144 diff changeset	146 }
139e5dcd6aa3 Make writes to control and data port block when DMA is in progress Mike Pavone <pavone@retrodev.com> parents: 144 diff changeset	147 if (blocked < 0) {
139e5dcd6aa3 Make writes to control and data port block when DMA is in progress Mike Pavone <pavone@retrodev.com> parents: 144 diff changeset	148 blocked = vdp_control_port_write(v_context, value);
139e5dcd6aa3 Make writes to control and data port block when DMA is in progress Mike Pavone <pavone@retrodev.com> parents: 144 diff changeset	149 } else {
139e5dcd6aa3 Make writes to control and data port block when DMA is in progress Mike Pavone <pavone@retrodev.com> parents: 144 diff changeset	150 blocked = 0;
139e5dcd6aa3 Make writes to control and data port block when DMA is in progress Mike Pavone <pavone@retrodev.com> parents: 144 diff changeset	151 }
139e5dcd6aa3 Make writes to control and data port block when DMA is in progress Mike Pavone <pavone@retrodev.com> parents: 144 diff changeset	152 }
139e5dcd6aa3 Make writes to control and data port block when DMA is in progress Mike Pavone <pavone@retrodev.com> parents: 144 diff changeset	153 context->current_cycle = v_context->cycles / MCLKS_PER_68K;
88 c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	154 } else {
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	155 if (v_context->regs[REG_MODE_2] & 0x20 && ((context->status & 0x7) < 6)) {
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	156 if (context->int_cycle > VINT_CYCLE) {
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	157 context->int_cycle = VINT_CYCLE;
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	158 context->int_num = 6;
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	159 if (context->int_cycle < context->sync_cycle) {
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	160 context->target_cycle = context->int_cycle;
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	161 }
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	162 }
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	163 } else {
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	164 context->int_cycle = 0xFFFFFFFF;
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	165 context->target_cycle = context->sync_cycle;
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	166 }
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	167 }
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	168 } else {
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	169 printf("Illegal write to HV Counter port %X\n", vdp_port);
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	170 exit(1);
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	171 }
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	172 context->current_cycle = v_context->cycles/MCLKS_PER_68K;
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	173 } else if (vdp_port < 0x18) {
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	174 //TODO: Implement PSG
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	175 } else {
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	176 //TODO: Implement undocumented test register(s)
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	177 }
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	178 return context;
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	179 }
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	180
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	181 m68k_context * vdp_port_read(uint32_t vdp_port, m68k_context * context)
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	182 {
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	183 sync_components(context);
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	184 vdp_context * v_context = context->next_context;
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	185 if (vdp_port < 0x10) {
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	186 if (vdp_port < 4) {
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	187 context->value = vdp_data_port_read(v_context);
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	188 } else if(vdp_port < 8) {
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	189 context->value = vdp_control_port_read(v_context);
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	190 } else {
137 0e7e1ccc0a81 Implemented HV counter Mike Pavone <pavone@retrodev.com> parents: 130 diff changeset	191 context->value = vdp_hv_counter_read(v_context);
0e7e1ccc0a81 Implemented HV counter Mike Pavone <pavone@retrodev.com> parents: 130 diff changeset	192 //printf("HV Counter: %X at cycle %d\n", context->value, v_context->cycles);
88 c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	193 }
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	194 context->current_cycle = v_context->cycles/MCLKS_PER_68K;
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	195 } else {
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	196 printf("Illegal read from PSG or test register port %X\n", vdp_port);
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	197 exit(1);
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	198 }
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	199 return context;
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	200 }
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	201
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	202 #define TH 0x40
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	203 #define TH_TIMEOUT 8000
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	204 #define Z80_ACK_DELAY 3 //TODO: Calculate this on the fly based on how synced up the Z80 and 68K clocks are
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	205
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	206 uint8_t reset = 1;
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	207 uint8_t busreq = 0;
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	208 uint8_t busack = 0;
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	209 uint32_t busack_cycle = CYCLE_NEVER;
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	210 uint8_t new_busack = 0;
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	211
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	212 void io_adjust_cycles(io_port * pad, uint32_t current_cycle, uint32_t deduction)
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	213 {
89 9757b4c6c33f Minor joypad fix and commeount out some debug printfs Mike Pavone <pavone@retrodev.com> parents: 88 diff changeset	214 /*uint8_t control = pad->control \| 0x80;
88 c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	215 uint8_t th = control & pad->output;
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	216 if (pad->input[GAMEPAD_TH0] \|\| pad->input[GAMEPAD_TH1]) {
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	217 printf("adjust_cycles \| control: %X, TH: %X, GAMEPAD_TH0: %X, GAMEPAD_TH1: %X, TH Counter: %d, Timeout: %d, Cycle: %d\n", control, th, pad->input[GAMEPAD_TH0], pad->input[GAMEPAD_TH1], pad->th_counter,pad->timeout_cycle, current_cycle);
89 9757b4c6c33f Minor joypad fix and commeount out some debug printfs Mike Pavone <pavone@retrodev.com> parents: 88 diff changeset	218 }*/
88 c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	219 if (current_cycle >= pad->timeout_cycle) {
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	220 pad->th_counter = 0;
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	221 } else {
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	222 pad->timeout_cycle -= deduction;
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	223 }
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	224 if (busack_cycle < CYCLE_NEVER && current_cycle < busack_cycle) {
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	225 busack_cycle -= deduction;
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	226 }
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	227 }
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	228
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	229 void io_data_write(io_port * pad, m68k_context * context, uint8_t value)
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	230 {
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	231 if (pad->control & TH) {
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	232 //check if TH has changed
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	233 if ((pad->output & TH) ^ (value & TH)) {
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	234 if (context->current_cycle >= pad->timeout_cycle) {
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	235 pad->th_counter = 0;
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	236 }
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	237 if (!(value & TH)) {
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	238 pad->th_counter++;
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	239 }
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	240 pad->timeout_cycle = context->current_cycle + TH_TIMEOUT;
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	241 }
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	242 }
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	243 pad->output = value;
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	244 }
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	245
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	246 void io_data_read(io_port * pad, m68k_context * context)
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	247 {
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	248 uint8_t control = pad->control \| 0x80;
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	249 uint8_t th = control & pad->output;
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	250 uint8_t input;
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	251 if (context->current_cycle >= pad->timeout_cycle) {
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	252 pad->th_counter = 0;
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	253 }
89 9757b4c6c33f Minor joypad fix and commeount out some debug printfs Mike Pavone <pavone@retrodev.com> parents: 88 diff changeset	254 /*if (pad->input[GAMEPAD_TH0] \|\| pad->input[GAMEPAD_TH1]) {
88 c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	255 printf("io_data_read \| control: %X, TH: %X, GAMEPAD_TH0: %X, GAMEPAD_TH1: %X, TH Counter: %d, Timeout: %d, Cycle: %d\n", control, th, pad->input[GAMEPAD_TH0], pad->input[GAMEPAD_TH1], pad->th_counter,pad->timeout_cycle, context->current_cycle);
89 9757b4c6c33f Minor joypad fix and commeount out some debug printfs Mike Pavone <pavone@retrodev.com> parents: 88 diff changeset	256 }*/
88 c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	257 if (th) {
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	258 if (pad->th_counter == 2) {
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	259 input = pad->input[GAMEPAD_EXTRA];
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	260 } else {
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	261 input = pad->input[GAMEPAD_TH1];
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	262 }
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	263 } else {
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	264 if (pad->th_counter == 2) {
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	265 input = pad->input[GAMEPAD_TH0] \| 0xF;
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	266 } else if(pad->th_counter == 3) {
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	267 input = pad->input[GAMEPAD_TH0] & 0x30;
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	268 } else {
89 9757b4c6c33f Minor joypad fix and commeount out some debug printfs Mike Pavone <pavone@retrodev.com> parents: 88 diff changeset	269 input = pad->input[GAMEPAD_TH0] \| 0xC;
88 c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	270 }
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	271 }
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	272 context->value = ((~input) & (~control)) \| (pad->output & control);
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	273 /*if (pad->input[GAMEPAD_TH0] \|\| pad->input[GAMEPAD_TH1]) {
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	274 printf ("value: %X\n", context->value);
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	275 }*/
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	276 }
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	277
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	278 m68k_context * io_write(uint32_t location, m68k_context * context, uint8_t value)
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	279 {
153 42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	280 if (location < 0x10000) {
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	281 if (busack_cycle > context->current_cycle) {
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	282 busack = new_busack;
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	283 busack_cycle = CYCLE_NEVER;
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	284 }
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	285 if (!(busack \|\| reset)) {
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	286 location &= 0x7FFF;
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	287 if (location < 0x4000) {
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	288 z80_ram[location & 0x1FFF] = value;
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	289 }
88 c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	290 }
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	291 } else {
153 42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	292 location &= 0x1FFF;
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	293 if (location < 0x100) {
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	294 switch(location/2)
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	295 {
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	296 case 0x1:
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	297 io_data_write(&gamepad_1, context, value);
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	298 break;
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	299 case 0x2:
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	300 io_data_write(&gamepad_2, context, value);
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	301 break;
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	302 case 0x3://PORT C Data
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	303 break;
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	304 case 0x4:
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	305 gamepad_1.control = value;
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	306 break;
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	307 case 0x5:
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	308 gamepad_2.control = value;
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	309 break;
88 c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	310 }
153 42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	311 } else {
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	312 if (location == 0x1100) {
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	313 if (busack_cycle > context->current_cycle) {
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	314 busack = new_busack;
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	315 busack_cycle = CYCLE_NEVER;
88 c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	316 }
153 42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	317 if (value & 1) {
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	318 busreq = 1;
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	319 if(!reset) {
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	320 busack_cycle = context->current_cycle + Z80_ACK_DELAY;
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	321 new_busack = 0;
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	322 }
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	323 } else {
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	324 busreq = 0;
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	325 busack_cycle = CYCLE_NEVER;
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	326 busack = 1;
88 c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	327 }
153 42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	328 } else if (location == 0x1200) {
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	329 if (value & 1) {
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	330 if (reset && busreq) {
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	331 new_busack = 0;
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	332 busack_cycle = context->current_cycle + Z80_ACK_DELAY;
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	333 }
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	334 reset = 0;
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	335 } else {
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	336 reset = 1;
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	337 }
88 c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	338 }
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	339 }
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	340 }
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	341 return context;
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	342 }
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	343
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	344 m68k_context * io_write_w(uint32_t location, m68k_context * context, uint16_t value)
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	345 {
153 42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	346 if (location < 0x10000) {
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	347 if (busack_cycle > context->current_cycle) {
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	348 busack = new_busack;
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	349 busack_cycle = CYCLE_NEVER;
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	350 }
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	351 if (!(busack \|\| reset)) {
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	352 location &= 0x7FFF;
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	353 if (location < 0x4000) {
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	354 z80_ram[location & 0x1FFE] = value >> 8;
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	355 }
88 c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	356 }
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	357 } else {
153 42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	358 location &= 0x1FFF;
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	359 if (location < 0x100) {
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	360 switch(location/2)
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	361 {
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	362 case 0x1:
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	363 io_data_write(&gamepad_1, context, value);
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	364 break;
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	365 case 0x2:
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	366 io_data_write(&gamepad_2, context, value);
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	367 break;
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	368 case 0x3://PORT C Data
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	369 break;
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	370 case 0x4:
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	371 gamepad_1.control = value;
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	372 break;
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	373 case 0x5:
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	374 gamepad_2.control = value;
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	375 break;
88 c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	376 }
153 42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	377 } else {
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	378 //printf("IO Write of %X to %X @ %d\n", value, location, context->current_cycle);
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	379 if (location == 0x1100) {
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	380 if (busack_cycle > context->current_cycle) {
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	381 busack = new_busack;
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	382 busack_cycle = CYCLE_NEVER;
88 c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	383 }
153 42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	384 if (value & 0x100) {
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	385 busreq = 1;
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	386 if(!reset) {
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	387 busack_cycle = context->current_cycle + Z80_ACK_DELAY;
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	388 new_busack = 0;
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	389 }
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	390 } else {
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	391 busreq = 0;
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	392 busack_cycle = CYCLE_NEVER;
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	393 busack = 1;
88 c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	394 }
153 42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	395 } else if (location == 0x1200) {
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	396 if (value & 0x100) {
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	397 if (reset && busreq) {
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	398 new_busack = 0;
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	399 busack_cycle = context->current_cycle + Z80_ACK_DELAY;
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	400 }
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	401 reset = 0;
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	402 } else {
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	403 reset = 1;
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	404 }
88 c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	405 }
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	406 }
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	407 }
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	408 return context;
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	409 }
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	410
130 0bdbffa9fe90 Make version register return correct value for USA Mike Pavone <pavone@retrodev.com> parents: 115 diff changeset	411 #define USA 0x80
0bdbffa9fe90 Make version register return correct value for USA Mike Pavone <pavone@retrodev.com> parents: 115 diff changeset	412 #define JAP 0x00
0bdbffa9fe90 Make version register return correct value for USA Mike Pavone <pavone@retrodev.com> parents: 115 diff changeset	413 #define EUR 0xC0
0bdbffa9fe90 Make version register return correct value for USA Mike Pavone <pavone@retrodev.com> parents: 115 diff changeset	414 #define NO_DISK 0x20
0bdbffa9fe90 Make version register return correct value for USA Mike Pavone <pavone@retrodev.com> parents: 115 diff changeset	415 uint8_t version_reg = NO_DISK \| USA;
0bdbffa9fe90 Make version register return correct value for USA Mike Pavone <pavone@retrodev.com> parents: 115 diff changeset	416
88 c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	417 m68k_context * io_read(uint32_t location, m68k_context * context)
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	418 {
153 42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	419 if (location < 0x10000) {
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	420 if (busack_cycle > context->current_cycle) {
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	421 busack = new_busack;
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	422 busack_cycle = CYCLE_NEVER;
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	423 }
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	424 if (!(busack \|\| reset)) {
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	425 location &= 0x7FFF;
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	426 if (location < 0x4000) {
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	427 context->value = z80_ram[location & 0x1FFF];
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	428 } else {
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	429 context->value = 0xFF;
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	430 }
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	431 } else {
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	432 context->value = 0xFF;
88 c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	433 }
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	434 } else {
153 42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	435 location &= 0x1FFF;
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	436 if (location < 0x100) {
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	437 switch(location/2)
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	438 {
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	439 case 0x0:
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	440 //version bits should be 0 for now since we're not emulating TMSS
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	441 //Not sure about the other bits
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	442 context->value = version_reg;
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	443 break;
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	444 case 0x1:
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	445 io_data_read(&gamepad_1, context);
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	446 break;
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	447 case 0x2:
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	448 io_data_read(&gamepad_2, context);
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	449 break;
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	450 case 0x3://PORT C Data
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	451 break;
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	452 case 0x4:
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	453 context->value = gamepad_1.control;
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	454 break;
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	455 case 0x5:
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	456 context->value = gamepad_2.control;
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	457 break;
88 c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	458 }
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	459 } else {
153 42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	460 if (location == 0x1100) {
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	461 if (busack_cycle > context->current_cycle) {
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	462 busack = new_busack;
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	463 busack_cycle = CYCLE_NEVER;
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	464 }
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	465 context->value = reset \|\| busack;
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	466 //printf("Byte read of BUSREQ returned %d @ %d (reset: %d, busack: %d)\n", context->value, context->current_cycle, reset, busack);
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	467 } else if (location == 0x1200) {
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	468 context->value = !reset;
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	469 } else {
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	470 printf("Byte read of unknown IO location: %X\n", location);
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	471 }
88 c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	472 }
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	473 }
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	474 return context;
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	475 }
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	476
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	477 m68k_context * io_read_w(uint32_t location, m68k_context * context)
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	478 {
153 42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	479 if (location < 0x10000) {
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	480 if (busack_cycle > context->current_cycle) {
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	481 busack = new_busack;
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	482 busack_cycle = CYCLE_NEVER;
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	483 }
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	484 if (!(busack \|\| reset)) {
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	485 location &= 0x7FFF;
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	486 if (location < 0x4000) {
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	487 context->value = z80_ram[location & 0x1FFE];
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	488 context->value \|= context->value << 8;
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	489 } else {
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	490 context->value = 0xFFFF;
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	491 }
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	492 } else {
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	493 context->value = 0xFFFF;
88 c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	494 }
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	495 } else {
153 42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	496 location &= 0x1FFF;
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	497 if (location < 0x100) {
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	498 switch(location/2)
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	499 {
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	500 case 0x0:
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	501 //version bits should be 0 for now since we're not emulating TMSS
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	502 //Not sure about the other bits
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	503 context->value = 0;
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	504 break;
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	505 case 0x1:
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	506 io_data_read(&gamepad_1, context);
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	507 break;
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	508 case 0x2:
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	509 io_data_read(&gamepad_2, context);
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	510 break;
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	511 case 0x3://PORT C Data
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	512 break;
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	513 case 0x4:
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	514 context->value = gamepad_1.control;
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	515 break;
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	516 case 0x5:
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	517 context->value = gamepad_2.control;
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	518 break;
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	519 case 0x6:
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	520 //PORT C Control
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	521 context->value = 0;
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	522 break;
88 c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	523 }
153 42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	524 context->value = context->value \| (context->value << 8);
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	525 //printf("Word read to %X returned %d\n", location, context->value);
88 c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	526 } else {
153 42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	527 if (location == 0x1100) {
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	528 if (busack_cycle > context->current_cycle) {
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	529 busack = new_busack;
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	530 busack_cycle = CYCLE_NEVER;
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	531 }
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	532 context->value = (reset \|\| busack) << 8;
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	533 //printf("Word read of BUSREQ returned %d\n", context->value);
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	534 } else if (location == 0x1200) {
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	535 context->value = (!reset) << 8;
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	536 } else {
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	537 printf("Word read of unknown IO location: %X\n", location);
42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	538 }
88 c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	539 }
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	540 }
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	541 return context;
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	542 }
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	543
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	544 int main(int argc, char ** argv)
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	545 {
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	546 if (argc < 2) {
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	547 fputs("Usage: blastem FILENAME\n", stderr);
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	548 return 1;
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	549 }
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	550 if(!load_rom(argv[1])) {
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	551 fprintf(stderr, "Failed to open %s for reading\n", argv[1]);
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	552 return 1;
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	553 }
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	554 int width = 320;
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	555 int height = 240;
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	556 if (argc > 2) {
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	557 width = atoi(argv[2]);
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	558 if (argc > 3) {
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	559 height = atoi(argv[3]);
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	560 } else {
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	561 height = (width/320) * 240;
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	562 }
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	563 }
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	564 render_init(width, height);
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	565
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	566 x86_68k_options opts;
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	567 m68k_context context;
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	568 vdp_context v_context;
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	569
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	570 init_x86_68k_opts(&opts);
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	571 init_68k_context(&context, opts.native_code_map, &opts);
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	572 init_vdp_context(&v_context);
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	573 context.next_context = &v_context;
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	574 //cartridge ROM
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	575 context.mem_pointers[0] = cart;
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	576 context.target_cycle = context.sync_cycle = MCLKS_PER_FRAME/MCLKS_PER_68K;
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	577 //work RAM
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	578 context.mem_pointers[1] = ram;
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	579 uint32_t address;
103 a71544cd01ea Don't pre-emptively translate code at interrupt vectors as some PD ROMs have these pointing at junk. Need some kind of heuristic for detecting garbage if I'm going to translate them ahead of time by default. Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	580 /*address = cart[0x68/2] << 16 \| cart[0x6A/2];
95 dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 89 diff changeset	581 translate_m68k_stream(address, &context);
88 c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	582 address = cart[0x70/2] << 16 \| cart[0x72/2];
95 dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 89 diff changeset	583 translate_m68k_stream(address, &context);
88 c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	584 address = cart[0x78/2] << 16 \| cart[0x7A/2];
103 a71544cd01ea Don't pre-emptively translate code at interrupt vectors as some PD ROMs have these pointing at junk. Need some kind of heuristic for detecting garbage if I'm going to translate them ahead of time by default. Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	585 translate_m68k_stream(address, &context);*/
88 c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	586 address = cart[2] << 16 \| cart[3];
95 dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 89 diff changeset	587 translate_m68k_stream(address, &context);
88 c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	588 m68k_reset(&context);
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	589 return 0;
c339559f1d4f Forgot to add blastem main file earlier Mike Pavone <pavone@retrodev.com> parents: diff changeset	590 }

Mercurial > repos > blastem

annotate blastem.c @ 153:42c031184e8a