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annotate 68kinst.c @ 154:4791c0204410

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Small fix for bit instructions
author Mike Pavone <pavone@retrodev.com>
date Fri, 04 Jan 2013 22:51:01 -0800
parents 18796a3b0fe2
children 5559616e6bd8
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1 #include "68kinst.h"
2
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2 #include <string.h>
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3 #include <stdio.h>
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4
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5 uint32_t sign_extend16(uint32_t val)
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6 {
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7 return (val & 0x8000) ? val | 0xFFFF0000 : val;
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8 }
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9
2
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10 uint32_t sign_extend8(uint32_t val)
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11 {
2
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12 return (val & 0x80) ? val | 0xFFFFFF00 : val;
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13 }
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14
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15 uint16_t *m68k_decode_op_ex(uint16_t *cur, uint8_t mode, uint8_t reg, uint8_t size, m68k_op_info *dst)
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16 {
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17 uint16_t ext;
0
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18 dst->addr_mode = mode;
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19 switch(mode)
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20 {
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21 case MODE_REG:
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22 case MODE_AREG:
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23 case MODE_AREG_INDIRECT:
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24 case MODE_AREG_POSTINC:
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25 case MODE_AREG_PREDEC:
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26 dst->params.regs.pri = reg;
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27 break;
2
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28 case MODE_AREG_DISPLACE:
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29 ext = *(++cur);
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30 dst->params.regs.pri = reg;
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31 dst->params.regs.displacement = sign_extend16(ext);
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32 break;
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33 case MODE_AREG_INDEX_MEM:
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34 #ifdef M68020
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35 //TODO: implement me for M68020+ support
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36 #else
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37 dst->addr_mode = MODE_AREG_INDEX_DISP8;
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38 dst->params.regs.pri = reg;
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39 ext = *(++cur);
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40 dst->params.regs.sec = ext >> 11;//includes areg/dreg bit, reg num and word/long bit
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41 dst->params.regs.displacement = sign_extend8(ext&0xFF);
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42 #endif
2
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43 break;
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44 case MODE_PC_INDIRECT_ABS_IMMED:
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45 switch(reg)
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46 {
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47 case 0:
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48 dst->addr_mode = MODE_ABSOLUTE_SHORT;
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49 ext = *(++cur);
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50 dst->params.immed = sign_extend16(ext);
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51 break;
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52 case 1:
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53 dst->addr_mode = MODE_ABSOLUTE;
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54 ext = *(++cur);
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55 dst->params.immed = ext << 16 | *(++cur);
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56 break;
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57 case 3:
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58 #ifdef M68020
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59 //TODO: Implement me for M68020+ support;
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60 #else
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61 dst->addr_mode = MODE_PC_INDEX_DISP8;
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62 ext = *(++cur);
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63 dst->params.regs.sec = ext >> 11;//includes areg/dreg bit, reg num and word/long bit
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64 dst->params.regs.displacement = sign_extend8(ext&0xFF);
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65 #endif
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dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
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66 break;
2
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67 case 2:
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68 dst->addr_mode = MODE_PC_DISPLACE;
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69 ext = *(++cur);
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70 dst->params.regs.displacement = sign_extend16(ext);
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71 break;
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72 case 4:
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73 dst->addr_mode = MODE_IMMEDIATE;
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74 ext = *(++cur);
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75 switch (size)
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76 {
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77 case OPSIZE_BYTE:
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78 dst->params.immed = ext & 0xFF;
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79 break;
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80 case OPSIZE_WORD:
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81 dst->params.immed = ext;
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82 break;
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83 case OPSIZE_LONG:
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84 dst->params.immed = ext << 16 | *(++cur);
2
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85 break;
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86 }
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87 break;
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88 }
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89 break;
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90 }
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91 return cur;
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92 }
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93
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94 uint16_t *m68k_decode_op(uint16_t *cur, uint8_t size, m68k_op_info *dst)
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95 {
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96 uint8_t mode = (*cur >> 3) & 0x7;
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97 uint8_t reg = *cur & 0x7;
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98 return m68k_decode_op_ex(cur, mode, reg, size, dst);
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99 }
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100
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101 void m68k_decode_cond(uint16_t op, m68kinst * decoded)
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102 {
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103 decoded->extra.cond = (op >> 0x8) & 0xF;
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104 }
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105
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106 uint8_t m68k_reg_quick_field(uint16_t op)
2
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107 {
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108 return (op >> 9) & 0x7;
0
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109 }
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110
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111 uint16_t * m68k_decode(uint16_t * istream, m68kinst * decoded, uint32_t address)
0
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112 {
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113 uint8_t optype = *istream >> 12;
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114 uint8_t size;
4
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115 uint8_t reg;
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116 uint8_t opmode;
2
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117 uint32_t immed;
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118 decoded->op = M68K_INVALID;
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119 decoded->src.addr_mode = decoded->dst.addr_mode = MODE_UNUSED;
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120 decoded->variant = VAR_NORMAL;
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121 decoded->address = address;
0
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122 switch(optype)
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123 {
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124 case BIT_MOVEP_IMMED:
4
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125 if (*istream & 0x100) {
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126 //BTST, BCHG, BCLR, BSET
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127 switch ((*istream >> 6) & 0x3)
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128 {
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129 case 0:
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130 decoded->op = M68K_BTST;
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131 break;
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132 case 1:
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parents: 3
diff changeset
133 decoded->op = M68K_BCHG;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents: 3
diff changeset
134 break;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents: 3
diff changeset
135 case 2:
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents: 3
diff changeset
136 decoded->op = M68K_BCLR;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents: 3
diff changeset
137 break;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents: 3
diff changeset
138 case 3:
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents: 3
diff changeset
139 decoded->op = M68K_BSET;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents: 3
diff changeset
140 break;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents: 3
diff changeset
141 }
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents: 3
diff changeset
142 decoded->src.addr_mode = MODE_REG;
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
143 decoded->src.params.regs.pri = m68k_reg_quick_field(*istream);
61
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 60
diff changeset
144 decoded->extra.size = OPSIZE_BYTE;
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 60
diff changeset
145 istream = m68k_decode_op(istream, decoded->extra.size, &(decoded->dst));
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 60
diff changeset
146 if (decoded->dst.addr_mode == MODE_REG) {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 60
diff changeset
147 decoded->extra.size = OPSIZE_LONG;
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 60
diff changeset
148 }
8
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
149 } else if ((*istream & 0xF00) == 0x800) {
12
db60ed283d8d Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions.
Mike Pavone <pavone@retrodev.com>
parents: 11
diff changeset
150 //BTST, BCHG, BCLR, BSET
db60ed283d8d Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions.
Mike Pavone <pavone@retrodev.com>
parents: 11
diff changeset
151 switch ((*istream >> 6) & 0x3)
db60ed283d8d Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions.
Mike Pavone <pavone@retrodev.com>
parents: 11
diff changeset
152 {
db60ed283d8d Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions.
Mike Pavone <pavone@retrodev.com>
parents: 11
diff changeset
153 case 0:
db60ed283d8d Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions.
Mike Pavone <pavone@retrodev.com>
parents: 11
diff changeset
154 decoded->op = M68K_BTST;
db60ed283d8d Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions.
Mike Pavone <pavone@retrodev.com>
parents: 11
diff changeset
155 break;
db60ed283d8d Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions.
Mike Pavone <pavone@retrodev.com>
parents: 11
diff changeset
156 case 1:
db60ed283d8d Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions.
Mike Pavone <pavone@retrodev.com>
parents: 11
diff changeset
157 decoded->op = M68K_BCHG;
db60ed283d8d Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions.
Mike Pavone <pavone@retrodev.com>
parents: 11
diff changeset
158 break;
db60ed283d8d Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions.
Mike Pavone <pavone@retrodev.com>
parents: 11
diff changeset
159 case 2:
db60ed283d8d Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions.
Mike Pavone <pavone@retrodev.com>
parents: 11
diff changeset
160 decoded->op = M68K_BCLR;
db60ed283d8d Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions.
Mike Pavone <pavone@retrodev.com>
parents: 11
diff changeset
161 break;
db60ed283d8d Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions.
Mike Pavone <pavone@retrodev.com>
parents: 11
diff changeset
162 case 3:
db60ed283d8d Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions.
Mike Pavone <pavone@retrodev.com>
parents: 11
diff changeset
163 decoded->op = M68K_BSET;
db60ed283d8d Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions.
Mike Pavone <pavone@retrodev.com>
parents: 11
diff changeset
164 break;
db60ed283d8d Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions.
Mike Pavone <pavone@retrodev.com>
parents: 11
diff changeset
165 }
db60ed283d8d Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions.
Mike Pavone <pavone@retrodev.com>
parents: 11
diff changeset
166 opmode = (*istream >> 3) & 0x7;
db60ed283d8d Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions.
Mike Pavone <pavone@retrodev.com>
parents: 11
diff changeset
167 reg = *istream & 0x7;
61
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 60
diff changeset
168 decoded->src.addr_mode = MODE_IMMEDIATE_WORD;
15
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 13
diff changeset
169 decoded->src.params.immed = *(++istream) & 0xFF;
12
db60ed283d8d Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions.
Mike Pavone <pavone@retrodev.com>
parents: 11
diff changeset
170 decoded->extra.size = OPSIZE_BYTE;
61
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 60
diff changeset
171 istream = m68k_decode_op_ex(istream, opmode, reg, decoded->extra.size, &(decoded->dst));
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 60
diff changeset
172 if (decoded->dst.addr_mode == MODE_REG) {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 60
diff changeset
173 decoded->extra.size = OPSIZE_LONG;
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 60
diff changeset
174 }
8
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
175 } else if ((*istream & 0xC0) == 0xC0) {
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
176 #ifdef M68020
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
177 //CMP2, CHK2, CAS, CAS2, RTM, CALLM
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
178 #endif
4
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents: 3
diff changeset
179 } else {
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents: 3
diff changeset
180 switch ((*istream >> 9) & 0x7)
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents: 3
diff changeset
181 {
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents: 3
diff changeset
182 case 0:
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents: 3
diff changeset
183 if ((*istream & 0xFF) == 0x3C) {
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents: 3
diff changeset
184 decoded->op = M68K_ORI_CCR;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents: 3
diff changeset
185 decoded->extra.size = OPSIZE_BYTE;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents: 3
diff changeset
186 decoded->src.addr_mode = MODE_IMMEDIATE;
15
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 13
diff changeset
187 decoded->src.params.immed = *(++istream) & 0xFF;
4
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents: 3
diff changeset
188 } else if((*istream & 0xFF) == 0x7C) {
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents: 3
diff changeset
189 decoded->op = M68K_ORI_SR;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents: 3
diff changeset
190 decoded->extra.size = OPSIZE_WORD;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents: 3
diff changeset
191 decoded->src.addr_mode = MODE_IMMEDIATE;
15
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 13
diff changeset
192 decoded->src.params.immed = *(++istream);
4
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents: 3
diff changeset
193 } else {
8
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
194 decoded->op = M68K_OR;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
195 decoded->variant = VAR_IMMEDIATE;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
196 decoded->src.addr_mode = MODE_IMMEDIATE;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
197 decoded->extra.size = size = (*istream >> 6) & 3;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
198 reg = *istream & 0x7;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
199 opmode = (*istream >> 3) & 0x7;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
200 switch (size)
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
201 {
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
202 case OPSIZE_BYTE:
15
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 13
diff changeset
203 decoded->src.params.immed = *(++istream) & 0xFF;
8
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
204 break;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
205 case OPSIZE_WORD:
15
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 13
diff changeset
206 decoded->src.params.immed = *(++istream);
8
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
207 break;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
208 case OPSIZE_LONG:
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
209 immed = *(++istream);
15
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 13
diff changeset
210 decoded->src.params.immed = immed << 16 | *(++istream);
8
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
211 break;
4
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents: 3
diff changeset
212 }
8
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
213 istream = m68k_decode_op_ex(istream, opmode, reg, size, &(decoded->dst));
4
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents: 3
diff changeset
214 }
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents: 3
diff changeset
215 break;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents: 3
diff changeset
216 case 1:
8
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
217 //ANDI, ANDI to CCR, ANDI to SR
5
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
218 if ((*istream & 0xFF) == 0x3C) {
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
219 decoded->op = M68K_ANDI_CCR;
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
220 decoded->extra.size = OPSIZE_BYTE;
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
221 decoded->src.addr_mode = MODE_IMMEDIATE;
15
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 13
diff changeset
222 decoded->src.params.immed = *(++istream) & 0xFF;
5
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
223 } else if((*istream & 0xFF) == 0x7C) {
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
224 decoded->op = M68K_ANDI_SR;
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
225 decoded->extra.size = OPSIZE_WORD;
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
226 decoded->src.addr_mode = MODE_IMMEDIATE;
15
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 13
diff changeset
227 decoded->src.params.immed = *(++istream);
5
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
228 } else {
8
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
229 decoded->op = M68K_AND;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
230 decoded->variant = VAR_IMMEDIATE;
5
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
231 decoded->src.addr_mode = MODE_IMMEDIATE;
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
232 decoded->extra.size = size = (*istream >> 6) & 3;
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
233 reg = *istream & 0x7;
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
234 opmode = (*istream >> 3) & 0x7;
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
235 switch (size)
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
236 {
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
237 case OPSIZE_BYTE:
15
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 13
diff changeset
238 decoded->src.params.immed = *(++istream) & 0xFF;
5
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
239 break;
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
240 case OPSIZE_WORD:
15
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 13
diff changeset
241 decoded->src.params.immed = *(++istream);
5
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
242 break;
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
243 case OPSIZE_LONG:
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
244 immed = *(++istream);
15
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 13
diff changeset
245 decoded->src.params.immed = immed << 16 | *(++istream);
5
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
246 break;
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
247 }
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
248 istream = m68k_decode_op_ex(istream, opmode, reg, size, &(decoded->dst));
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
249 }
4
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents: 3
diff changeset
250 break;
8
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
251 case 2:
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
252 decoded->op = M68K_SUB;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
253 decoded->variant = VAR_IMMEDIATE;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
254 decoded->src.addr_mode = MODE_IMMEDIATE;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
255 decoded->extra.size = size = (*istream >> 6) & 3;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
256 reg = *istream & 0x7;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
257 opmode = (*istream >> 3) & 0x7;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
258 switch (size)
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
259 {
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
260 case OPSIZE_BYTE:
15
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 13
diff changeset
261 decoded->src.params.immed = *(++istream) & 0xFF;
8
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
262 break;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
263 case OPSIZE_WORD:
15
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 13
diff changeset
264 decoded->src.params.immed = *(++istream);
8
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
265 break;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
266 case OPSIZE_LONG:
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
267 immed = *(++istream);
15
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 13
diff changeset
268 decoded->src.params.immed = immed << 16 | *(++istream);
8
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
269 break;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
270 }
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
271 istream = m68k_decode_op_ex(istream, opmode, reg, size, &(decoded->dst));
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
272 break;
4
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents: 3
diff changeset
273 case 3:
8
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
274 decoded->op = M68K_ADD;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
275 decoded->variant = VAR_IMMEDIATE;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
276 decoded->src.addr_mode = MODE_IMMEDIATE;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
277 decoded->extra.size = size = (*istream >> 6) & 3;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
278 reg = *istream & 0x7;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
279 opmode = (*istream >> 3) & 0x7;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
280 switch (size)
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
281 {
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
282 case OPSIZE_BYTE:
15
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 13
diff changeset
283 decoded->src.params.immed = *(++istream) & 0xFF;
8
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
284 break;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
285 case OPSIZE_WORD:
15
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 13
diff changeset
286 decoded->src.params.immed = *(++istream);
8
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
287 break;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
288 case OPSIZE_LONG:
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
289 immed = *(++istream);
15
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 13
diff changeset
290 decoded->src.params.immed = immed << 16 | *(++istream);
8
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
291 break;
5
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
292 }
8
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
293 istream = m68k_decode_op_ex(istream, opmode, reg, size, &(decoded->dst));
4
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents: 3
diff changeset
294 break;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents: 3
diff changeset
295 case 4:
5
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
296 //BTST, BCHG, BCLR, BSET
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
297 switch ((*istream >> 6) & 0x3)
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
298 {
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
299 case 0:
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
300 decoded->op = M68K_BTST;
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
301 break;
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
302 case 1:
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
303 decoded->op = M68K_BCHG;
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
304 break;
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
305 case 2:
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
306 decoded->op = M68K_BCLR;
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
307 break;
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
308 case 3:
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
309 decoded->op = M68K_BSET;
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
310 break;
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
311 }
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
312 decoded->src.addr_mode = MODE_IMMEDIATE;
15
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 13
diff changeset
313 decoded->src.params.immed = *(++istream) & 0xFF;
5
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
314 istream = m68k_decode_op(istream, OPSIZE_BYTE, &(decoded->dst));
4
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents: 3
diff changeset
315 break;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents: 3
diff changeset
316 case 5:
5
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
317 //EORI, EORI to CCR, EORI to SR
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
318 if ((*istream & 0xFF) == 0x3C) {
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
319 decoded->op = M68K_EORI_CCR;
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
320 decoded->extra.size = OPSIZE_BYTE;
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
321 decoded->src.addr_mode = MODE_IMMEDIATE;
15
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 13
diff changeset
322 decoded->src.params.immed = *(++istream) & 0xFF;
5
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
323 } else if((*istream & 0xFF) == 0x7C) {
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
324 decoded->op = M68K_EORI_SR;
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
325 decoded->extra.size = OPSIZE_WORD;
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
326 decoded->src.addr_mode = MODE_IMMEDIATE;
15
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 13
diff changeset
327 decoded->src.params.immed = *(++istream);
5
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
328 } else {
8
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
329 decoded->op = M68K_EOR;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
330 decoded->variant = VAR_IMMEDIATE;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
331 decoded->src.addr_mode = MODE_IMMEDIATE;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
332 decoded->extra.size = size = (*istream >> 6) & 3;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
333 reg = *istream & 0x7;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
334 opmode = (*istream >> 3) & 0x7;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
335 switch (size)
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
336 {
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
337 case OPSIZE_BYTE:
15
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 13
diff changeset
338 decoded->src.params.immed = *(++istream) & 0xFF;
8
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
339 break;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
340 case OPSIZE_WORD:
15
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 13
diff changeset
341 decoded->src.params.immed = *(++istream);
8
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
342 break;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
343 case OPSIZE_LONG:
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
344 immed = *(++istream);
15
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 13
diff changeset
345 decoded->src.params.immed = immed << 16 | *(++istream);
8
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
346 break;
5
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
347 }
8
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
348 istream = m68k_decode_op_ex(istream, opmode, reg, size, &(decoded->dst));
5
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
349 }
4
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents: 3
diff changeset
350 break;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents: 3
diff changeset
351 case 6:
8
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
352 decoded->op = M68K_CMP;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
353 decoded->variant = VAR_IMMEDIATE;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
354 decoded->extra.size = (*istream >> 6) & 0x3;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
355 decoded->src.addr_mode = MODE_IMMEDIATE;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
356 reg = *istream & 0x7;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
357 opmode = (*istream >> 3) & 0x7;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
358 switch (decoded->extra.size)
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
359 {
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
360 case OPSIZE_BYTE:
15
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 13
diff changeset
361 decoded->src.params.immed = *(++istream) & 0xFF;
8
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
362 break;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
363 case OPSIZE_WORD:
15
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 13
diff changeset
364 decoded->src.params.immed = *(++istream);
8
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
365 break;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
366 case OPSIZE_LONG:
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
367 immed = *(++istream);
15
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 13
diff changeset
368 decoded->src.params.immed = (immed << 16) | *(++istream);
8
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
369 break;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
370 }
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
371 istream = m68k_decode_op_ex(istream, opmode, reg, size, &(decoded->dst));
4
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents: 3
diff changeset
372 break;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents: 3
diff changeset
373 case 7:
8
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
374 //MOVEP
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
375 decoded->op = M68K_MOVEP;
8
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
376 decoded->extra.size = *istream & 0x40 ? OPSIZE_LONG : OPSIZE_WORD;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
377 if (*istream & 0x80) {
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
378 //memory dest
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
379 decoded->src.addr_mode = MODE_REG;
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
380 decoded->src.params.regs.pri = m68k_reg_quick_field(*istream);
8
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
381 decoded->dst.addr_mode = MODE_AREG_DISPLACE;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
382 decoded->dst.params.regs.pri = *istream & 0x7;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
383 } else {
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
384 //memory source
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
385 decoded->dst.addr_mode = MODE_REG;
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
386 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream);
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
387 decoded->src.addr_mode = MODE_AREG_DISPLACE;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
388 decoded->src.params.regs.pri = *istream & 0x7;
8
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
389 }
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
390 immed = *(++istream);
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
391
4
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents: 3
diff changeset
392 break;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents: 3
diff changeset
393 }
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents: 3
diff changeset
394 }
0
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
395 break;
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
396 case MOVE_BYTE:
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
397 case MOVE_LONG:
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
398 case MOVE_WORD:
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
399 decoded->op = M68K_MOVE;
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
400 decoded->extra.size = optype == MOVE_BYTE ? OPSIZE_BYTE : (optype == MOVE_WORD ? OPSIZE_WORD : OPSIZE_LONG);
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
401 opmode = (*istream >> 6) & 0x7;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
402 reg = m68k_reg_quick_field(*istream);
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
403 istream = m68k_decode_op(istream, decoded->extra.size, &(decoded->src));
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
404 istream = m68k_decode_op_ex(istream, opmode, reg, decoded->extra.size, &(decoded->dst));
0
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
405 break;
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
406 case MISC:
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
407
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
408 if ((*istream & 0x1C0) == 0x1C0) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
409 decoded->op = M68K_LEA;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
410 decoded->extra.size = OPSIZE_LONG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
411 decoded->dst.addr_mode = MODE_AREG;
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
412 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream);
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
413 istream = m68k_decode_op(istream, decoded->extra.size, &(decoded->src));
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
414 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
415 if (*istream & 0x100) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
416 decoded->op = M68K_CHK;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
417 if ((*istream & 0x180) == 0x180) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
418 decoded->extra.size = OPSIZE_WORD;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
419 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
420 //only on M68020+
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
421 #ifdef M68020
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
422 decoded->extra.size = OPSIZE_LONG;
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
423 #else
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
424 decoded->op = M68K_INVALID;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
425 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
426 #endif
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
427 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
428 istream = m68k_decode_op(istream, decoded->extra.size, &(decoded->src));
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
429 decoded->dst.addr_mode = MODE_REG;
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
430 decoded->dst.addr_mode = m68k_reg_quick_field(*istream);
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
431 } else {
13
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
432 opmode = (*istream >> 3) & 0x7;
61
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 60
diff changeset
433 if ((*istream & 0xB80) == 0x880 && opmode != MODE_REG && opmode != MODE_AREG) {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 60
diff changeset
434 //TODO: Check for invalid modes that are dependent on direction
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
435 decoded->op = M68K_MOVEM;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
436 decoded->extra.size = *istream & 0x40 ? OPSIZE_LONG : OPSIZE_WORD;
13
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
437 reg = *istream & 0x7;
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
438 if(*istream & 0x400) {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
439 decoded->dst.addr_mode = MODE_REG;
68
1c9a4052a2c0 Fix decoding and disassembly of MOVEM
Mike Pavone <pavone@retrodev.com>
parents: 62
diff changeset
440 decoded->dst.params.immed = *(++istream);
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
441 istream = m68k_decode_op_ex(istream, opmode, reg, decoded->extra.size, &(decoded->src));
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
442 } else {
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
443 decoded->src.addr_mode = MODE_REG;
68
1c9a4052a2c0 Fix decoding and disassembly of MOVEM
Mike Pavone <pavone@retrodev.com>
parents: 62
diff changeset
444 decoded->src.params.immed = *(++istream);
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
445 istream = m68k_decode_op_ex(istream, opmode, reg, decoded->extra.size, &(decoded->dst));
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
446 }
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
447 } else {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
448 optype = (*istream >> 9) & 0x7;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
449 size = (*istream >> 6) & 0x3;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
450 switch(optype)
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
451 {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
452 case 0:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
453 //Move from SR or NEGX
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
454 if (size == OPSIZE_INVALID) {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
455 decoded->op = M68K_MOVE_FROM_SR;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
456 size = OPSIZE_WORD;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
457 } else {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
458 decoded->op = M68K_NEGX;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
459 }
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
460 decoded->extra.size = size;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
461 istream= m68k_decode_op(istream, size, &(decoded->dst));
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
462 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
463 case 1:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
464 //MOVE from CCR or CLR
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
465 if (size == OPSIZE_INVALID) {
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
466 #ifdef M68010
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
467 decoded->op = M68K_MOVE_FROM_CCR;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
468 size = OPSIZE_WORD;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
469 #else
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
470 return istream+1;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
471 #endif
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
472 } else {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
473 decoded->op = M68K_CLR;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
474 }
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
475 decoded->extra.size = size;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
476 istream= m68k_decode_op(istream, size, &(decoded->dst));
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
477 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
478 case 2:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
479 //MOVE to CCR or NEG
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
480 if (size == OPSIZE_INVALID) {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
481 decoded->op = M68K_MOVE_CCR;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
482 size = OPSIZE_WORD;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
483 istream= m68k_decode_op(istream, size, &(decoded->src));
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
484 } else {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
485 decoded->op = M68K_NEG;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
486 istream= m68k_decode_op(istream, size, &(decoded->dst));
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
487 }
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
488 decoded->extra.size = size;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
489 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
490 case 3:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
491 //MOVE to SR or NOT
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
492 if (size == OPSIZE_INVALID) {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
493 decoded->op = M68K_MOVE_SR;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
494 size = OPSIZE_WORD;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
495 istream= m68k_decode_op(istream, size, &(decoded->src));
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
496 } else {
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
497 decoded->op = M68K_NOT;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
498 istream= m68k_decode_op(istream, size, &(decoded->dst));
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
499 }
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
500 decoded->extra.size = size;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
501 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
502 case 4:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
503 //EXT, EXTB, LINK.l, NBCD, SWAP, BKPT, PEA
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
504 switch((*istream >> 3) & 0x3F)
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
505 {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
506 case 1:
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
507 #ifdef M68020
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
508 decoded->op = M68K_LINK;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
509 decoded->extra.size = OPSIZE_LONG;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
510 reg = *istream & 0x7;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
511 immed = *(++istream) << 16;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
512 immed |= *(++istream);
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
513 #endif
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
514 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
515 case 8:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
516 decoded->op = M68K_SWAP;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
517 decoded->src.addr_mode = MODE_REG;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
518 decoded->src.params.regs.pri = *istream & 0x7;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
519 decoded->extra.size = OPSIZE_WORD;
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
520 break;
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
521 case 9:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
522 #ifdef M68010
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
523 decoded->op = M68K_BKPT;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
524 decoded->src.addr_mode = MODE_IMMEDIATE;
10
4553fc97b15e Added new OPSIZE for unsized instructions so they can be properly disassembled without making them special cases
Mike Pavone <pavone@retrodev.com>
parents: 9
diff changeset
525 decoded->extra.size = OPSIZE_UNSIZED;
15
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 13
diff changeset
526 decoded->src.params.immed = *istream & 0x7;
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
527 #endif
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
528 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
529 case 0x10:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
530 decoded->op = M68K_EXT;
93
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents: 91
diff changeset
531 decoded->dst.addr_mode = MODE_REG;
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents: 91
diff changeset
532 decoded->dst.params.regs.pri = *istream & 0x7;
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
533 decoded->extra.size = OPSIZE_WORD;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
534 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
535 case 0x18:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
536 decoded->op = M68K_EXT;
93
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents: 91
diff changeset
537 decoded->dst.addr_mode = MODE_REG;
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents: 91
diff changeset
538 decoded->dst.params.regs.pri = *istream & 0x7;
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
539 decoded->extra.size = OPSIZE_LONG;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
540 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
541 case 0x38:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
542 #ifdef M68020
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
543 #endif
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
544 break;
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
545 default:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
546 if (!(*istream & 0x1C0)) {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
547 decoded->op = M68K_NBCD;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
548 decoded->extra.size = OPSIZE_BYTE;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
549 istream = m68k_decode_op(istream, OPSIZE_BYTE, &(decoded->dst));
13
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
550 } else if((*istream & 0x1C0) == 0x40) {
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
551 decoded->op = M68K_PEA;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
552 decoded->extra.size = OPSIZE_LONG;
116
9eaba47c429d Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents: 111
diff changeset
553 istream = m68k_decode_op(istream, OPSIZE_LONG, &(decoded->src));
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
554 }
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
555 }
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
556 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
557 case 5:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
558 //BGND, ILLEGAL, TAS, TST
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
559 optype = *istream & 0xFF;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
560 if (optype == 0xFA) {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
561 //BGND - CPU32 only
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
562 } else if (optype == 0xFC) {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
563 decoded->op = M68K_ILLEGAL;
10
4553fc97b15e Added new OPSIZE for unsized instructions so they can be properly disassembled without making them special cases
Mike Pavone <pavone@retrodev.com>
parents: 9
diff changeset
564 decoded->extra.size = OPSIZE_UNSIZED;
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
565 } else {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
566 if (size == OPSIZE_INVALID) {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
567 decoded->op = M68K_TAS;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
568 } else {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
569 decoded->op = M68K_TST;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
570 decoded->extra.size = size;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
571 istream = m68k_decode_op(istream, decoded->extra.size, &(decoded->src));
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
572 }
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
573 }
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
574 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
575 case 6:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
576 //MULU, MULS, DIVU, DIVUL, DIVS, DIVSL
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
577 #ifdef M68020
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
578 //TODO: Implement these for 68020+ support
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
579 #endif
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
580 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
581 case 7:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
582 //TRAP, LINK.w, UNLNK, MOVE USP, RESET, NOP, STOP, RTE, RTD, RTS, TRAPV, RTR, MOVEC, JSR, JMP
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
583 if (*istream & 0x80) {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
584 //JSR, JMP
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
585 if (*istream & 0x40) {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
586 decoded->op = M68K_JMP;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
587 } else {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
588 decoded->op = M68K_JSR;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
589 }
10
4553fc97b15e Added new OPSIZE for unsized instructions so they can be properly disassembled without making them special cases
Mike Pavone <pavone@retrodev.com>
parents: 9
diff changeset
590 decoded->extra.size = OPSIZE_UNSIZED;
4553fc97b15e Added new OPSIZE for unsized instructions so they can be properly disassembled without making them special cases
Mike Pavone <pavone@retrodev.com>
parents: 9
diff changeset
591 istream = m68k_decode_op(istream, OPSIZE_UNSIZED, &(decoded->src));
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
592 } else {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
593 //it would appear bit 6 needs to be set for it to be a valid instruction here
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
594 switch((*istream >> 3) & 0x7)
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
595 {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
596 case 0:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
597 case 1:
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
598 //TRAP
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
599 decoded->op = M68K_TRAP;
10
4553fc97b15e Added new OPSIZE for unsized instructions so they can be properly disassembled without making them special cases
Mike Pavone <pavone@retrodev.com>
parents: 9
diff changeset
600 decoded->extra.size = OPSIZE_UNSIZED;
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
601 decoded->src.addr_mode = MODE_IMMEDIATE;
15
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 13
diff changeset
602 decoded->src.params.immed = *istream & 0xF;
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
603 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
604 case 2:
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
605 //LINK.w
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
606 decoded->op = M68K_LINK;
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
607 decoded->extra.size = OPSIZE_WORD;
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
608 decoded->src.addr_mode = MODE_AREG;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
609 decoded->src.params.regs.pri = *istream & 0x7;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
610 decoded->dst.addr_mode = MODE_IMMEDIATE;
93
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents: 91
diff changeset
611 decoded->dst.params.immed = sign_extend16(*(++istream));
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
612 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
613 case 3:
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
614 //UNLK
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
615 decoded->op = M68K_UNLK;
10
4553fc97b15e Added new OPSIZE for unsized instructions so they can be properly disassembled without making them special cases
Mike Pavone <pavone@retrodev.com>
parents: 9
diff changeset
616 decoded->extra.size = OPSIZE_UNSIZED;
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
617 decoded->dst.addr_mode = MODE_AREG;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
618 decoded->dst.params.regs.pri = *istream & 0x7;
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
619 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
620 case 4:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
621 case 5:
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
622 //MOVE USP
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
623 decoded->op = M68K_MOVE_USP;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
624 if (*istream & 0x8) {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
625 decoded->dst.addr_mode = MODE_AREG;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
626 decoded->dst.params.regs.pri = *istream & 0x7;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
627 } else {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
628 decoded->src.addr_mode = MODE_AREG;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
629 decoded->src.params.regs.pri = *istream & 0x7;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
630 }
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
631 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
632 case 6:
10
4553fc97b15e Added new OPSIZE for unsized instructions so they can be properly disassembled without making them special cases
Mike Pavone <pavone@retrodev.com>
parents: 9
diff changeset
633 decoded->extra.size = OPSIZE_UNSIZED;
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
634 switch(*istream & 0x7)
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
635 {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
636 case 0:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
637 decoded->op = M68K_RESET;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
638 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
639 case 1:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
640 decoded->op = M68K_NOP;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
641 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
642 case 2:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
643 decoded->op = M68K_STOP;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
644 decoded->src.addr_mode = MODE_IMMEDIATE;
15
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 13
diff changeset
645 decoded->src.params.immed =*(++istream);
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
646 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
647 case 3:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
648 decoded->op = M68K_RTE;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
649 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
650 case 4:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
651 #ifdef M68010
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
652 decoded->op = M68K_RTD;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
653 decoded->src.addr_mode = MODE_IMMEDIATE;
15
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 13
diff changeset
654 decoded->src.params.immed =*(++istream);
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
655 #endif
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
656 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
657 case 5:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
658 decoded->op = M68K_RTS;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
659 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
660 case 6:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
661 decoded->op = M68K_TRAPV;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
662 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
663 case 7:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
664 decoded->op = M68K_RTR;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
665 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
666 }
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
667 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
668 case 7:
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
669 //MOVEC
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
670 #ifdef M68010
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
671 #endif
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
672 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
673 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
674 }
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
675 break;
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
676 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
677 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
678 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
679 }
0
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
680 break;
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
681 case QUICK_ARITH_LOOP:
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
682 size = (*istream >> 6) & 3;
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
683 if (size == 0x3) {
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
684 //DBcc, TRAPcc or Scc
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
685 m68k_decode_cond(*istream, decoded);
111
8b50d2c975b2 Fix decoding of Scc
Mike Pavone <pavone@retrodev.com>
parents: 101
diff changeset
686 if (((*istream >> 3) & 0x7) == 1) {
0
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
687 decoded->op = M68K_DBCC;
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
688 decoded->src.addr_mode = MODE_IMMEDIATE;
0
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
689 decoded->dst.addr_mode = MODE_REG;
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
690 decoded->dst.params.regs.pri = *istream & 0x7;
46
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
691 decoded->src.params.immed = sign_extend16(*(++istream));
111
8b50d2c975b2 Fix decoding of Scc
Mike Pavone <pavone@retrodev.com>
parents: 101
diff changeset
692 } else if(((*istream >> 3) & 0x7) == 1 && (*istream & 0x7) > 1 && (*istream & 0x7) < 5) {
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
693 #ifdef M68020
0
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
694 decoded->op = M68K_TRAPCC;
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
695 decoded->src.addr_mode = MODE_IMMEDIATE;
0
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
696 //TODO: Figure out what to do with OPMODE and optional extention words
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
697 #endif
111
8b50d2c975b2 Fix decoding of Scc
Mike Pavone <pavone@retrodev.com>
parents: 101
diff changeset
698 } else {
0
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
699 decoded->op = M68K_SCC;
111
8b50d2c975b2 Fix decoding of Scc
Mike Pavone <pavone@retrodev.com>
parents: 101
diff changeset
700 decoded->extra.cond = (*istream >> 8) & 0xF;
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
701 istream = m68k_decode_op(istream, OPSIZE_BYTE, &(decoded->dst));
0
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
702 }
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
703 } else {
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
704 //ADDQ, SUBQ
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
705 decoded->variant = VAR_QUICK;
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
706 decoded->extra.size = size;
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
707 decoded->src.addr_mode = MODE_IMMEDIATE;
91
8c446fc19cc0 Fix decoding bug in addq/subq
Mike Pavone <pavone@retrodev.com>
parents: 90
diff changeset
708 immed = m68k_reg_quick_field(*istream);
0
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
709 if (!immed) {
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
710 immed = 8;
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
711 }
15
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 13
diff changeset
712 decoded->src.params.immed = immed;
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
713 if (*istream & 0x100) {
0
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
714 decoded->op = M68K_SUB;
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
715 } else {
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
716 decoded->op = M68K_ADD;
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
717 }
94
a668a35a3463 Fix decoding bug for addq/subq
Mike Pavone <pavone@retrodev.com>
parents: 93
diff changeset
718 istream = m68k_decode_op(istream, size, &(decoded->dst));
0
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
719 }
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
720 break;
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
721 case BRANCH:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
722 m68k_decode_cond(*istream, decoded);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
723 decoded->op = decoded->extra.cond == COND_FALSE ? M68K_BSR : M68K_BCC;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
724 decoded->src.addr_mode = MODE_IMMEDIATE;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
725 immed = *istream & 0xFF;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
726 if (immed == 0) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
727 decoded->variant = VAR_WORD;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
728 immed = *(++istream);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
729 immed = sign_extend16(immed);
154
4791c0204410 Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 140
diff changeset
730 #ifdef M68020
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
731 } else if (immed == 0xFF) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
732 decoded->variant = VAR_LONG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
733 immed = *(++istream) << 16;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
734 immed |= *(++istream);
154
4791c0204410 Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 140
diff changeset
735 #endif
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
736 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
737 decoded->variant = VAR_BYTE;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
738 immed = sign_extend8(immed);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
739 }
15
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 13
diff changeset
740 decoded->src.params.immed = immed;
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
741 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
742 case MOVEQ:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
743 decoded->op = M68K_MOVE;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
744 decoded->variant = VAR_QUICK;
15
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 13
diff changeset
745 decoded->extra.size = OPSIZE_LONG;
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
746 decoded->src.addr_mode = MODE_IMMEDIATE;
15
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 13
diff changeset
747 decoded->src.params.immed = sign_extend8(*istream & 0xFF);
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
748 decoded->dst.addr_mode = MODE_REG;
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
749 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream);
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
750 immed = *istream & 0xFF;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
751 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
752 case OR_DIV_SBCD:
11
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
753 //for OR, if opmode bit 2 is 1, then src = Dn, dst = <ea>
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
754 opmode = (*istream >> 6) & 0x7;
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
755 size = opmode & 0x3;
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
756 if (size == OPSIZE_INVALID || (opmode & 0x4 && !(*istream & 0x30))) {
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
757 switch(opmode)
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
758 {
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
759 case 3:
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
760 decoded->op = M68K_DIVU;
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
761 decoded->extra.size = OPSIZE_WORD;
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
762 decoded->dst.addr_mode = MODE_REG;
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
763 decoded->dst.params.regs.pri = (*istream >> 9) & 0x7;
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
764 istream = m68k_decode_op(istream, OPSIZE_WORD, &(decoded->src));
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
765 break;
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
766 case 4:
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
767 decoded->op = M68K_SBCD;
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
768 decoded->dst.addr_mode = decoded->src.addr_mode = *istream & 0x8 ? MODE_AREG_PREDEC : MODE_REG;
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
769 decoded->src.params.regs.pri = *istream & 0x7;
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
770 decoded->dst.params.regs.pri = (*istream >> 9) & 0x7;
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
771 break;
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
772 case 5:
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
773 #ifdef M68020
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
774 #endif
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
775 break;
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
776 case 6:
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
777 #ifdef M68020
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
778 #endif
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
779 break;
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
780 case 7:
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
781 decoded->op = M68K_DIVS;
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
782 decoded->extra.size = OPSIZE_WORD;
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
783 decoded->dst.addr_mode = MODE_REG;
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
784 decoded->dst.params.regs.pri = (*istream >> 9) & 0x7;
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
785 istream = m68k_decode_op(istream, OPSIZE_WORD, &(decoded->src));
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
786 break;
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
787 }
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
788 } else {
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
789 decoded->op = M68K_OR;
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
790 decoded->extra.size = size;
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
791 if (opmode & 0x4) {
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
792 decoded->src.addr_mode = MODE_REG;
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
793 decoded->src.params.regs.pri = (*istream >> 9) & 0x7;
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
794 istream = m68k_decode_op(istream, size, &(decoded->dst));
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
795 } else {
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
796 decoded->dst.addr_mode = MODE_REG;
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
797 decoded->dst.params.regs.pri = (*istream >> 9) & 0x7;
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
798 istream = m68k_decode_op(istream, size, &(decoded->src));
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
799 }
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
800 }
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
801 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
802 case SUB_SUBX:
101
d7789186ba5e Some fixes to add/addx sub/subx decoding
Mike Pavone <pavone@retrodev.com>
parents: 95
diff changeset
803 size = (*istream >> 6) & 0x3;
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
804 decoded->op = M68K_SUB;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
805 if (*istream & 0x100) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
806 //<ea> destination, SUBA.l or SUBX
101
d7789186ba5e Some fixes to add/addx sub/subx decoding
Mike Pavone <pavone@retrodev.com>
parents: 95
diff changeset
807 if (*istream & 0x30 || size == OPSIZE_INVALID) {
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
808 if (size == OPSIZE_INVALID) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
809 //SUBA.l
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
810 decoded->extra.size = OPSIZE_LONG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
811 decoded->dst.addr_mode = MODE_AREG;
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
812 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream);
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
813 istream = m68k_decode_op(istream, OPSIZE_LONG, &(decoded->src));
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
814 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
815 decoded->extra.size = size;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
816 decoded->src.addr_mode = MODE_REG;
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
817 decoded->src.params.regs.pri = m68k_reg_quick_field(*istream);
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
818 istream = m68k_decode_op(istream, size, &(decoded->dst));
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
819 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
820 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
821 //SUBX
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
822 decoded->op = M68K_SUBX;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
823 decoded->extra.size = size;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
824 istream = m68k_decode_op(istream, size, &(decoded->src));
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
825 decoded->dst.addr_mode = decoded->src.addr_mode;
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
826 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream);
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
827 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
828 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
829 if (size == OPSIZE_INVALID) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
830 //SUBA.w
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
831 decoded->extra.size = OPSIZE_WORD;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
832 decoded->dst.addr_mode = MODE_AREG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
833 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
834 decoded->extra.size = size;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
835 decoded->dst.addr_mode = MODE_REG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
836 }
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
837 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream);
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
838 istream = m68k_decode_op(istream, decoded->extra.size, &(decoded->src));
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
839 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
840 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
841 case RESERVED:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
842 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
843 case CMP_XOR:
120
3648abc45aec Fix decoding of CMPA
Mike Pavone <pavone@retrodev.com>
parents: 116
diff changeset
844 size = (*istream >> 6) & 0x3;
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
845 decoded->op = M68K_CMP;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
846 if (*istream & 0x100) {
120
3648abc45aec Fix decoding of CMPA
Mike Pavone <pavone@retrodev.com>
parents: 116
diff changeset
847 //CMPM or CMPA.l or EOR
3648abc45aec Fix decoding of CMPA
Mike Pavone <pavone@retrodev.com>
parents: 116
diff changeset
848 if (size == OPSIZE_INVALID) {
3648abc45aec Fix decoding of CMPA
Mike Pavone <pavone@retrodev.com>
parents: 116
diff changeset
849 decoded->extra.size = OPSIZE_LONG;
3648abc45aec Fix decoding of CMPA
Mike Pavone <pavone@retrodev.com>
parents: 116
diff changeset
850 decoded->dst.addr_mode = MODE_AREG;
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
851 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream);
136
e64554246d11 Fix some bugs in decoding cmp
Mike Pavone <pavone@retrodev.com>
parents: 134
diff changeset
852 istream = m68k_decode_op(istream, decoded->extra.size, &(decoded->src));
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
853 } else {
120
3648abc45aec Fix decoding of CMPA
Mike Pavone <pavone@retrodev.com>
parents: 116
diff changeset
854 istream = m68k_decode_op(istream, size, &(decoded->dst));
3648abc45aec Fix decoding of CMPA
Mike Pavone <pavone@retrodev.com>
parents: 116
diff changeset
855 if (decoded->src.addr_mode == MODE_AREG) {
3648abc45aec Fix decoding of CMPA
Mike Pavone <pavone@retrodev.com>
parents: 116
diff changeset
856 //CMPM
3648abc45aec Fix decoding of CMPA
Mike Pavone <pavone@retrodev.com>
parents: 116
diff changeset
857 decoded->src.addr_mode = decoded->dst.addr_mode = MODE_AREG_POSTINC;
3648abc45aec Fix decoding of CMPA
Mike Pavone <pavone@retrodev.com>
parents: 116
diff changeset
858 decoded->src.params.regs.pri = decoded->dst.params.regs.pri;
3648abc45aec Fix decoding of CMPA
Mike Pavone <pavone@retrodev.com>
parents: 116
diff changeset
859 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream);
3648abc45aec Fix decoding of CMPA
Mike Pavone <pavone@retrodev.com>
parents: 116
diff changeset
860 } else {
3648abc45aec Fix decoding of CMPA
Mike Pavone <pavone@retrodev.com>
parents: 116
diff changeset
861 //EOR
3648abc45aec Fix decoding of CMPA
Mike Pavone <pavone@retrodev.com>
parents: 116
diff changeset
862 decoded->op = M68K_EOR;
3648abc45aec Fix decoding of CMPA
Mike Pavone <pavone@retrodev.com>
parents: 116
diff changeset
863 decoded->extra.size = size;
3648abc45aec Fix decoding of CMPA
Mike Pavone <pavone@retrodev.com>
parents: 116
diff changeset
864 decoded->src.addr_mode = MODE_REG;
3648abc45aec Fix decoding of CMPA
Mike Pavone <pavone@retrodev.com>
parents: 116
diff changeset
865 decoded->src.params.regs.pri = m68k_reg_quick_field(*istream);
3648abc45aec Fix decoding of CMPA
Mike Pavone <pavone@retrodev.com>
parents: 116
diff changeset
866 }
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
867 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
868 } else {
120
3648abc45aec Fix decoding of CMPA
Mike Pavone <pavone@retrodev.com>
parents: 116
diff changeset
869 //CMP or CMPA.w
3648abc45aec Fix decoding of CMPA
Mike Pavone <pavone@retrodev.com>
parents: 116
diff changeset
870 if (size == OPSIZE_INVALID) {
3648abc45aec Fix decoding of CMPA
Mike Pavone <pavone@retrodev.com>
parents: 116
diff changeset
871 decoded->extra.size = OPSIZE_WORD;
3648abc45aec Fix decoding of CMPA
Mike Pavone <pavone@retrodev.com>
parents: 116
diff changeset
872 decoded->dst.addr_mode = MODE_AREG;
3648abc45aec Fix decoding of CMPA
Mike Pavone <pavone@retrodev.com>
parents: 116
diff changeset
873 } else {
3648abc45aec Fix decoding of CMPA
Mike Pavone <pavone@retrodev.com>
parents: 116
diff changeset
874 decoded->extra.size = size;
3648abc45aec Fix decoding of CMPA
Mike Pavone <pavone@retrodev.com>
parents: 116
diff changeset
875 decoded->dst.addr_mode = MODE_REG;
3648abc45aec Fix decoding of CMPA
Mike Pavone <pavone@retrodev.com>
parents: 116
diff changeset
876 }
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
877 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream);
136
e64554246d11 Fix some bugs in decoding cmp
Mike Pavone <pavone@retrodev.com>
parents: 134
diff changeset
878 istream = m68k_decode_op(istream, decoded->extra.size, &(decoded->src));
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
879 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
880 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
881 case AND_MUL_ABCD_EXG:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
882 //page 575 for summary
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
883 //EXG opmodes:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
884 //01000 -data regs
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
885 //01001 -addr regs
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
886 //10001 -one of each
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
887 //AND opmodes:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
888 //operand order bit + 2 size bits (00 - 10)
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
889 //no address register direct addressing
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
890 //data register direct not allowed when <ea> is the source (operand order bit of 1)
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
891 if (*istream & 0x100) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
892 if ((*istream & 0xC0) == 0xC0) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
893 decoded->op = M68K_MULS;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
894 decoded->extra.size = OPSIZE_WORD;
3
a4ad0e3e3e0e Finish mulu.w, muls.w and abcd parameter decoding
Mike Pavone <pavone@retrodev.com>
parents: 2
diff changeset
895 decoded->dst.addr_mode = MODE_REG;
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
896 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream);
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
897 istream = m68k_decode_op(istream, OPSIZE_WORD, &(decoded->src));
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
898 } else if(!(*istream & 0xF0)) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
899 decoded->op = M68K_ABCD;
3
a4ad0e3e3e0e Finish mulu.w, muls.w and abcd parameter decoding
Mike Pavone <pavone@retrodev.com>
parents: 2
diff changeset
900 decoded->extra.size = OPSIZE_BYTE;
a4ad0e3e3e0e Finish mulu.w, muls.w and abcd parameter decoding
Mike Pavone <pavone@retrodev.com>
parents: 2
diff changeset
901 decoded->src.params.regs.pri = *istream & 0x7;
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
902 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream);
3
a4ad0e3e3e0e Finish mulu.w, muls.w and abcd parameter decoding
Mike Pavone <pavone@retrodev.com>
parents: 2
diff changeset
903 decoded->dst.addr_mode = decoded->src.addr_mode = (*istream & 8) ? MODE_AREG_PREDEC : MODE_REG;
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
904 } else if(!(*istream & 0x30)) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
905 decoded->op = M68K_EXG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
906 decoded->extra.size = OPSIZE_LONG;
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
907 decoded->src.params.regs.pri = m68k_reg_quick_field(*istream);
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
908 decoded->dst.params.regs.pri = *istream & 0x7;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
909 if (*istream & 0x8) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
910 if (*istream & 0x80) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
911 decoded->src.addr_mode = MODE_REG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
912 decoded->dst.addr_mode = MODE_AREG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
913 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
914 decoded->src.addr_mode = decoded->dst.addr_mode = MODE_AREG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
915 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
916 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
917 decoded->src.addr_mode = decoded->dst.addr_mode = MODE_REG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
918 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
919 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
920 decoded->op = M68K_AND;
90
645fe435cb48 Fix decoding of and
Mike Pavone <pavone@retrodev.com>
parents: 79
diff changeset
921 decoded->extra.size = (*istream >> 6) & 0x3;
60
6ffea8607730 Fix operand order for AND instructions
Mike Pavone <pavone@retrodev.com>
parents: 54
diff changeset
922 decoded->src.addr_mode = MODE_REG;
6ffea8607730 Fix operand order for AND instructions
Mike Pavone <pavone@retrodev.com>
parents: 54
diff changeset
923 decoded->src.params.regs.pri = m68k_reg_quick_field(*istream);
6ffea8607730 Fix operand order for AND instructions
Mike Pavone <pavone@retrodev.com>
parents: 54
diff changeset
924 istream = m68k_decode_op(istream, decoded->extra.size, &(decoded->dst));
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
925 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
926 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
927 if ((*istream & 0xC0) == 0xC0) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
928 decoded->op = M68K_MULU;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
929 decoded->extra.size = OPSIZE_WORD;
3
a4ad0e3e3e0e Finish mulu.w, muls.w and abcd parameter decoding
Mike Pavone <pavone@retrodev.com>
parents: 2
diff changeset
930 decoded->dst.addr_mode = MODE_REG;
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
931 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream);
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
932 istream = m68k_decode_op(istream, OPSIZE_WORD, &(decoded->src));
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
933 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
934 decoded->op = M68K_AND;
90
645fe435cb48 Fix decoding of and
Mike Pavone <pavone@retrodev.com>
parents: 79
diff changeset
935 decoded->extra.size = (*istream >> 6) & 0x3;
60
6ffea8607730 Fix operand order for AND instructions
Mike Pavone <pavone@retrodev.com>
parents: 54
diff changeset
936 decoded->dst.addr_mode = MODE_REG;
6ffea8607730 Fix operand order for AND instructions
Mike Pavone <pavone@retrodev.com>
parents: 54
diff changeset
937 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream);
6ffea8607730 Fix operand order for AND instructions
Mike Pavone <pavone@retrodev.com>
parents: 54
diff changeset
938 istream = m68k_decode_op(istream, decoded->extra.size, &(decoded->src));
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
939 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
940 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
941 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
942 case ADD_ADDX:
101
d7789186ba5e Some fixes to add/addx sub/subx decoding
Mike Pavone <pavone@retrodev.com>
parents: 95
diff changeset
943 size = (*istream >> 6) & 0x3;
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
944 decoded->op = M68K_ADD;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
945 if (*istream & 0x100) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
946 //<ea> destination, ADDA.l or ADDX
101
d7789186ba5e Some fixes to add/addx sub/subx decoding
Mike Pavone <pavone@retrodev.com>
parents: 95
diff changeset
947 if (*istream & 0x30 || size == OPSIZE_INVALID) {
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
948 if (size == OPSIZE_INVALID) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
949 //ADDA.l
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
950 decoded->extra.size = OPSIZE_LONG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
951 decoded->dst.addr_mode = MODE_AREG;
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
952 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream);
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
953 istream = m68k_decode_op(istream, OPSIZE_LONG, &(decoded->src));
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
954 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
955 decoded->extra.size = size;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
956 decoded->src.addr_mode = MODE_REG;
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
957 decoded->src.params.regs.pri = m68k_reg_quick_field(*istream);
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
958 istream = m68k_decode_op(istream, size, &(decoded->dst));
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
959 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
960 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
961 //ADDX
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
962 decoded->op = M68K_ADDX;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
963 //FIXME: Size is not technically correct
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
964 decoded->extra.size = size;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
965 istream = m68k_decode_op(istream, size, &(decoded->src));
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
966 decoded->dst.addr_mode = decoded->src.addr_mode;
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
967 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream);
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
968 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
969 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
970 if (size == OPSIZE_INVALID) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
971 //ADDA.w
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
972 decoded->extra.size = OPSIZE_WORD;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
973 decoded->dst.addr_mode = MODE_AREG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
974 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
975 decoded->extra.size = size;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
976 decoded->dst.addr_mode = MODE_REG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
977 }
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
978 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream);
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
979 istream = m68k_decode_op(istream, decoded->extra.size, &(decoded->src));
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
980 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
981 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
982 case SHIFT_ROTATE:
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
983 if ((*istream & 0x8C0) == 0xC0) {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
984 switch((*istream >> 8) & 0x7)
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
985 {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
986 case 0:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
987 decoded->op = M68K_ASR;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
988 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
989 case 1:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
990 decoded->op = M68K_ASL;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
991 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
992 case 2:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
993 decoded->op = M68K_LSR;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
994 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
995 case 3:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
996 decoded->op = M68K_LSL;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
997 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
998 case 4:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
999 decoded->op = M68K_ROXR;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1000 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1001 case 5:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1002 decoded->op = M68K_ROXL;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1003 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1004 case 6:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1005 decoded->op = M68K_ROR;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1006 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1007 case 7:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1008 decoded->op = M68K_ROL;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1009 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1010 }
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1011 decoded->extra.size = OPSIZE_WORD;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1012 istream = m68k_decode_op(istream, OPSIZE_WORD, &(decoded->dst));
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1013 } else if((*istream & 0xC0) != 0xC0) {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1014 switch(((*istream >> 2) & 0x6) | ((*istream >> 8) & 1))
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1015 {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1016 case 0:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1017 decoded->op = M68K_ASR;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1018 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1019 case 1:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1020 decoded->op = M68K_ASL;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1021 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1022 case 2:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1023 decoded->op = M68K_LSR;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1024 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1025 case 3:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1026 decoded->op = M68K_LSL;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1027 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1028 case 4:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1029 decoded->op = M68K_ROXR;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1030 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1031 case 5:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1032 decoded->op = M68K_ROXL;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1033 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1034 case 6:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1035 decoded->op = M68K_ROR;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1036 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1037 case 7:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1038 decoded->op = M68K_ROL;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1039 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1040 }
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1041 decoded->extra.size = (*istream >> 6) & 0x3;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1042 immed = (*istream >> 9) & 0x7;
51
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 50
diff changeset
1043 if (*istream & 0x20) {
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1044 decoded->src.addr_mode = MODE_REG;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1045 decoded->src.params.regs.pri = immed;
50
4836d1f3841a Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1046 } else {
4836d1f3841a Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1047 decoded->src.addr_mode = MODE_IMMEDIATE;
4836d1f3841a Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1048 if (!immed) {
4836d1f3841a Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1049 immed = 8;
4836d1f3841a Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1050 }
4836d1f3841a Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1051 decoded->src.params.immed = immed;
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1052 }
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1053 decoded->dst.addr_mode = MODE_REG;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1054 decoded->dst.params.regs.pri = *istream & 0x7;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1055
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1056 } else {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1057 #ifdef M68020
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1058 //TODO: Implement bitfield instructions for M68020+ support
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1059 #endif
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1060 }
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1061 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1062 case COPROC:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1063 //TODO: Implement me
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1064 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1065 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1066 return istream+1;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1067 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1068
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1069 char * mnemonics[] = {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1070 "abcd",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1071 "add",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1072 "addx",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1073 "and",
13
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
1074 "andi",//ccr
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
1075 "andi",//sr
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1076 "asl",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1077 "asr",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1078 "bcc",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1079 "bchg",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1080 "bclr",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1081 "bset",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1082 "bsr",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1083 "btst",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1084 "chk",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1085 "clr",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1086 "cmp",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1087 "dbcc",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1088 "divs",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1089 "divu",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1090 "eor",
13
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
1091 "eori",//ccr
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
1092 "eori",//sr
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1093 "exg",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1094 "ext",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1095 "illegal",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1096 "jmp",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1097 "jsr",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1098 "lea",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1099 "link",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1100 "lsl",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1101 "lsr",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1102 "move",
13
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
1103 "move",//ccr
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
1104 "move",//from_sr
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
1105 "move",//sr
50
4836d1f3841a Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1106 "move",//usp
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1107 "movem",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1108 "movep",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1109 "muls",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1110 "mulu",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1111 "nbcd",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1112 "neg",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1113 "negx",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1114 "nop",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1115 "not",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1116 "or",
13
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
1117 "ori",//ccr
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
1118 "ori",//sr
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1119 "pea",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1120 "reset",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1121 "rol",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1122 "ror",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1123 "roxl",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1124 "roxr",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1125 "rte",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1126 "rtr",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1127 "rts",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1128 "sbcd",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1129 "scc",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1130 "stop",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1131 "sub",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1132 "subx",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1133 "swap",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1134 "tas",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1135 "trap",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1136 "trapv",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1137 "tst",
12
db60ed283d8d Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions.
Mike Pavone <pavone@retrodev.com>
parents: 11
diff changeset
1138 "unlk",
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1139 "invalid"
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1140 };
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1141
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1142 char * cond_mnem[] = {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1143 "ra",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1144 "f",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1145 "hi",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1146 "ls",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1147 "cc",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1148 "cs",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1149 "ne",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1150 "eq",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1151 "vc",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1152 "vs",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1153 "pl",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1154 "mi",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1155 "ge",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1156 "lt",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1157 "gt",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1158 "le"
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1159 };
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1160
134
ab50421b1b7a Improve disassembler
Mike Pavone <pavone@retrodev.com>
parents: 120
diff changeset
1161 int m68k_disasm_op(m68k_op_info *decoded, char *dst, int need_comma, uint8_t labels, uint32_t address)
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1162 {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1163 char * c = need_comma ? "," : "";
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1164 switch(decoded->addr_mode)
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1165 {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1166 case MODE_REG:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1167 return sprintf(dst, "%s d%d", c, decoded->params.regs.pri);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1168 case MODE_AREG:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1169 return sprintf(dst, "%s a%d", c, decoded->params.regs.pri);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1170 case MODE_AREG_INDIRECT:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1171 return sprintf(dst, "%s (a%d)", c, decoded->params.regs.pri);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1172 case MODE_AREG_POSTINC:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1173 return sprintf(dst, "%s (a%d)+", c, decoded->params.regs.pri);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1174 case MODE_AREG_PREDEC:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1175 return sprintf(dst, "%s -(a%d)", c, decoded->params.regs.pri);
13
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
1176 case MODE_AREG_DISPLACE:
79
d212e0cd0b7e Implement indexed with 8-bit displacement addressing modes in decoder and disassembler
Mike Pavone <pavone@retrodev.com>
parents: 69
diff changeset
1177 return sprintf(dst, "%s (%d, a%d)", c, decoded->params.regs.displacement, decoded->params.regs.pri);
d212e0cd0b7e Implement indexed with 8-bit displacement addressing modes in decoder and disassembler
Mike Pavone <pavone@retrodev.com>
parents: 69
diff changeset
1178 case MODE_AREG_INDEX_DISP8:
d212e0cd0b7e Implement indexed with 8-bit displacement addressing modes in decoder and disassembler
Mike Pavone <pavone@retrodev.com>
parents: 69
diff changeset
1179 return sprintf(dst, "%s (%d, a%d, %c%d.%c)", c, decoded->params.regs.displacement, decoded->params.regs.pri, (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w');
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1180 case MODE_IMMEDIATE:
61
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 60
diff changeset
1181 case MODE_IMMEDIATE_WORD:
62
b37cb596bc21 Print out large immediate values in hex rather than decimal form
Mike Pavone <pavone@retrodev.com>
parents: 61
diff changeset
1182 return sprintf(dst, (decoded->params.immed <= 128 ? "%s #%d" : "%s #$%X"), c, decoded->params.immed);
13
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
1183 case MODE_ABSOLUTE_SHORT:
134
ab50421b1b7a Improve disassembler
Mike Pavone <pavone@retrodev.com>
parents: 120
diff changeset
1184 if (labels) {
140
18796a3b0fe2 Fix label names in disassembler
Mike Pavone <pavone@retrodev.com>
parents: 136
diff changeset
1185 return sprintf(dst, "%s ADR_%X.w", c, decoded->params.immed);
134
ab50421b1b7a Improve disassembler
Mike Pavone <pavone@retrodev.com>
parents: 120
diff changeset
1186 } else {
ab50421b1b7a Improve disassembler
Mike Pavone <pavone@retrodev.com>
parents: 120
diff changeset
1187 return sprintf(dst, "%s $%X.w", c, decoded->params.immed);
ab50421b1b7a Improve disassembler
Mike Pavone <pavone@retrodev.com>
parents: 120
diff changeset
1188 }
13
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
1189 case MODE_ABSOLUTE:
134
ab50421b1b7a Improve disassembler
Mike Pavone <pavone@retrodev.com>
parents: 120
diff changeset
1190 if (labels) {
140
18796a3b0fe2 Fix label names in disassembler
Mike Pavone <pavone@retrodev.com>
parents: 136
diff changeset
1191 return sprintf(dst, "%s ADR_%X.l", c, decoded->params.immed);
134
ab50421b1b7a Improve disassembler
Mike Pavone <pavone@retrodev.com>
parents: 120
diff changeset
1192 } else {
ab50421b1b7a Improve disassembler
Mike Pavone <pavone@retrodev.com>
parents: 120
diff changeset
1193 return sprintf(dst, "%s $%X", c, decoded->params.immed);
ab50421b1b7a Improve disassembler
Mike Pavone <pavone@retrodev.com>
parents: 120
diff changeset
1194 }
13
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
1195 case MODE_PC_DISPLACE:
134
ab50421b1b7a Improve disassembler
Mike Pavone <pavone@retrodev.com>
parents: 120
diff changeset
1196 if (labels) {
140
18796a3b0fe2 Fix label names in disassembler
Mike Pavone <pavone@retrodev.com>
parents: 136
diff changeset
1197 return sprintf(dst, "%s ADR_%X(pc)", c, address + 2 + decoded->params.regs.displacement);
134
ab50421b1b7a Improve disassembler
Mike Pavone <pavone@retrodev.com>
parents: 120
diff changeset
1198 } else {
ab50421b1b7a Improve disassembler
Mike Pavone <pavone@retrodev.com>
parents: 120
diff changeset
1199 return sprintf(dst, "%s (%d, pc)", c, decoded->params.regs.displacement);
ab50421b1b7a Improve disassembler
Mike Pavone <pavone@retrodev.com>
parents: 120
diff changeset
1200 }
79
d212e0cd0b7e Implement indexed with 8-bit displacement addressing modes in decoder and disassembler
Mike Pavone <pavone@retrodev.com>
parents: 69
diff changeset
1201 case MODE_PC_INDEX_DISP8:
d212e0cd0b7e Implement indexed with 8-bit displacement addressing modes in decoder and disassembler
Mike Pavone <pavone@retrodev.com>
parents: 69
diff changeset
1202 return sprintf(dst, "%s (%d, pc, %c%d.%c)", c, decoded->params.regs.displacement, (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w');
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1203 default:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1204 return 0;
0
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1205 }
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1206 }
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1207
134
ab50421b1b7a Improve disassembler
Mike Pavone <pavone@retrodev.com>
parents: 120
diff changeset
1208 int m68k_disasm_movem_op(m68k_op_info *decoded, m68k_op_info *other, char *dst, int need_comma, uint8_t labels, uint32_t address)
13
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
1209 {
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
1210 int8_t dir, reg, bit, regnum, last=-1, lastreg, first=-1;
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
1211 char *rtype, *last_rtype;
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
1212 int oplen;
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
1213 if (decoded->addr_mode == MODE_REG) {
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
1214 if (other->addr_mode == MODE_AREG_PREDEC) {
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
1215 bit = 15;
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
1216 dir = -1;
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
1217 } else {
69
36f1133837d0 Fix disassembly of reg list in MOVEM when the reg list is the destination
Mike Pavone <pavone@retrodev.com>
parents: 68
diff changeset
1218 dir = 1;
36f1133837d0 Fix disassembly of reg list in MOVEM when the reg list is the destination
Mike Pavone <pavone@retrodev.com>
parents: 68
diff changeset
1219 bit = 0;
13
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
1220 }
68
1c9a4052a2c0 Fix decoding and disassembly of MOVEM
Mike Pavone <pavone@retrodev.com>
parents: 62
diff changeset
1221 if (need_comma) {
1c9a4052a2c0 Fix decoding and disassembly of MOVEM
Mike Pavone <pavone@retrodev.com>
parents: 62
diff changeset
1222 strcat(dst, ", ");
1c9a4052a2c0 Fix decoding and disassembly of MOVEM
Mike Pavone <pavone@retrodev.com>
parents: 62
diff changeset
1223 oplen = 2;
1c9a4052a2c0 Fix decoding and disassembly of MOVEM
Mike Pavone <pavone@retrodev.com>
parents: 62
diff changeset
1224 } else {
1c9a4052a2c0 Fix decoding and disassembly of MOVEM
Mike Pavone <pavone@retrodev.com>
parents: 62
diff changeset
1225 strcat(dst, " ");
1c9a4052a2c0 Fix decoding and disassembly of MOVEM
Mike Pavone <pavone@retrodev.com>
parents: 62
diff changeset
1226 oplen = 1;
1c9a4052a2c0 Fix decoding and disassembly of MOVEM
Mike Pavone <pavone@retrodev.com>
parents: 62
diff changeset
1227 }
1c9a4052a2c0 Fix decoding and disassembly of MOVEM
Mike Pavone <pavone@retrodev.com>
parents: 62
diff changeset
1228 for (reg=0; bit < 16 && bit > -1; bit += dir, reg++) {
15
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 13
diff changeset
1229 if (decoded->params.immed & (1 << bit)) {
13
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
1230 if (reg > 7) {
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
1231 rtype = "a";
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
1232 regnum = reg - 8;
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
1233 } else {
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
1234 rtype = "d";
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
1235 regnum = reg;
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
1236 }
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
1237 if (last >= 0 && last == regnum - 1 && lastreg == reg - 1) {
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
1238 last = regnum;
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
1239 lastreg = reg;
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
1240 } else if(last >= 0) {
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
1241 if (first != last) {
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
1242 oplen += sprintf(dst + oplen, "-%s%d/%s%d",last_rtype, last, rtype, regnum);
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
1243 } else {
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
1244 oplen += sprintf(dst + oplen, "/%s%d", rtype, regnum);
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
1245 }
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
1246 first = last = regnum;
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
1247 last_rtype = rtype;
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
1248 lastreg = reg;
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
1249 } else {
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
1250 oplen += sprintf(dst + oplen, "%s%d", rtype, regnum);
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
1251 first = last = regnum;
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
1252 last_rtype = rtype;
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
1253 lastreg = reg;
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
1254 }
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
1255 }
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
1256 }
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
1257 if (last >= 0 && last != first) {
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
1258 oplen += sprintf(dst + oplen, "-%s%d", last_rtype, last);
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
1259 }
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
1260 return oplen;
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
1261 } else {
134
ab50421b1b7a Improve disassembler
Mike Pavone <pavone@retrodev.com>
parents: 120
diff changeset
1262 return m68k_disasm_op(decoded, dst, need_comma, labels, address);
13
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
1263 }
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
1264 }
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
1265
134
ab50421b1b7a Improve disassembler
Mike Pavone <pavone@retrodev.com>
parents: 120
diff changeset
1266 int m68k_disasm_ex(m68kinst * decoded, char * dst, uint8_t labels)
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1267 {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1268 int ret,op1len;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1269 uint8_t size;
13
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
1270 char * special_op = "CCR";
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
1271 switch (decoded->op)
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
1272 {
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
1273 case M68K_BCC:
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
1274 case M68K_DBCC:
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
1275 case M68K_SCC:
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1276 ret = strlen(mnemonics[decoded->op]) - 2;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1277 memcpy(dst, mnemonics[decoded->op], ret);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1278 dst[ret] = 0;
50
4836d1f3841a Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1279 strcpy(dst+ret, cond_mnem[decoded->extra.cond]);
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1280 ret = strlen(dst);
50
4836d1f3841a Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1281 if (decoded->op != M68K_SCC) {
134
ab50421b1b7a Improve disassembler
Mike Pavone <pavone@retrodev.com>
parents: 120
diff changeset
1282 if (labels) {
ab50421b1b7a Improve disassembler
Mike Pavone <pavone@retrodev.com>
parents: 120
diff changeset
1283 if (decoded->op == M68K_DBCC) {
140
18796a3b0fe2 Fix label names in disassembler
Mike Pavone <pavone@retrodev.com>
parents: 136
diff changeset
1284 ret += sprintf(dst+ret, " d%d, ADR_%X", decoded->dst.params.regs.pri, decoded->address + 2 + decoded->src.params.immed);
134
ab50421b1b7a Improve disassembler
Mike Pavone <pavone@retrodev.com>
parents: 120
diff changeset
1285 } else {
140
18796a3b0fe2 Fix label names in disassembler
Mike Pavone <pavone@retrodev.com>
parents: 136
diff changeset
1286 ret += sprintf(dst+ret, " ADR_%X", decoded->address + 2 + decoded->src.params.immed);
134
ab50421b1b7a Improve disassembler
Mike Pavone <pavone@retrodev.com>
parents: 120
diff changeset
1287 }
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
1288 } else {
134
ab50421b1b7a Improve disassembler
Mike Pavone <pavone@retrodev.com>
parents: 120
diff changeset
1289 if (decoded->op == M68K_DBCC) {
ab50421b1b7a Improve disassembler
Mike Pavone <pavone@retrodev.com>
parents: 120
diff changeset
1290 ret += sprintf(dst+ret, " d%d, #%d <%X>", decoded->dst.params.regs.pri, decoded->src.params.immed, decoded->address + 2 + decoded->src.params.immed);
ab50421b1b7a Improve disassembler
Mike Pavone <pavone@retrodev.com>
parents: 120
diff changeset
1291 } else {
ab50421b1b7a Improve disassembler
Mike Pavone <pavone@retrodev.com>
parents: 120
diff changeset
1292 ret += sprintf(dst+ret, " #%d <%X>", decoded->src.params.immed, decoded->address + 2 + decoded->src.params.immed);
ab50421b1b7a Improve disassembler
Mike Pavone <pavone@retrodev.com>
parents: 120
diff changeset
1293 }
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
1294 }
50
4836d1f3841a Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1295 return ret;
4836d1f3841a Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1296 }
13
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
1297 break;
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
1298 case M68K_BSR:
134
ab50421b1b7a Improve disassembler
Mike Pavone <pavone@retrodev.com>
parents: 120
diff changeset
1299 if (labels) {
140
18796a3b0fe2 Fix label names in disassembler
Mike Pavone <pavone@retrodev.com>
parents: 136
diff changeset
1300 ret = sprintf(dst, "bsr%s ADR_%X", decoded->variant == VAR_BYTE ? ".s" : "",
134
ab50421b1b7a Improve disassembler
Mike Pavone <pavone@retrodev.com>
parents: 120
diff changeset
1301 decoded->address + 2 + decoded->src.params.immed);
ab50421b1b7a Improve disassembler
Mike Pavone <pavone@retrodev.com>
parents: 120
diff changeset
1302 } else {
ab50421b1b7a Improve disassembler
Mike Pavone <pavone@retrodev.com>
parents: 120
diff changeset
1303 ret = sprintf(dst, "bsr%s #%d <%X>", decoded->variant == VAR_BYTE ? ".s" : "", decoded->src.params.immed, decoded->address + 2 + decoded->src.params.immed);
ab50421b1b7a Improve disassembler
Mike Pavone <pavone@retrodev.com>
parents: 120
diff changeset
1304 }
50
4836d1f3841a Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1305 return ret;
13
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
1306 case M68K_MOVE_FROM_SR:
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
1307 ret = sprintf(dst, "%s", mnemonics[decoded->op]);
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
1308 ret += sprintf(dst + ret, " SR");
134
ab50421b1b7a Improve disassembler
Mike Pavone <pavone@retrodev.com>
parents: 120
diff changeset
1309 ret += m68k_disasm_op(&(decoded->dst), dst + ret, 1, labels, decoded->address);
13
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
1310 return ret;
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
1311 case M68K_ANDI_SR:
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
1312 case M68K_EORI_SR:
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
1313 case M68K_MOVE_SR:
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
1314 case M68K_ORI_SR:
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
1315 special_op = "SR";
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
1316 case M68K_ANDI_CCR:
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
1317 case M68K_EORI_CCR:
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
1318 case M68K_MOVE_CCR:
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
1319 case M68K_ORI_CCR:
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
1320 ret = sprintf(dst, "%s", mnemonics[decoded->op]);
134
ab50421b1b7a Improve disassembler
Mike Pavone <pavone@retrodev.com>
parents: 120
diff changeset
1321 ret += m68k_disasm_op(&(decoded->src), dst + ret, 0, labels, decoded->address);
13
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
1322 ret += sprintf(dst + ret, ", %s", special_op);
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
1323 return ret;
50
4836d1f3841a Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1324 case M68K_MOVE_USP:
4836d1f3841a Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1325 ret = sprintf(dst, "%s", mnemonics[decoded->op]);
4836d1f3841a Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1326 if (decoded->src.addr_mode != MODE_UNUSED) {
134
ab50421b1b7a Improve disassembler
Mike Pavone <pavone@retrodev.com>
parents: 120
diff changeset
1327 ret += m68k_disasm_op(&(decoded->src), dst + ret, 0, labels, decoded->address);
50
4836d1f3841a Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1328 ret += sprintf(dst + ret, ", USP");
4836d1f3841a Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1329 } else {
4836d1f3841a Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1330 ret += sprintf(dst + ret, "USP, ");
134
ab50421b1b7a Improve disassembler
Mike Pavone <pavone@retrodev.com>
parents: 120
diff changeset
1331 ret += m68k_disasm_op(&(decoded->dst), dst + ret, 0, labels, decoded->address);
50
4836d1f3841a Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1332 }
4836d1f3841a Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1333 return ret;
13
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
1334 default:
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1335 size = decoded->extra.size;
13
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
1336 ret = sprintf(dst, "%s%s%s",
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1337 mnemonics[decoded->op],
8
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
1338 decoded->variant == VAR_QUICK ? "q" : (decoded->variant == VAR_IMMEDIATE ? "i" : ""),
13
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
1339 size == OPSIZE_BYTE ? ".b" : (size == OPSIZE_WORD ? ".w" : (size == OPSIZE_LONG ? ".l" : "")));
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1340 }
13
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
1341 if (decoded->op == M68K_MOVEM) {
134
ab50421b1b7a Improve disassembler
Mike Pavone <pavone@retrodev.com>
parents: 120
diff changeset
1342 op1len = m68k_disasm_movem_op(&(decoded->src), &(decoded->dst), dst + ret, 0, labels, decoded->address);
13
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
1343 ret += op1len;
134
ab50421b1b7a Improve disassembler
Mike Pavone <pavone@retrodev.com>
parents: 120
diff changeset
1344 ret += m68k_disasm_movem_op(&(decoded->dst), &(decoded->src), dst + ret, op1len, labels, decoded->address);
13
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
1345 } else {
134
ab50421b1b7a Improve disassembler
Mike Pavone <pavone@retrodev.com>
parents: 120
diff changeset
1346 op1len = m68k_disasm_op(&(decoded->src), dst + ret, 0, labels, decoded->address);
13
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
1347 ret += op1len;
134
ab50421b1b7a Improve disassembler
Mike Pavone <pavone@retrodev.com>
parents: 120
diff changeset
1348 ret += m68k_disasm_op(&(decoded->dst), dst + ret, op1len, labels, decoded->address);
13
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
1349 }
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1350 return ret;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1351 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1352
134
ab50421b1b7a Improve disassembler
Mike Pavone <pavone@retrodev.com>
parents: 120
diff changeset
1353 int m68k_disasm(m68kinst * decoded, char * dst)
ab50421b1b7a Improve disassembler
Mike Pavone <pavone@retrodev.com>
parents: 120
diff changeset
1354 {
ab50421b1b7a Improve disassembler
Mike Pavone <pavone@retrodev.com>
parents: 120
diff changeset
1355 return m68k_disasm_ex(decoded, dst, 0);
ab50421b1b7a Improve disassembler
Mike Pavone <pavone@retrodev.com>
parents: 120
diff changeset
1356 }
ab50421b1b7a Improve disassembler
Mike Pavone <pavone@retrodev.com>
parents: 120
diff changeset
1357
ab50421b1b7a Improve disassembler
Mike Pavone <pavone@retrodev.com>
parents: 120
diff changeset
1358 int m68k_disasm_labels(m68kinst * decoded, char * dst)
ab50421b1b7a Improve disassembler
Mike Pavone <pavone@retrodev.com>
parents: 120
diff changeset
1359 {
ab50421b1b7a Improve disassembler
Mike Pavone <pavone@retrodev.com>
parents: 120
diff changeset
1360 return m68k_disasm_ex(decoded, dst, 1);
ab50421b1b7a Improve disassembler
Mike Pavone <pavone@retrodev.com>
parents: 120
diff changeset
1361 }