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annotate z80.cpu @ 1742:6290c88949bd

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Fixed CPI/CPD/CPIR/CPDR in new Z80 core
author Michael Pavone <pavone@retrodev.com>
date Mon, 04 Feb 2019 23:46:35 -0800
parents 3dbfb4524ad2
children a1663a83dcab
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1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
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1 info
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2 prefix z80_
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3 opcode_size 8
1721
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
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4 extra_tables cb ed dded fded ddcb fdcb dd fd
1706
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5 body z80_run_op
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6 include z80_util.c
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7 header z80.h
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8
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9 regs
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10 main 8 b c d e h l f a
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11 alt 8 b' c' d' e' h' l' f' a'
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12 i 8
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13 r 8
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3b286be82ea5 Implemented ld a,r and ld a,i in new Z80 core
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14 rhigh 8
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15 iff1 8
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16 iff2 8
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17 imode 8
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18 sp 16
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19 ix 16
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20 iy 16
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21 pc 16
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22 wz 16
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23 nflag 8
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24 last_flag_result 8
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25 pvflag 8
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26 chflags 8
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27 zflag 8
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28 scratch1 16
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29 scratch2 16
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ca2336469397 Get new Z80 core running in CPM harness
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30 io_map ptrmemmap_chunk
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31 io_chunks 32
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32 io_mask 32
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33
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34 flags
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35 register f
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36 S 7 sign last_flag_result.7
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37 Z 6 zero zflag
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38 Y 5 bit-5 last_flag_result.5
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39 H 4 half-carry chflags.3
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40 P 2 parity pvflag
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41 V 2 overflow pvflag
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42 X 3 bit-3 last_flag_result.3
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43 N 1 none nflag
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44 C 0 carry chflags.7
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45
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46
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47 z80_op_fetch
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48 cycles 1
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49 add 1 r r
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50 mov pc scratch1
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51 ocall read_8
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52 add 1 pc pc
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53
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54 z80_run_op
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55 z80_op_fetch
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56 dispatch scratch1
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57
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58 11001011 cb_prefix
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59 z80_op_fetch
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60 dispatch scratch1 cb
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61
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62 11011101 dd_prefix
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63 z80_op_fetch
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64 dispatch scratch1 dd
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65
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0a9a88b3d061 Fix ED prefix in new Z80 core
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66 11101101 ed_prefix
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67 z80_op_fetch
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68 dispatch scratch1 ed
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69
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70 11111101 fd_prefix
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71 z80_op_fetch
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72 dispatch scratch1 fd
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73
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74 dd 11001011 ddcb_prefix
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75 z80_calc_index ix
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76 cycles 2
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77 mov pc scratch1
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78 ocall read_8
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79 add 1 pc pc
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80 dispatch scratch1 ddcb
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81
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82 fd 11001011 fdcb_prefix
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83 z80_calc_index iy
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84 cycles 2
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85 mov pc scratch1
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86 ocall read_8
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87 add 1 pc pc
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88 dispatch scratch1 fdcb
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89
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90 z80_check_cond
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91 arg cond 8
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92 local invert 8
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93 switch cond
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94 case 0
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95 meta istrue invert
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96 lnot zflag invert
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97
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98 case 1
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99 meta istrue zflag
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100
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101 case 2
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102 meta istrue invert
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103 not chflags invert
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104 and 0x80 invert invert
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105
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106 case 3
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107 meta istrue invert
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89ee53a149ea Miscellaneous small fixes to new Z80 core
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108 and 0x80 chflags invert
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109
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110 case 4
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111 meta istrue invert
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112 lnot pvflag invert
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113
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114 case 5
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115 meta istrue pvflag
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116
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117 case 6
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118 meta istrue invert
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119 not last_flag_result invert
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120 and 0x80 invert invert
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121
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122 case 7
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123 meta istrue invert
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124 and 0x80 last_flag_result invert
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125
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126 end
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127
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128 z80_fetch_hl
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129 lsl h 8 scratch1
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130 or l scratch1 scratch1
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131 ocall read_8
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132
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133 z80_store_hl
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134 lsl h 8 scratch2
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135 or l scratch2 scratch2
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136 ocall write_8
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137
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138 z80_fetch_immed
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139 mov pc scratch1
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140 ocall read_8
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141 add 1 pc pc
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142
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143 z80_fetch_immed16
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144 mov pc scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
145 ocall read_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
146 mov scratch1 wz
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
147 add 1 pc pc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
148 mov pc scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
149 ocall read_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
150 add 1 pc pc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
151 lsl scratch1 8 scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
152 or scratch1 wz wz
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
153
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
154 z80_fetch_immed_reg16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
155 mov pc scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
156 ocall read_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
157 mov scratch1 low
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
158 add 1 pc pc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
159 mov pc scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
160 ocall read_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
161 mov scratch1 high
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
162 add 1 pc pc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
163
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
164 z80_fetch_immed_to_reg16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
165 mov pc scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
166 ocall read_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
167 mov scratch1 reg
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
168 add 1 pc pc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
169 mov pc scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
170 ocall read_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
171 add 1 pc pc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
172 lsl scratch1 8 scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
173 or scratch1 reg reg
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
174
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
175 01RRR110 ld_from_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
176 z80_fetch_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
177 mov scratch1 main.R
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
178
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
179 01DDDSSS ld_from_reg
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
180 mov main.S main.D
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
181
1730
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
182 dd 01DDD100 ld_from_ixh
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
183 invalid D 6
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
184 lsr ix 8 main.D
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
185
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
186 dd 01100SSS ld_to_ixh
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
187 invalid S 6
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
188 local tmp 16
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
189 and 0xFF ix ix
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
190 lsl main.S 8 tmp
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
191 or tmp ix ix
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
192
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
193 dd 0110D10S ld_ixb_to_ixb
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
194
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
195 dd 01DDD101 ld_from_ixl
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
196 invalid D 6
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
197 mov ix main.D
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
198
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
199 dd 01101SSS ld_to_ixl
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
200 invalid S 6
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
201 and 0xFF00 ix ix
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
202 or main.S ix ix
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
203
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
204 dd 01100101 ld_ixl_to_ixh
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
205 local tmp 16
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
206 lsl ix 8 tmp
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
207 and 0xFF ix ix
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
208 or tmp ix ix
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
209
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
210 dd 01101100 ld_ixh_to_ixl
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
211 local tmp 16
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
212 lsr ix 8 tmp
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
213 and 0xFF00 ix ix
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
214 or tmp ix ix
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
215
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
216 fd 01DDD100 ld_from_iyh
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
217 invalid D 6
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
218 lsr iy 8 main.D
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
219
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
220 fd 01100SSS ld_to_iyh
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
221 invalid S 6
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
222 local tmp 16
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
223 and 0xFF iy iy
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
224 lsl main.S 8 tmp
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
225 or tmp iy iy
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
226
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
227 fd 0110D10S ld_iyb_to_iyb
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
228
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
229 fd 01DDD101 ld_from_iyl
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
230 invalid D 6
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
231 mov iy main.D
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
232
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
233 fd 01101SSS ld_to_iyl
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
234 invalid S 6
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
235 and 0xFF00 iy iy
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
236 or main.S iy iy
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
237
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
238 fd 01100101 ld_iyl_to_iyh
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
239 local tmp 16
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
240 lsl iy 8 tmp
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
241 and 0xFF iy iy
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
242 or tmp iy iy
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
243
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
244 fd 01101100 ld_iyh_to_iyl
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
245 local tmp 16
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
246 lsr iy 8 tmp
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
247 and 0xFF00 iy iy
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
248 or tmp iy iy
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
249
1717
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
250 z80_calc_index
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
251 arg index 16
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
252 mov index wz
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
253 z80_fetch_immed
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
254 sext 16 scratch1 scratch1
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
255 add scratch1 wz wz
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
256
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
257 z80_fetch_index
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
258 arg index 16
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
259 z80_calc_index index
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
260 mov wz scratch1
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
261 cycles 5
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
262 ocall read_8
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
263
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
264 z80_store_index
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
265 mov wz scratch2
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
266 ocall write_8
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
267
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
268 dd 01RRR110 ld_from_ix
1717
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
269 z80_fetch_index ix
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
270 mov scratch1 main.R
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
271
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
272 fd 01RRR110 ld_from_iy
1717
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
273 z80_fetch_index iy
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
274 mov scratch1 main.R
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
275
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
276 00RRR110 ld_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
277 z80_fetch_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
278 mov scratch1 main.R
1730
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
279
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
280 dd 00100110 ld_immed_ixh
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
281 z80_fetch_immed
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
282 lsl scratch1 8 scratch1
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
283 and 0xFF ix ix
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
284 or scratch1 ix ix
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
285
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
286 dd 00101110 ld_immed_ixl
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
287 z80_fetch_immed
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
288 and 0xFF00 ix ix
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
289 or scratch1 ix ix
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
290
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
291 fd 00100110 ld_immed_iyh
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
292 z80_fetch_immed
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
293 lsl scratch1 8 scratch1
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
294 and 0xFF iy iy
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
295 or scratch1 iy iy
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
296
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
297 fd 00101110 ld_immed_iyl
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
298 z80_fetch_immed
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
299 and 0xFF00 iy iy
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
300 or scratch1 iy iy
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
301
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
302 01110RRR ld_to_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
303 mov main.R scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
304 z80_store_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
305
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
306 dd 01110RRR ld_to_ix
1717
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
307 z80_calc_index ix
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
308 mov wz scratch2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
309 mov main.R scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
310 ocall write_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
311
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
312 fd 01110RRR ld_to_iy
1717
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
313 z80_calc_index iy
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
314 mov wz scratch2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
315 mov main.R scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
316 ocall write_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
317
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
318 00110110 ld_to_hl_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
319 z80_fetch_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
320 z80_store_hl
1730
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
321
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
322 dd 00110110 ld_to_ixd_immed
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
323 z80_calc_index ix
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
324 z80_fetch_immed
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
325 cycles 2
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
326 mov wz scratch2
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
327 ocall write_8
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
328
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
329 fd 00110110 ld_to_iyd_immed
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
330 z80_calc_index iy
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
331 z80_fetch_immed
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
332 cycles 2
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
333 mov wz scratch2
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
334 ocall write_8
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
335
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
336 00001010 ld_a_from_bc
1727
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
337 lsl b 8 wz
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
338 or c wz wz
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
339 mov wz scratch1
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
340 add 1 wz wz
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
341 ocall read_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
342 mov scratch1 a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
343
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
344 00011010 ld_a_from_de
1727
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
345 lsl d 8 wz
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
346 or e wz wz
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
347 mov wz scratch1
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
348 add 1 wz wz
1724
9a74c2d05672 Fixed a few ld instructions in the new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1723
diff changeset
349 ocall read_8
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
350 mov scratch1 a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
351
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
352 00111010 ld_a_from_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
353 z80_fetch_immed16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
354 mov wz scratch1
1727
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
355 add 1 wz wz
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
356 ocall read_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
357 mov scratch1 a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
358
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
359 00000010 ld_a_to_bc
1727
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
360 local tmp 8
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
361 lsl b 8 scratch2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
362 or c scratch2 scratch2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
363 mov a scratch1
1727
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
364 add c 1 tmp
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
365 lsl a 8 wz
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
366 or tmp wz wz
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
367 ocall write_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
368
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
369 00010010 ld_a_to_de
1727
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
370 local tmp 8
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
371 lsl d 8 scratch2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
372 or e scratch2 scratch2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
373 mov a scratch1
1727
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
374 add e 1 tmp
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
375 lsl a 8 wz
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
376 or tmp wz wz
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
377 ocall write_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
378
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
379 00110010 ld_a_to_immed
1727
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
380 local tmp 16
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
381 z80_fetch_immed16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
382 mov wz scratch2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
383 mov a scratch1
1727
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
384 add 1 wz wz
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
385 ocall write_8
1727
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
386 and 0xFF wz wz
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
387 lsl a 8 tmp
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
388 or tmp wz wz
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
389
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
390 ed 01000111 ld_i_a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
391 mov a i
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
392 cycles 1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
393
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
394 ed 01001111 ld_r_a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
395 mov a r
1732
3b286be82ea5 Implemented ld a,r and ld a,i in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1731
diff changeset
396 and 0x80 a rhigh
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
397 cycles 1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
398
1732
3b286be82ea5 Implemented ld a,r and ld a,i in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1731
diff changeset
399 ed 01011111 ld_a_r
3b286be82ea5 Implemented ld a,r and ld a,i in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1731
diff changeset
400 cycles 1
3b286be82ea5 Implemented ld a,r and ld a,i in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1731
diff changeset
401 and 0x7F r a
3b286be82ea5 Implemented ld a,r and ld a,i in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1731
diff changeset
402 or rhigh a a
3b286be82ea5 Implemented ld a,r and ld a,i in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1731
diff changeset
403 update_flags SZYH0XN0
3b286be82ea5 Implemented ld a,r and ld a,i in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1731
diff changeset
404 mov iff2 pvflag
3b286be82ea5 Implemented ld a,r and ld a,i in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1731
diff changeset
405
3b286be82ea5 Implemented ld a,r and ld a,i in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1731
diff changeset
406 ed 01010111 ld_a_i
3b286be82ea5 Implemented ld a,r and ld a,i in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1731
diff changeset
407 cycles 1
3b286be82ea5 Implemented ld a,r and ld a,i in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1731
diff changeset
408 mov i a
3b286be82ea5 Implemented ld a,r and ld a,i in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1731
diff changeset
409 update_flags SZYH0XN0
3b286be82ea5 Implemented ld a,r and ld a,i in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1731
diff changeset
410 mov iff2 pvflag
3b286be82ea5 Implemented ld a,r and ld a,i in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1731
diff changeset
411
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
412 00000001 ld_bc_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
413 meta high b
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
414 meta low c
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
415 z80_fetch_immed_reg16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
416
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
417 00010001 ld_de_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
418 meta high d
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
419 meta low e
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
420 z80_fetch_immed_reg16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
421
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
422 00100001 ld_hl_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
423 meta high h
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
424 meta low l
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
425 z80_fetch_immed_reg16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
426
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
427 00110001 ld_sp_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
428 meta reg sp
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
429 z80_fetch_immed_to_reg16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
430
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
431 dd 00100001 ld_ix_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
432 meta reg ix
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
433 z80_fetch_immed_to_reg16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
434
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
435 fd 00100001 ld_iy_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
436 meta reg iy
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
437 z80_fetch_immed_to_reg16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
438
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
439 z80_fetch16_from_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
440 z80_fetch_immed16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
441 mov wz scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
442 ocall read_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
443 mov scratch1 low
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
444 add 1 wz wz
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
445 mov wz scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
446 ocall read_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
447 mov scratch1 high
1727
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
448 add 1 wz wz
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
449
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
450 00101010 ld_hl_from_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
451 meta low l
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
452 meta high h
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
453 z80_fetch16_from_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
454
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
455 ed 01001011 ld_bc_from_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
456 meta low c
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
457 meta high b
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
458 z80_fetch16_from_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
459
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
460 ed 01011011 ld_de_from_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
461 meta low e
1724
9a74c2d05672 Fixed a few ld instructions in the new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1723
diff changeset
462 meta high d
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
463 z80_fetch16_from_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
464
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
465 ed 01101011 ld_hl_from_immed_slow
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
466 meta low l
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
467 meta high h
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
468 z80_fetch16_from_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
469
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
470 z80_fetch_reg16_from_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
471 z80_fetch_immed16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
472 mov wz scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
473 ocall read_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
474 mov scratch1 reg
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
475 add 1 wz wz
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
476 mov wz scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
477 ocall read_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
478 lsl scratch1 8 scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
479 or scratch1 reg reg
1727
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
480 add 1 wz wz
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
481
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
482 ed 01111011 ld_sp_from_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
483 meta reg sp
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
484 z80_fetch_reg16_from_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
485
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
486 dd 00101010 ld_ix_from_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
487 meta reg ix
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
488 z80_fetch_reg16_from_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
489
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
490 fd 00101010 ld_iy_from_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
491 meta reg iy
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
492 z80_fetch_reg16_from_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
493
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
494 00100010 ld_hl_to_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
495 z80_fetch_immed16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
496 mov wz scratch2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
497 mov l scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
498 ocall write_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
499 add 1 wz wz
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
500 mov wz scratch2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
501 mov h scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
502 ocall write_8
1727
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
503 add 1 wz wz
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
504
1730
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
505 dd 00100010 ld_ix_to_immed
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
506 z80_fetch_immed16
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
507 mov wz scratch2
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
508 mov ix scratch1
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
509 ocall write_8
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
510 add 1 wz wz
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
511 mov wz scratch2
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
512 lsr ix 8 scratch1
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
513 ocall write_8
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
514 add 1 wz wz
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
515
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
516 fd 00100010 ld_iy_to_immed
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
517 z80_fetch_immed16
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
518 mov wz scratch2
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
519 mov iy scratch1
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
520 ocall write_8
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
521 add 1 wz wz
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
522 mov wz scratch2
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
523 lsr iy 8 scratch1
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
524 ocall write_8
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
525 add 1 wz wz
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
526
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
527 z80_regpair_to_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
528 z80_fetch_immed16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
529 mov wz scratch2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
530 mov low scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
531 ocall write_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
532 add 1 wz wz
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
533 mov high scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
534 mov wz scratch2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
535 ocall write_8
1727
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
536 add 1 wz wz
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
537
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
538 ed 01000011 ld_bc_to_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
539 meta low c
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
540 meta high b
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
541 z80_regpair_to_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
542
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
543 ed 01010011 ld_de_to_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
544 meta low e
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
545 meta high d
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
546 z80_regpair_to_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
547
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
548 ed 01100011 ld_hl_to_immed_slow
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
549 meta low l
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
550 meta high h
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
551 z80_regpair_to_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
552
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
553 ed 01110011 ld_sp_to_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
554 meta low sp
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
555 local sph 8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
556 lsr sp 8 sph
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
557 meta high sph
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
558 z80_regpair_to_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
559
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
560 11111001 ld_sp_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
561 cycles 2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
562 lsl h 8 sp
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
563 or l sp sp
1730
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
564
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
565 dd 11111001 ld_sp_ix
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
566 cycles 2
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
567 mov ix sp
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
568
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
569 fd 11111001 ld_sp_iy
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
570 cycles 2
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
571 mov iy sp
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
572
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
573 z80_push
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
574 cycles 1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
575 sub 1 sp sp
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
576 mov sp scratch2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
577 mov high scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
578 ocall write_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
579 sub 1 sp sp
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
580 mov sp scratch2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
581 mov low scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
582 ocall write_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
583
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
584 11000101 push_bc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
585 meta high b
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
586 meta low c
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
587 z80_push
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
588
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
589 11010101 push_de
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
590 meta high d
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
591 meta low e
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
592 z80_push
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
593
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
594 11100101 push_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
595 meta high h
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
596 meta low l
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
597 z80_push
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
598
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
599 11110101 push_af
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
600 meta high a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
601 meta low f
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
602 z80_push
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
603
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
604 dd 11100101 push_ix
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
605 local ixh 8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
606 lsr ix 8 ixh
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
607 meta high ixh
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
608 meta low ix
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
609 z80_push
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
610
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
611 fd 11100101 push_iy
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
612 local iyh 8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
613 lsr iy 8 iyh
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
614 meta high iyh
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
615 meta low iy
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
616 z80_push
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
617
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
618 z80_pop
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
619 mov sp scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
620 ocall read_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
621 add 1 sp sp
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
622 mov scratch1 low
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
623 mov sp scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
624 ocall read_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
625 add 1 sp sp
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
626 mov scratch1 high
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
627
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
628 11000001 pop_bc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
629 meta high b
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
630 meta low c
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
631 z80_pop
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
632
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
633 11010001 pop_de
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
634 meta high d
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
635 meta low e
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
636 z80_pop
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
637
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
638 11100001 pop_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
639 meta high h
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
640 meta low l
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
641 z80_pop
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
642
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
643 11110001 pop_af
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
644 meta high a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
645 meta low f
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
646 z80_pop
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
647
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
648 dd 11100001 pop_ix
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
649 local ixh 16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
650 meta high ixh
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
651 meta low ix
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
652 z80_pop
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
653 lsl ixh 8 ixh
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
654 or ixh ix ix
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
655
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
656 fd 11100001 pop_iy
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
657 local iyh 16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
658 meta high iyh
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
659 meta low iy
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
660 z80_pop
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
661 lsl iyh 8 iyh
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
662 or iyh iy iy
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
663
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
664 11101011 ex_de_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
665 xchg e l
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
666 xchg d h
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
667
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
668 00001000 ex_af_af
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
669 xchg a a'
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
670 xchg f f'
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
671
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
672 11011001 exx
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
673 xchg b b'
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
674 xchg c c'
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
675 xchg d d'
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
676 xchg e e'
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
677 xchg h h'
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
678 xchg l l'
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
679
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
680 11100011 ex_sp_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
681 mov sp scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
682 ocall read_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
683 xchg l scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
684 cycles 1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
685 mov sp scratch2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
686 ocall write_8
1731
366b65d91614 Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1730
diff changeset
687 add 1 sp scratch1
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
688 ocall read_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
689 xchg h scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
690 cycles 2
1731
366b65d91614 Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1730
diff changeset
691 add 1 sp scratch2
366b65d91614 Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1730
diff changeset
692 ocall write_8
366b65d91614 Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1730
diff changeset
693 lsl h 8 wz
366b65d91614 Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1730
diff changeset
694 or l wz wz
366b65d91614 Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1730
diff changeset
695
366b65d91614 Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1730
diff changeset
696 dd 11100011 ex_sp_ix
366b65d91614 Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1730
diff changeset
697 mov sp scratch1
366b65d91614 Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1730
diff changeset
698 ocall read_8
366b65d91614 Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1730
diff changeset
699 mov scratch1 wz
366b65d91614 Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1730
diff changeset
700 mov ix scratch1
366b65d91614 Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1730
diff changeset
701 cycles 1
366b65d91614 Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1730
diff changeset
702 mov sp scratch2
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
703 ocall write_8
1731
366b65d91614 Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1730
diff changeset
704 add 1 sp scratch1
366b65d91614 Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1730
diff changeset
705 ocall read_8
366b65d91614 Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1730
diff changeset
706 lsl scratch1 8 scratch1
366b65d91614 Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1730
diff changeset
707 or scratch1 wz wz
366b65d91614 Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1730
diff changeset
708 lsr ix 8 scratch1
366b65d91614 Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1730
diff changeset
709 cycles 2
366b65d91614 Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1730
diff changeset
710 add 1 sp scratch2
366b65d91614 Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1730
diff changeset
711 ocall write_8
366b65d91614 Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1730
diff changeset
712 mov wz ix
366b65d91614 Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1730
diff changeset
713
366b65d91614 Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1730
diff changeset
714 fd 11100011 ex_sp_iy
366b65d91614 Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1730
diff changeset
715 mov sp scratch1
366b65d91614 Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1730
diff changeset
716 ocall read_8
366b65d91614 Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1730
diff changeset
717 mov scratch1 wz
366b65d91614 Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1730
diff changeset
718 mov iy scratch1
366b65d91614 Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1730
diff changeset
719 cycles 1
366b65d91614 Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1730
diff changeset
720 mov sp scratch2
366b65d91614 Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1730
diff changeset
721 ocall write_8
366b65d91614 Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1730
diff changeset
722 add 1 sp scratch1
366b65d91614 Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1730
diff changeset
723 ocall read_8
366b65d91614 Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1730
diff changeset
724 lsl scratch1 8 scratch1
366b65d91614 Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1730
diff changeset
725 or scratch1 wz wz
366b65d91614 Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1730
diff changeset
726 lsr iy 8 scratch1
366b65d91614 Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1730
diff changeset
727 cycles 2
366b65d91614 Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1730
diff changeset
728 add 1 sp scratch2
366b65d91614 Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1730
diff changeset
729 ocall write_8
366b65d91614 Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1730
diff changeset
730 mov wz iy
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
731
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
732 10000RRR add_reg
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
733 add a main.R a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
734 update_flags SZYHVXN0C
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
735
1718
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
736 dd 10000100 add_ixh
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
737 lsr ix 8 scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
738 add a scratch1 a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
739 update_flags SZYHVXN0C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
740
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
741 dd 10000101 add_ixl
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
742 and ix 0xFF scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
743 add a scratch1 a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
744 update_flags SZYHVXN0C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
745
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
746 fd 10000100 add_iyh
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
747 lsr iy 8 scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
748 add a scratch1 a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
749 update_flags SZYHVXN0C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
750
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
751 fd 10000101 add_iyl
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
752 and iy 0xFF scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
753 add a scratch1 a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
754 update_flags SZYHVXN0C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
755
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
756 10000110 add_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
757 z80_fetch_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
758 add a scratch1 a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
759 update_flags SZYHVXN0C
1717
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
760
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
761 dd 10000110 add_ixd
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
762 z80_fetch_index ix
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
763 add a scratch1 a
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
764 update_flags SZYHVXN0C
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
765
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
766 fd 10000110 add_iyd
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
767 z80_fetch_index iy
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
768 add a scratch1 a
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
769 update_flags SZYHVXN0C
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
770
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
771 11000110 add_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
772 z80_fetch_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
773 add a scratch1 a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
774 update_flags SZYHVXN0C
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
775
1715
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
776 z80_add16_hl
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
777 arg src 16
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
778 lsl h 8 hlt
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
779 or l hlt hlt
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
780 add 1 hlt wz
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
781 add src hlt hlt
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
782 update_flags YHXN0C
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
783 mov hlt l
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
784 lsr hlt 8 h
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
785
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
786 00001001 add_hl_bc
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
787 local hlw 16
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
788 local bcw 16
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
789 meta hlt hlw
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
790 lsl b 8 bcw
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
791 or c bcw bcw
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
792 z80_add16_hl bcw
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
793
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
794 00011001 add_hl_de
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
795 local hlw 16
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
796 local dew 16
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
797 meta hlt hlw
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
798 lsl d 8 dew
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
799 or e dew dew
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
800 z80_add16_hl dew
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
801
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
802 00101001 add_hl_hl
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
803 local hlw 16
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
804 meta hlt hlw
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
805 z80_add16_hl hlw
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
806
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
807 00111001 add_hl_sp
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
808 local hlw 16
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
809 meta hlt hlw
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
810 z80_add16_hl sp
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
811
1718
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
812 dd 00001001 add_ix_bc
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
813 lsl b 8 scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
814 or c scratch1 scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
815 add scratch1 ix ix
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
816 update_flags YHXN0C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
817
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
818 dd 00011001 add_ix_de
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
819 lsl d 8 scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
820 or e scratch1 scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
821 add scratch1 ix ix
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
822 update_flags YHXN0C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
823
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
824 dd 00101001 add_ix_ix
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
825 add ix ix ix
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
826 update_flags YHXN0C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
827
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
828 dd 00111001 add_ix_sp
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
829 add sp ix ix
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
830 update_flags YHXN0C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
831
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
832 fd 00001001 add_iy_bc
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
833 lsl b 8 scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
834 or c scratch1 scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
835 add scratch1 iy iy
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
836 update_flags YHXN0C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
837
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
838 fd 00011001 add_iy_de
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
839 lsl d 8 scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
840 or e scratch1 scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
841 add scratch1 iy iy
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
842 update_flags YHXN0C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
843
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
844 fd 00101001 add_iy_iy
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
845 add iy iy iy
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
846 update_flags YHXN0C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
847
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
848 fd 00111001 add_iy_sp
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
849 add sp iy iy
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
850 update_flags YHXN0C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
851
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
852 10001RRR adc_reg
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
853 adc a main.R a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
854 update_flags SZYHVXN0C
1718
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
855
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
856 dd 10001100 adc_ixh
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
857 lsr ix 8 scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
858 adc a scratch1 a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
859 update_flags SZYHVXN0C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
860
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
861 dd 10001101 adc_ixl
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
862 and ix 0xFF scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
863 adc a scratch1 a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
864 update_flags SZYHVXN0C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
865
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
866 fd 10001100 adc_iyh
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
867 lsr iy 8 scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
868 adc a scratch1 a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
869 update_flags SZYHVXN0C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
870
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
871 fd 10001101 adc_iyl
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
872 and iy 0xFF scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
873 adc a scratch1 a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
874 update_flags SZYHVXN0C
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
875
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
876 10001110 adc_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
877 z80_fetch_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
878 adc a scratch1 a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
879 update_flags SZYHVXN0C
1718
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
880
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
881 dd 10001110 adc_ixd
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
882 z80_fetch_index ix
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
883 adc a scratch1 a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
884 update_flags SZYHVXN0C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
885
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
886 fd 10001110 adc_iyd
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
887 z80_fetch_index iy
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
888 adc a scratch1 a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
889 update_flags SZYHVXN0C
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
890
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
891 11001110 adc_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
892 z80_fetch_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
893 adc a scratch1 a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
894 update_flags SZYHVXN0C
1715
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
895
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
896 z80_adc16_hl
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
897 arg src 16
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
898 lsl h 8 hlt
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
899 or l hlt hlt
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
900 add 1 hlt wz
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
901 adc src hlt hlt
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
902 update_flags SZYHVXN0C
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
903 mov hlt l
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
904 lsr hlt 8 h
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
905
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
906 ed 01001010 adc_hl_bc
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
907 local hlw 16
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
908 local bcw 16
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
909 meta hlt hlw
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
910 lsl b 8 bcw
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
911 or c bcw bcw
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
912 z80_adc16_hl bcw
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
913
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
914 ed 01011010 adc_hl_de
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
915 local hlw 16
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
916 local dew 16
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
917 meta hlt hlw
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
918 lsl d 8 dew
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
919 or e dew dew
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
920 z80_adc16_hl dew
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
921
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
922 ed 01101010 adc_hl_hl
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
923 local hlw 16
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
924 meta hlt hlw
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
925 z80_adc16_hl hlw
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
926
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
927
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
928 ed 01111010 adc_hl_sp
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
929 local hlw 16
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
930 meta hlt hlw
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
931 z80_adc16_hl sp
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
932
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
933 10010RRR sub_reg
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
934 sub main.R a a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
935 update_flags SZYHVXN1C
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
936
1718
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
937 dd 10010100 sub_ixh
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
938 lsr ix 8 scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
939 sub scratch1 a a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
940 update_flags SZYHVXN1C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
941
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
942 dd 10010101 sub_ixl
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
943 and ix 0xFF scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
944 sub scratch1 a a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
945 update_flags SZYHVXN1C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
946
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
947 fd 10010100 sub_iyh
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
948 lsr iy 8 scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
949 sub scratch1 a a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
950 update_flags SZYHVXN1C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
951
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
952 fd 10010101 sub_iyl
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
953 and iy 0xFF scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
954 sub scratch1 a a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
955 update_flags SZYHVXN1C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
956
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
957 10010110 sub_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
958 z80_fetch_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
959 sub scratch1 a a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
960 update_flags SZYHVXN1C
1718
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
961
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
962 dd 10010110 sub_ixd
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
963 z80_fetch_index ix
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
964 sub scratch1 a a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
965 update_flags SZYHVXN1C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
966
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
967 fd 10010110 sub_iyd
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
968 z80_fetch_index iy
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
969 sub scratch1 a a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
970 update_flags SZYHVXN1C
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
971
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
972 11010110 sub_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
973 z80_fetch_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
974 sub scratch1 a a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
975 update_flags SZYHVXN1C
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
976
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
977 10011RRR sbc_reg
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
978 sbc main.R a a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
979 update_flags SZYHVXN1C
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
980
1718
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
981 dd 10011100 sbc_ixh
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
982 lsr ix 8 scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
983 sbc scratch1 a a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
984 update_flags SZYHVXN1C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
985
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
986 dd 10011101 sbc_ixl
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
987 and ix 0xFF scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
988 sbc scratch1 a a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
989 update_flags SZYHVXN1C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
990
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
991 fd 10011100 sbc_iyh
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
992 lsr iy 8 scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
993 sbc scratch1 a a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
994 update_flags SZYHVXN1C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
995
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
996 fd 10011101 sbc_iyl
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
997 and iy 0xFF scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
998 sbc scratch1 a a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
999 update_flags SZYHVXN1C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1000
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1001
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1002 10011110 sbc_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1003 z80_fetch_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1004 sbc scratch1 a a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1005 update_flags SZYHVXN1C
1718
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1006
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1007 dd 10011110 sbc_ixd
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1008 z80_fetch_index ix
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1009 sbc scratch1 a a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1010 update_flags SZYHVXN1C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1011
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1012 fd 10011110 sbc_iyd
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1013 z80_fetch_index iy
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1014 sbc scratch1 a a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1015 update_flags SZYHVXN1C
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1016
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1017 11011110 sbc_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1018 z80_fetch_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1019 sbc scratch1 a a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1020 update_flags SZYHVXN1C
1717
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1021
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1022 z80_sbc16_hl
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1023 arg src 16
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1024 lsl h 8 hlt
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1025 or l hlt hlt
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1026 add 1 hlt wz
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1027 sbc src hlt hlt
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1028 update_flags SZYHVXN1C
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1029 mov hlt l
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1030 lsr hlt 8 h
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1031
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1032 ed 01000010 sbc_hl_bc
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1033 local hlw 16
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1034 local bcw 16
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1035 meta hlt hlw
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1036 lsl b 8 bcw
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1037 or c bcw bcw
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1038 z80_sbc16_hl bcw
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1039
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1040 ed 01010010 sbc_hl_de
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1041 local hlw 16
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1042 local dew 16
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1043 meta hlt hlw
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1044 lsl d 8 dew
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1045 or e dew dew
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1046 z80_sbc16_hl dew
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1047
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1048 ed 01100010 sbc_hl_hl
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1049 local hlw 16
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1050 meta hlt hlw
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1051 z80_sbc16_hl hlw
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1052
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1053
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1054 ed 01110010 sbc_hl_sp
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1055 local hlw 16
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1056 meta hlt hlw
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1057 z80_sbc16_hl sp
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1058
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1059 10100RRR and_reg
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1060 and a main.R a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1061 update_flags SZYH1PXN0C0
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1062
1720
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1063 dd 10100100 and_ixh
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1064 lsr ix 8 scratch1
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1065 and scratch1 a a
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1066 update_flags SZYH1PXN0C0
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1067
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1068 dd 10100101 and_ixl
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1069 and ix a a
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1070 update_flags SZYH1PXN0C0
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1071
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1072 fd 10100100 and_iyh
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1073 lsr iy 8 scratch1
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1074 and scratch1 a a
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1075 update_flags SZYH1PXN0C0
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1076
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1077 fd 10100101 and_iyl
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1078 and iy a a
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1079 update_flags SZYH1PXN0C0
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1080
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1081 10100110 and_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1082 z80_fetch_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1083 and a scratch1 a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1084 update_flags SZYH1PXN0C0
1720
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1085
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1086 dd 10100110 and_ixd
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1087 z80_fetch_index ix
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1088 and a scratch1 a
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1089 update_flags SZYH1PXN0C0
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1090
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1091 fd 10100110 and_iyd
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1092 z80_fetch_index iy
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1093 and a scratch1 a
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1094 update_flags SZYH1PXN0C0
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1095
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1096 11100110 and_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1097 z80_fetch_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1098 and a scratch1 a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1099 update_flags SZYH1PXN0C0
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1100
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1101 10110RRR or_reg
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1102 or a main.R a
1714
e170a0f75c4f fix half-carry for or and xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1712
diff changeset
1103 update_flags SZYH0PXN0C0
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1104
1720
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1105 dd 10110100 or_ixh
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1106 lsr ix 8 scratch1
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1107 or scratch1 a a
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1108 update_flags SZYH0PXN0C0
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1109
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1110 dd 10110101 or_ixl
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1111 or ix a a
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1112 update_flags SZYH0PXN0C0
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1113
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1114 fd 10110100 or_iyh
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1115 lsr iy 8 scratch1
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1116 or scratch1 a a
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1117 update_flags SZYH0PXN0C0
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1118
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1119 fd 10110101 or_iyl
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1120 or iy a a
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1121 update_flags SZYH0PXN0C0
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1122
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1123 10110110 or_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1124 z80_fetch_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1125 or a scratch1 a
1714
e170a0f75c4f fix half-carry for or and xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1712
diff changeset
1126 update_flags SZYH0PXN0C0
1720
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1127
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1128 dd 10110110 or_ixd
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1129 z80_fetch_index ix
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1130 or a scratch1 a
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1131 update_flags SZYH0PXN0C0
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1132
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1133 fd 10110110 or_iyd
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1134 z80_fetch_index iy
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1135 or a scratch1 a
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1136 update_flags SZYH0PXN0C0
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1137
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1138 11110110 or_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1139 z80_fetch_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1140 or a scratch1 a
1714
e170a0f75c4f fix half-carry for or and xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1712
diff changeset
1141 update_flags SZYH0PXN0C0
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1142
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1143 10101RRR xor_reg
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1144 xor a main.R a
1714
e170a0f75c4f fix half-carry for or and xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1712
diff changeset
1145 update_flags SZYH0PXN0C0
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1146
1720
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1147 dd 10101100 xor_ixh
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1148 lsr ix 8 scratch1
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1149 xor scratch1 a a
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1150 update_flags SZYH0PXN0C0
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1151
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1152 dd 10101101 xor_ixl
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1153 xor ix a a
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1154 update_flags SZYH0PXN0C0
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1155
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1156 fd 10101100 xor_iyh
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1157 lsr iy 8 scratch1
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1158 xor scratch1 a a
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1159 update_flags SZYH0PXN0C0
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1160
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1161 fd 10101101 xor_iyl
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1162 xor iy a a
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1163 update_flags SZYH0PXN0C0
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1164
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1165 10101110 xor_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1166 z80_fetch_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1167 xor a scratch1 a
1714
e170a0f75c4f fix half-carry for or and xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1712
diff changeset
1168 update_flags SZYH0PXN0C0
1720
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1169
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1170 dd 10101110 xor_ixd
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1171 z80_fetch_index ix
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1172 xor a scratch1 a
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1173 update_flags SZYH0PXN0C0
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1174
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1175 fd 10101110 xor_iyd
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1176 z80_fetch_index iy
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1177 xor a scratch1 a
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1178 update_flags SZYH0PXN0C0
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1179
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1180 11101110 xor_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1181 z80_fetch_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1182 xor a scratch1 a
1714
e170a0f75c4f fix half-carry for or and xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1712
diff changeset
1183 update_flags SZYH0PXN0C0
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1184
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1185 10111RRR cp_reg
1719
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1186 mov main.R last_flag_result
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1187 cmp main.R a
1719
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1188 update_flags SZHVN1C
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1189
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1190 dd 10111100 cp_ixh
1725
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1191 local tmp 8
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1192 lsr ix 8 tmp
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1193 mov tmp last_flag_result
1719
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1194 cmp last_flag_result a
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1195 update_flags SZHVN1C
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1196
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1197 dd 10111101 cp_ixl
1725
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1198 local tmp 8
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1199 mov ix tmp
1719
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1200 mov ix last_flag_result
1725
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1201 cmp tmp a
1719
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1202 update_flags SZHVN1C
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1203
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1204 fd 10111100 cp_iyh
1725
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1205 local tmp 8
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1206 lsr iy 8 tmp
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1207 mov tmp last_flag_result
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1208 cmp tmp a
1719
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1209 update_flags SZHVN1C
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1210
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1211 fd 10111101 cp_iyl
1725
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1212 local tmp 8
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1213 mov iy tmp
1719
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1214 mov iy last_flag_result
1725
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1215 cmp tmp a
1719
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1216 update_flags SZHVN1C
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1217
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1218 10111110 cp_hl
1725
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1219 local tmp 8
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1220 z80_fetch_hl
1725
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1221 mov scratch1 tmp
1719
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1222 mov scratch1 last_flag_result
1725
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1223 cmp tmp a
1719
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1224 update_flags SZHVN1C
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1225
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1226 dd 10111110 cp_ixd
1725
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1227 local tmp 8
1719
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1228 z80_fetch_index ix
1725
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1229 mov scratch1 tmp
1719
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1230 mov scratch1 last_flag_result
1725
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1231 cmp tmp a
1719
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1232 update_flags SZHVN1C
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1233
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1234 fd 10111110 cp_iyd
1725
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1235 local tmp 8
1719
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1236 z80_fetch_index iy
1725
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1237 mov scratch1 tmp
1719
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1238 mov scratch1 last_flag_result
1725
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1239 cmp tmp a
1719
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1240 update_flags SZHVN1C
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1241
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1242 11111110 cp_immed
1725
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1243 local tmp 8
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1244 z80_fetch_immed
1725
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1245 mov scratch1 tmp
1719
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1246 mov scratch1 last_flag_result
1725
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1247 cmp tmp a
1719
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1248 update_flags SZHVN1C
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1249
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1250 00RRR100 inc_reg
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1251 add 1 main.R main.R
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1252 update_flags SZYHVXN0
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1253
1718
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1254 dd 00100100 inc_ixh
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1255 add 0x100 ix ix
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1256 update_flags SZYHVXN0
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1257
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1258 dd 00101100 inc_ixl
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1259 local tmp 8
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1260 mov ix tmp
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1261 add 1 tmp tmp
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1262 update_flags SZYHVXN0
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1263 and 0xFF00 ix ix
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1264 or tmp ix ix
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1265
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1266 fd 00100100 inc_iyh
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1267 add 0x100 iy iy
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1268 update_flags SZYHVXN0
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1269
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1270 fd 00101100 inc_iyl
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1271 local tmp 8
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1272 mov iy tmp
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1273 add 1 tmp tmp
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1274 update_flags SZYHVXN0
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1275 and 0xFF00 iy iy
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1276 or tmp iy iy
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1277
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1278 00110100 inc_hl
1717
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1279 local tmp 8
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1280 z80_fetch_hl
1717
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1281 #TODO: Either make DSL compiler smart enough to optimize these unnecessary moves out
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1282 #or add some syntax to force a certain size on an operation so they are unnecessary
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1283 mov scratch1 tmp
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1284 add 1 tmp tmp
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1285 update_flags SZYHVXN0
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1286 mov tmp scratch1
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1287 z80_store_hl
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1288
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1289 dd 00110100 inc_ixd
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1290 local tmp 8
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1291 z80_fetch_index ix
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1292 #TODO: Either make DSL compiler smart enough to optimize these unnecessary moves out
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1293 #or add some syntax to force a certain size on an operation so they are unnecessary
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1294 mov scratch1 tmp
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1295 add 1 tmp tmp
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1296 update_flags SZYHVXN0
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1297 mov tmp scratch1
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1298 cycles 1
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1299 z80_store_index
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1300
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1301 fd 00110100 inc_iyd
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1302 local tmp 8
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1303 z80_fetch_index iy
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1304 #TODO: Either make DSL compiler smart enough to optimize these unnecessary moves out
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1305 #or add some syntax to force a certain size on an operation so they are unnecessary
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1306 mov scratch1 tmp
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1307 add 1 tmp tmp
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1308 update_flags SZYHVXN0
1717
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1309 mov tmp scratch1
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1310 cycles 1
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1311 z80_store_index
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1312
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1313 z80_inc_pair
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1314 arg high 8
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1315 arg low 8
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1316 local word 16
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1317 lsl high 8 word
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1318 or low word word
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1319 add 1 word word
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1320 mov word low
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1321 lsr word 8 high
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1322
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1323 00000011 inc_bc
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1324 z80_inc_pair b c
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1325
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1326 00010011 inc_de
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1327 z80_inc_pair d e
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1328
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1329 00100011 inc16_hl
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1330 z80_inc_pair h l
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1331
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1332 00110011 inc_sp
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1333 add 1 sp sp
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1334
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1335 dd 00100011 inc_ix
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1336 add 1 ix ix
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1337
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1338 fd 00100011 inc_iy
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1339 add 1 iy iy
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1340
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1341 00RRR101 dec_reg
1717
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1342 sub 1 main.R main.R
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1343 update_flags SZYHVXN1
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1344
1718
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1345 dd 00100101 dec_ixh
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1346 sub 0x100 ix ix
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1347 update_flags SZYHVXN1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1348
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1349 dd 00101101 dec_ixl
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1350 local tmp 8
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1351 mov ix tmp
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1352 sub 1 tmp tmp
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1353 update_flags SZYHVXN1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1354 and 0xFF00 ix ix
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1355 or tmp ix ix
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1356
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1357 fd 00100101 dec_iyh
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1358 sub 0x100 iy iy
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1359 update_flags SZYHVXN1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1360
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1361 fd 00101101 dec_iyl
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1362 local tmp 8
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1363 mov iy tmp
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1364 sub 1 tmp tmp
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1365 update_flags SZYHVXN1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1366 and 0xFF00 iy iy
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1367 or tmp iy iy
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1368
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1369 00110101 dec_hl
1739
435877da5837 Fixed flag calculation in dec (hl) in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1738
diff changeset
1370 local tmp 8
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1371 z80_fetch_hl
1739
435877da5837 Fixed flag calculation in dec (hl) in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1738
diff changeset
1372 #TODO: Either make DSL compiler smart enough to optimize these unnecessary moves out
435877da5837 Fixed flag calculation in dec (hl) in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1738
diff changeset
1373 #or add some syntax to force a certain size on an operation so they are unnecessary
435877da5837 Fixed flag calculation in dec (hl) in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1738
diff changeset
1374 mov scratch1 tmp
435877da5837 Fixed flag calculation in dec (hl) in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1738
diff changeset
1375 sub 1 tmp tmp
1717
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1376 update_flags SZYHVXN1
1739
435877da5837 Fixed flag calculation in dec (hl) in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1738
diff changeset
1377 mov tmp scratch1
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1378 z80_store_hl
1717
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1379
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1380 dd 00110101 dec_ixd
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1381 local tmp 8
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1382 z80_fetch_index ix
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1383 #TODO: Either make DSL compiler smart enough to optimize these unnecessary moves out
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1384 #or add some syntax to force a certain size on an operation so they are unnecessary
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1385 mov scratch1 tmp
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1386 sub 1 tmp tmp
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1387 update_flags SZYHVXN1
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1388 mov tmp scratch1
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1389 cycles 1
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1390 z80_store_index
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1391
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1392 fd 00110101 dec_iyd
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1393 local tmp 8
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1394 z80_fetch_index iy
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1395 #TODO: Either make DSL compiler smart enough to optimize these unnecessary moves out
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1396 #or add some syntax to force a certain size on an operation so they are unnecessary
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1397 mov scratch1 tmp
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1398 sub 1 tmp tmp
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1399 update_flags SZYHVXN1
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1400 mov tmp scratch1
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1401 cycles 1
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1402 z80_store_index
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1403
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1404 z80_dec_pair
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1405 arg high 8
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1406 arg low 8
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1407 local word 16
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1408 lsl high 8 word
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1409 or low word word
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1410 sub 1 word word
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1411 mov word low
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1412 lsr word 8 high
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1413
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1414 00001011 dec_bc
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1415 z80_dec_pair b c
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1416
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1417 00011011 dec_de
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1418 z80_dec_pair d e
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1419
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1420 00101011 dec16_hl
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1421 z80_dec_pair h l
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1422
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1423 00111011 dec_sp
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1424 sub 1 sp sp
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1425
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1426 dd 00101011 dec_ix
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1427 sub 1 ix ix
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1428
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1429 fd 00101011 dec_iy
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1430 sub 1 iy iy
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1431
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1432 00101111 cpl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1433 not a a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1434 update_flags YH1XN1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1435
1725
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1436 ed 01DDD100 neg
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1437 neg a a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1438 update_flags SZYHVXN1C
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1439
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1440 00111111 ccf
1725
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1441 local tmp 8
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1442 and 0x80 chflags chflags
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1443 lsr chflags 4 tmp
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1444 or tmp chflags chflags
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1445 xor 0x80 chflags chflags
1725
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1446 update_flags N0
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1447
1725
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1448 00110111 scf
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1449 update_flags H0N0C1
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1450
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1451 00000000 nop
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1452
1725
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1453 01110110 halt
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1454 sub 1 pc pc
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1455
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1456 11110011 di
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1457 mov 0 iff1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1458 mov 0 iff2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1459 #TODO: update interrupt/sync cycle
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1460
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1461 11111011 ei
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1462 mov 1 iff1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1463 mov 1 iff2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1464 #TODO: update interrupt/sync cycle
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1465
1725
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1466 ed 01D00110 im0
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1467 mov 0 imode
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1468
1725
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1469 ed 01D10110 im1
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1470 mov 1 imode
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1471
1725
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1472 ed 01D11110 im2
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1473 mov 2 imode
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1474
1725
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1475 ed 01D01110 im3
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1476 mov 3 imode
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1477
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1478 11000011 jp
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1479 z80_fetch_immed16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1480 mov wz pc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1481
1726
4f064b575e57 Implemented jp (hl), jp (ix) and jp (iy) in the new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1725
diff changeset
1482 11101001 jp_hl
4f064b575e57 Implemented jp (hl), jp (ix) and jp (iy) in the new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1725
diff changeset
1483 lsl h 8 pc
4f064b575e57 Implemented jp (hl), jp (ix) and jp (iy) in the new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1725
diff changeset
1484 or l pc pc
4f064b575e57 Implemented jp (hl), jp (ix) and jp (iy) in the new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1725
diff changeset
1485
4f064b575e57 Implemented jp (hl), jp (ix) and jp (iy) in the new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1725
diff changeset
1486 dd 11101001 jp_ix
4f064b575e57 Implemented jp (hl), jp (ix) and jp (iy) in the new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1725
diff changeset
1487 mov ix pc
4f064b575e57 Implemented jp (hl), jp (ix) and jp (iy) in the new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1725
diff changeset
1488
4f064b575e57 Implemented jp (hl), jp (ix) and jp (iy) in the new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1725
diff changeset
1489 fd 11101001 jp_iy
4f064b575e57 Implemented jp (hl), jp (ix) and jp (iy) in the new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1725
diff changeset
1490 mov iy pc
4f064b575e57 Implemented jp (hl), jp (ix) and jp (iy) in the new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1725
diff changeset
1491
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1492 11CCC010 jp_cc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1493 z80_check_cond C
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1494 z80_fetch_immed16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1495 if istrue
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1496
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1497 mov wz pc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1498
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1499 end
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1500
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1501 00011000 jr
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1502 z80_fetch_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1503 #TODO: determine if this updates wz
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1504 sext 16 scratch1 scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1505 add scratch1 pc pc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1506 cycles 5
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1507
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1508 001CC000 jr_cc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1509 z80_check_cond C
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1510 z80_fetch_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1511
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1512 if istrue
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1513
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1514 sext 16 scratch1 scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1515 add scratch1 pc pc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1516 cycles 5
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1517
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1518 end
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1519
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1520 00010000 djnz
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1521 cycles 1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1522 z80_fetch_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1523 sub 1 b b
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1524
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1525 if b
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1526
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1527 sext 16 scratch1 scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1528 add scratch1 pc pc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1529 cycles 5
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1530
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1531 end
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1532
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1533
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1534 11001101 call_uncond
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1535 z80_fetch_immed16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1536 local pch 8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1537 lsr pc 8 pch
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1538 meta high pch
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1539 meta low pc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1540 z80_push
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1541 mov wz pc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1542
1736
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
1543 11CCC100 call_cond
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
1544 local pch 8
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
1545 z80_fetch_immed16
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
1546 z80_check_cond C
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
1547
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
1548 if istrue
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
1549
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
1550 lsr pc 8 pch
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
1551 meta high pch
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
1552 meta low pc
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
1553 z80_push
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
1554 mov wz pc
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
1555
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
1556 end
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
1557
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1558 11TTT111 rst
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1559 local pch 8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1560 lsr pc 8 pch
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1561 meta high pch
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1562 meta low pc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1563 z80_push
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1564 lsl T 3 scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1565 mov scratch1 pc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1566
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1567 11001001 ret
1736
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
1568 local pch 16
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
1569 cycles 1
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
1570 meta high pch
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
1571 meta low pc
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1572 z80_pop
1736
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
1573 lsl pch 8 pch
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
1574 or pch pc pc
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
1575
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
1576 11CCC000 ret_cond
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
1577 local pch 16
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
1578 cycles 1
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
1579 z80_check_cond C
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
1580 if istrue
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
1581
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
1582 meta high pch
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
1583 meta low pc
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
1584 z80_pop
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
1585 lsl pch 8 pch
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
1586 or pch pc pc
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
1587
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
1588 end
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1589
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1590 11011011 in_abs
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1591 z80_fetch_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1592 ocall io_read8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1593 mov scratch1 a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1594
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1595 ed 01RRR000 in_bc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1596 lsl b 8 scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1597 or c scratch1 scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1598 ocall io_read8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1599 mov scratch1 main.R
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1600
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1601 11010011 out_abs
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1602 z80_fetch_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1603 mov scratch1 scratch2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1604 mov a scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1605 ocall io_write8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1606
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1607 ed 01RRR001 out_bc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1608 lsl b 8 scratch2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1609 or c scratch2 scratch2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1610 mov main.R scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1611 ocall io_write8
1721
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1612
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1613 00000111 rlca
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1614 rol a 1 a
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1615 update_flags YH0XN0C
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1616
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1617 00010111 rla
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1618 rlc a 1 a
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1619 update_flags YH0XN0C
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1620
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1621 00001111 rrca
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1622 ror a 1 a
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1623 update_flags YH0XN0C
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1624
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1625 00011111 rra
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1626 rrc a 1 a
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1627 update_flags YH0XN0C
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1628
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1629 cb 00000RRR rlc
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1630 rol main.R 1 main.R
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1631 update_flags SZYH0PXN0C
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1632
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1633 cb 00000110 rlc_hl
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1634 local tmp 8
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1635 z80_fetch_hl
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1636 mov scratch1 tmp
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1637 rol tmp 1 tmp
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1638 update_flags SZYH0PXN0C
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1639 mov tmp scratch1
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1640 z80_store_hl
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1641
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1642 z80_rlc_index
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1643 arg tmp 8
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1644 mov wz scratch1
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1645 ocall read_8
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1646 cycles 1
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1647 mov scratch1 tmp
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1648 rol tmp 1 tmp
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1649 update_flags SZYH0PXN0C
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1650 mov tmp scratch1
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1651 z80_store_index
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1652
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1653 ddcb 00000110 rlc_ixd
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1654 local tmp 8
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1655 z80_rlc_index tmp
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1656
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1657 ddcb 00000RRR rlc_ixd_reg
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1658 z80_rlc_index main.R
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1659
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1660 fdcb 00000110 rlc_iyd
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1661 local tmp 8
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1662 z80_rlc_index tmp
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1663
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1664 fdcb 00000RRR rlc_iyd_reg
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1665 z80_rlc_index main.R
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1666
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1667 cb 00010RRR rl
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1668 rlc main.R 1 main.R
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1669 update_flags SZYH0PXN0C
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1670
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1671 cb 00010110 rl_hl
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1672 local tmp 8
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1673 z80_fetch_hl
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1674 mov scratch1 tmp
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1675 rlc tmp 1 tmp
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1676 update_flags SZYH0PXN0C
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1677 mov tmp scratch1
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1678 z80_store_hl
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1679
1722
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1680 z80_rl_index
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1681 arg tmp 8
1721
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1682 mov wz scratch1
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1683 ocall read_8
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1684 cycles 1
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1685 mov scratch1 tmp
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1686 rlc tmp 1 tmp
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1687 update_flags SZYH0PXN0C
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1688 mov tmp scratch1
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1689 z80_store_index
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1690
1722
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1691 ddcb 00010110 rl_ixd
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1692 local tmp 8
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1693 z80_rl_index tmp
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1694
1721
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1695 fdcb 00010110 rl_iyd
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1696 local tmp 8
1722
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1697 z80_rl_index tmp
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1698
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1699
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1700 ddcb 00010RRR rl_ixd_reg
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1701 z80_rl_index main.R
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1702
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1703 fdcb 00010RRR rl_iyd_reg
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1704 z80_rl_index main.R
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1705
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1706 cb 00001RRR rrc
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1707 ror main.R 1 main.R
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1708 update_flags SZYH0PXN0C
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1709
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1710 cb 00001110 rrc_hl
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1711 local tmp 8
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1712 z80_fetch_hl
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1713 mov scratch1 tmp
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1714 ror tmp 1 tmp
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1715 update_flags SZYH0PXN0C
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1716 mov tmp scratch1
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1717 z80_store_hl
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1718
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1719 z80_rrc_index
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1720 arg tmp 8
1721
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1721 mov wz scratch1
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1722 ocall read_8
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1723 cycles 1
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1724 mov scratch1 tmp
1722
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1725 ror tmp 1 tmp
1721
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1726 update_flags SZYH0PXN0C
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1727 mov tmp scratch1
1722
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1728 z80_store_index
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1729
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1730 ddcb 00001110 rrc_ixd
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1731 local tmp 8
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1732 z80_rrc_index tmp
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1733
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1734 ddcb 00001RRR rrc_ixd_reg
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1735 z80_rrc_index main.R
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1736
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1737 fdcb 00001110 rrc_iyd
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1738 local tmp 8
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1739 z80_rrc_index tmp
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1740
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1741 fdcb 00001RRR rrc_iyd_reg
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1742 z80_rrc_index main.R
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1743
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1744 cb 00011RRR rr
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1745 rrc main.R 1 main.R
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1746 update_flags SZYH0PXN0C
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1747
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1748 cb 00011110 rr_hl
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1749 local tmp 8
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1750 z80_fetch_hl
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1751 mov scratch1 tmp
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1752 rrc tmp 1 tmp
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1753 update_flags SZYH0PXN0C
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1754 mov tmp scratch1
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1755 z80_store_hl
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1756
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1757 z80_rr_index
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1758 arg tmp 8
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1759 mov wz scratch1
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1760 ocall read_8
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1761 cycles 1
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1762 mov scratch1 tmp
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1763 rrc tmp 1 tmp
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1764 update_flags SZYH0PXN0C
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1765 mov tmp scratch1
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1766 z80_store_index
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1767
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1768 ddcb 00011110 rr_ixd
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1769 local tmp 8
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1770 z80_rr_index tmp
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1771
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1772 ddcb 00011RRR rr_ixd_reg
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1773 z80_rr_index main.R
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1774
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1775 fdcb 00011110 rr_iyd
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1776 local tmp 8
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1777 z80_rr_index tmp
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1778
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1779 fdcb 00011RRR rr_iyd_reg
1723
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1780 z80_rr_index main.R
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1781
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1782 cb 00100RRR sla
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1783 lsl main.R 1 main.R
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1784 update_flags SZYH0PXN0C
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1785
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1786 cb 00100110 sla_hl
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1787 local tmp 8
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1788 z80_fetch_hl
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1789 mov scratch1 tmp
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1790 lsl tmp 1 tmp
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1791 update_flags SZYH0PXN0C
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1792 mov tmp scratch1
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1793 z80_store_hl
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1794
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1795 z80_sla_index
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1796 arg tmp 8
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1797 mov wz scratch1
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1798 ocall read_8
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1799 cycles 1
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1800 mov scratch1 tmp
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1801 lsl tmp 1 tmp
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1802 update_flags SZYH0PXN0C
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1803 mov tmp scratch1
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1804 z80_store_index
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1805
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1806 ddcb 00100110 sla_ixd
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1807 local tmp 8
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1808 z80_sla_index tmp
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1809
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1810 ddcb 00100RRR sla_ixd_reg
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1811 z80_sla_index main.R
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1812
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1813 fdcb 00100110 sla_iyd
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1814 local tmp 8
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1815 z80_sla_index tmp
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1816
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1817 fdcb 00100RRR sla_iyd_reg
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1818 z80_sla_index main.R
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1819
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1820 cb 00101RRR sra
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1821 asr main.R 1 main.R
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1822 update_flags SZYH0PXN0C
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1823
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1824 cb 00101110 sra_hl
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1825 local tmp 8
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1826 z80_fetch_hl
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1827 mov scratch1 tmp
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1828 asr tmp 1 tmp
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1829 update_flags SZYH0PXN0C
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1830 mov tmp scratch1
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1831 z80_store_hl
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1832
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1833 z80_sra_index
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1834 arg tmp 8
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1835 mov wz scratch1
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1836 ocall read_8
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1837 cycles 1
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1838 mov scratch1 tmp
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1839 asr tmp 1 tmp
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1840 update_flags SZYH0PXN0C
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1841 mov tmp scratch1
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1842 z80_store_index
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1843
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1844 ddcb 00101110 sra_ixd
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1845 local tmp 8
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1846 z80_sra_index tmp
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1847
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1848 ddcb 00101RRR sra_ixd_reg
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1849 z80_sra_index main.R
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1850
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1851 fdcb 00101110 sra_iyd
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1852 local tmp 8
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1853 z80_sra_index tmp
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1854
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1855 fdcb 00101RRR sra_iyd_reg
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1856 z80_sra_index main.R
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1857
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1858 cb 00110RRR sll
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1859 lsl main.R 1 main.R
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1860 update_flags SZ0YH0XN0C
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1861 or 1 main.R main.R
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1862 update_flags P
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1863
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1864 cb 00110110 sll_hl
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1865 local tmp 8
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1866 z80_fetch_hl
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1867 mov scratch1 tmp
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1868 lsl tmp 1 tmp
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1869 update_flags SZ0YH0XN0C
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1870 or 1 tmp tmp
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1871 update_flags P
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1872 mov tmp scratch1
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1873 z80_store_hl
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1874
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1875 z80_sll_index
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1876 arg tmp 8
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1877 mov wz scratch1
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1878 ocall read_8
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1879 cycles 1
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1880 mov scratch1 tmp
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1881 lsl tmp 1 tmp
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1882 update_flags SZ0YH0XN0C
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1883 or 1 tmp tmp
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1884 update_flags P
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1885 mov tmp scratch1
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1886 z80_store_index
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1887
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1888 ddcb 00110110 sll_ixd
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1889 local tmp 8
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1890 z80_sll_index tmp
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1891
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1892 ddcb 00110RRR sll_ixd_reg
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1893 z80_sll_index main.R
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1894
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1895 fdcb 00110110 sll_iyd
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1896 local tmp 8
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1897 z80_sll_index tmp
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1898
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1899 fdcb 00110RRR sll_iyd_reg
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1900 z80_sll_index main.R
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1901
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1902 cb 00111RRR srl
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1903 lsr main.R 1 main.R
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1904 update_flags SZYH0PXN0C
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1905
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1906 cb 00111110 srl_hl
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1907 local tmp 8
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1908 z80_fetch_hl
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1909 mov scratch1 tmp
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1910 lsr tmp 1 tmp
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1911 update_flags SZYH0PXN0C
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1912 mov tmp scratch1
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1913 z80_store_hl
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1914
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1915 z80_srl_index
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1916 arg tmp 8
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1917 mov wz scratch1
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1918 ocall read_8
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1919 cycles 1
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1920 mov scratch1 tmp
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1921 lsr tmp 1 tmp
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1922 update_flags SZYH0PXN0C
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1923 mov tmp scratch1
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1924 z80_store_index
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1925
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1926 ddcb 00111110 srl_ixd
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1927 local tmp 8
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1928 z80_srl_index tmp
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1929
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1930 ddcb 00111RRR srl_ixd_reg
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1931 z80_srl_index main.R
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1932
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1933 fdcb 00111110 srl_iyd
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1934 local tmp 8
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1935 z80_srl_index tmp
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1936
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
1937 fdcb 00111RRR srl_iyd_reg
1727
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
1938 z80_srl_index main.R
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
1939
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
1940 cb 01BBBRRR bit_reg
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
1941 local tmp 8
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
1942 lsl 1 B tmp
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
1943 mov main.R last_flag_result
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
1944 and main.R tmp tmp
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
1945 update_flags SZH1PN0
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
1946
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
1947 cb 01BBB110 bit_hl
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
1948 local tmp 8
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
1949 z80_fetch_hl
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
1950 lsl 1 B tmp
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
1951 lsr wz 8 last_flag_result
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
1952 and scratch1 tmp tmp
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
1953 update_flags SZH1PN0
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
1954
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
1955
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
1956 ddcb 01BBBRRR bit_ixd
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
1957 local tmp 8
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
1958 mov wz scratch1
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
1959 ocall read_8
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
1960 cycles 1
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
1961 lsl 1 B tmp
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
1962 lsr wz 8 last_flag_result
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
1963 and scratch1 tmp tmp
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
1964 update_flags SZH1PN0
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
1965
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
1966 fdcb 01BBBRRR bit_iyd
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
1967 local tmp 8
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
1968 mov wz scratch1
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
1969 ocall read_8
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
1970 cycles 1
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
1971 lsl 1 B tmp
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
1972 lsr wz 8 last_flag_result
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
1973 and scratch1 tmp tmp
1728
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
1974 update_flags SZH1PN0
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
1975
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
1976 cb 10BBBRRR res_reg
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
1977 local tmp 8
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
1978 lsl 1 B tmp
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
1979 not tmp tmp
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
1980 and main.R tmp main.R
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
1981
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
1982 cb 10BBB110 res_hl
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
1983 z80_fetch_hl
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
1984 cycles 1
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
1985 local tmp 8
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
1986 lsl 1 B tmp
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
1987 not tmp tmp
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
1988 and scratch1 tmp scratch1
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
1989 z80_store_hl
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
1990
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
1991 z80_res_index
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
1992 arg bit 8
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
1993 arg tmp 8
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
1994 lsl 1 bit tmp
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
1995 not tmp tmp
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
1996 mov wz scratch1
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
1997 ocall read_8
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
1998 cycles 1
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
1999 and scratch1 tmp tmp
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
2000 mov tmp scratch1
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
2001 z80_store_index
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
2002
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
2003 ddcb 10BBB110 res_ixd
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
2004 local tmp 8
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
2005 z80_res_index B tmp
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
2006
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
2007 ddcb 10BBBRRR res_ixd_reg
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
2008 z80_res_index B main.R
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
2009
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
2010 fdcb 10BBB110 res_iyd
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
2011 local tmp 8
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
2012 z80_res_index B tmp
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
2013
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
2014 fdcb 10BBBRRR res_iyd_reg
1729
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2015 z80_res_index B main.R
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2016
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2017 cb 11BBBRRR set_reg
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2018 local tmp 8
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2019 lsl 1 B tmp
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2020 or main.R tmp main.R
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2021
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2022 cb 11BBB110 set_hl
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2023 z80_fetch_hl
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2024 cycles 1
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2025 local tmp 8
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2026 lsl 1 B tmp
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2027 or scratch1 tmp scratch1
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2028 z80_store_hl
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2029
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2030 z80_set_index
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2031 arg bit 8
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2032 arg tmp 8
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2033 lsl 1 bit tmp
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2034 mov wz scratch1
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2035 ocall read_8
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2036 cycles 1
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2037 or scratch1 tmp tmp
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2038 mov tmp scratch1
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2039 z80_store_index
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2040
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2041 ddcb 11BBB110 set_ixd
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2042 local tmp 8
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2043 z80_set_index B tmp
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2044
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2045 ddcb 11BBBRRR set_ixd_reg
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2046 z80_set_index B main.R
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2047
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2048 fdcb 11BBB110 set_iyd
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2049 local tmp 8
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2050 z80_set_index B tmp
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2051
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2052 fdcb 11BBBRRR set_iyd_reg
1733
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2053 z80_set_index B main.R
1734
88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1733
diff changeset
2054
88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1733
diff changeset
2055 z80_fetch_mod_hl
1733
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2056 local tmp 16
1734
88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1733
diff changeset
2057 arg change 16
1733
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2058 lsl h 8 tmp
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2059 or l tmp tmp
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2060 mov tmp scratch1
1734
88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1733
diff changeset
2061 add change tmp tmp
1733
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2062 mov tmp l
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2063 lsr tmp 8 h
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2064 ocall read_8
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2065 cycles 1
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2066
1734
88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1733
diff changeset
2067 z80_ldd_ldi
88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1733
diff changeset
2068 arg change 16
88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1733
diff changeset
2069 local tmp 16
88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1733
diff changeset
2070 local tmp8 8
88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1733
diff changeset
2071 z80_fetch_mod_hl change
88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1733
diff changeset
2072
1733
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2073 add a scratch1 tmp8
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2074 update_flags H0XN0
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2075
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2076 and 0x2 tmp8 tmp8
1734
88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1733
diff changeset
2077 lsl tmp8 4 tmp8
1733
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2078 and 0x88 last_flag_result last_flag_result
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2079 or tmp8 last_flag_result last_flag_result
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2080
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2081 lsl d 8 tmp
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2082 or e tmp tmp
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2083 mov tmp scratch2
1734
88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1733
diff changeset
2084 add change tmp tmp
1733
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2085 mov tmp e
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2086 lsr tmp 8 d
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2087 ocall write_8
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2088
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2089 lsl b 8 tmp
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2090 or c tmp tmp
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2091 sub 1 tmp tmp
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2092
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2093 mov tmp c
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2094 lsr tmp 8 b
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2095 mov c pvflag
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2096 or b pvflag pvflag
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2097
1734
88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1733
diff changeset
2098 cycles 5
1733
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2099
1734
88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1733
diff changeset
2100
88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1733
diff changeset
2101 ed 10100000 ldi
88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1733
diff changeset
2102 z80_ldd_ldi 1
88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1733
diff changeset
2103
88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1733
diff changeset
2104 ed 10101000 ldd
88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1733
diff changeset
2105 z80_ldd_ldi -1
88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1733
diff changeset
2106
88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1733
diff changeset
2107 ed 10110000 ldir
88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1733
diff changeset
2108 z80_ldd_ldi 1
88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1733
diff changeset
2109 if pvflag
1733
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2110
1734
88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1733
diff changeset
2111 add 1 pc wz
1736
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2112 sub 2 pc pc
1733
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2113 cycles 5
1734
88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1733
diff changeset
2114
88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1733
diff changeset
2115 end
88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1733
diff changeset
2116
88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1733
diff changeset
2117 ed 10111000 lddr
88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1733
diff changeset
2118 z80_ldd_ldi -1
88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1733
diff changeset
2119 if pvflag
88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1733
diff changeset
2120
88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1733
diff changeset
2121 add 1 pc wz
1736
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2122 sub 2 pc pc
1734
88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1733
diff changeset
2123 cycles 5
88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1733
diff changeset
2124
88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1733
diff changeset
2125 end
88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1733
diff changeset
2126
1736
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2127 z80_cpd_cpi
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2128 local tmp 16
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2129 local tmp8 8
1742
6290c88949bd Fixed CPI/CPD/CPIR/CPDR in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1741
diff changeset
2130 local hf 8
1736
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2131 arg change 16
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2132
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2133 z80_fetch_mod_hl change
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2134 sub scratch1 a tmp8
1742
6290c88949bd Fixed CPI/CPD/CPIR/CPDR in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1741
diff changeset
2135 update_flags SZHN1
6290c88949bd Fixed CPI/CPD/CPIR/CPDR in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1741
diff changeset
2136
6290c88949bd Fixed CPI/CPD/CPIR/CPDR in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1741
diff changeset
2137 lsr chflags 3 hf
6290c88949bd Fixed CPI/CPD/CPIR/CPDR in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1741
diff changeset
2138 and 1 hf hf
6290c88949bd Fixed CPI/CPD/CPIR/CPDR in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1741
diff changeset
2139
6290c88949bd Fixed CPI/CPD/CPIR/CPDR in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1741
diff changeset
2140 sub hf tmp8 tmp8
6290c88949bd Fixed CPI/CPD/CPIR/CPDR in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1741
diff changeset
2141 update_flags X
1736
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2142
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2143 and 0x2 tmp8 tmp8
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2144 lsl tmp8 4 tmp8
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2145 and 0x88 last_flag_result last_flag_result
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2146 or tmp8 last_flag_result last_flag_result
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2147
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2148 lsl b 8 tmp
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2149 or c tmp tmp
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2150 sub 1 tmp tmp
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2151
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2152 mov tmp c
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2153 lsr tmp 8 b
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2154 mov c pvflag
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2155 or b pvflag pvflag
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2156
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2157 cycles 5
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2158
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2159 ed 10100001 cpi
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2160 z80_cpd_cpi 1
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2161
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2162 ed 10101001 cpd
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2163 z80_cpd_cpi -1
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2164
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2165 ed 10110001 cpir
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2166 z80_cpd_cpi 1
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2167 if pvflag
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2168
1742
6290c88949bd Fixed CPI/CPD/CPIR/CPDR in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1741
diff changeset
2169 if zflag
6290c88949bd Fixed CPI/CPD/CPIR/CPDR in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1741
diff changeset
2170
6290c88949bd Fixed CPI/CPD/CPIR/CPDR in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1741
diff changeset
2171 else
6290c88949bd Fixed CPI/CPD/CPIR/CPDR in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1741
diff changeset
2172
1736
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2173 add 1 pc wz
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2174 sub 2 pc pc
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2175 cycles 5
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2176
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2177 end
1742
6290c88949bd Fixed CPI/CPD/CPIR/CPDR in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1741
diff changeset
2178 end
1736
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2179
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2180 ed 10111001 cpdr
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2181 z80_cpd_cpi -1
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2182 if pvflag
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2183
1742
6290c88949bd Fixed CPI/CPD/CPIR/CPDR in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1741
diff changeset
2184 if zflag
6290c88949bd Fixed CPI/CPD/CPIR/CPDR in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1741
diff changeset
2185
6290c88949bd Fixed CPI/CPD/CPIR/CPDR in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1741
diff changeset
2186 else
6290c88949bd Fixed CPI/CPD/CPIR/CPDR in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1741
diff changeset
2187
1736
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2188 add 1 pc wz
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2189 sub 2 pc pc
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2190 cycles 5
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2191
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2192 end
1742
6290c88949bd Fixed CPI/CPD/CPIR/CPDR in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1741
diff changeset
2193 end
1734
88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1733
diff changeset
2194
1738
d6157b7eb20c Implemented DAA in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1736
diff changeset
2195 00100111 daa
d6157b7eb20c Implemented DAA in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1736
diff changeset
2196 local diff 8
d6157b7eb20c Implemented DAA in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1736
diff changeset
2197 local tmp 8
d6157b7eb20c Implemented DAA in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1736
diff changeset
2198 local low 8
d6157b7eb20c Implemented DAA in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1736
diff changeset
2199 and 0xF a low
d6157b7eb20c Implemented DAA in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1736
diff changeset
2200 and 0x8 chflags tmp
d6157b7eb20c Implemented DAA in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1736
diff changeset
2201 if tmp
d6157b7eb20c Implemented DAA in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1736
diff changeset
2202
d6157b7eb20c Implemented DAA in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1736
diff changeset
2203 mov 6 diff
d6157b7eb20c Implemented DAA in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1736
diff changeset
2204
d6157b7eb20c Implemented DAA in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1736
diff changeset
2205 else
d6157b7eb20c Implemented DAA in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1736
diff changeset
2206
d6157b7eb20c Implemented DAA in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1736
diff changeset
2207 cmp 0xA low
d6157b7eb20c Implemented DAA in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1736
diff changeset
2208 if >=U
d6157b7eb20c Implemented DAA in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1736
diff changeset
2209 mov 6 diff
d6157b7eb20c Implemented DAA in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1736
diff changeset
2210 else
d6157b7eb20c Implemented DAA in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1736
diff changeset
2211 mov 0 diff
d6157b7eb20c Implemented DAA in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1736
diff changeset
2212 end
d6157b7eb20c Implemented DAA in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1736
diff changeset
2213
d6157b7eb20c Implemented DAA in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1736
diff changeset
2214 end
d6157b7eb20c Implemented DAA in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1736
diff changeset
2215
d6157b7eb20c Implemented DAA in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1736
diff changeset
2216 and 0x80 chflags tmp
d6157b7eb20c Implemented DAA in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1736
diff changeset
2217 if tmp
d6157b7eb20c Implemented DAA in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1736
diff changeset
2218
d6157b7eb20c Implemented DAA in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1736
diff changeset
2219 or 0x60 diff diff
d6157b7eb20c Implemented DAA in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1736
diff changeset
2220
d6157b7eb20c Implemented DAA in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1736
diff changeset
2221 else
d6157b7eb20c Implemented DAA in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1736
diff changeset
2222
d6157b7eb20c Implemented DAA in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1736
diff changeset
2223 cmp 0xA0 a
d6157b7eb20c Implemented DAA in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1736
diff changeset
2224 if >=U
d6157b7eb20c Implemented DAA in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1736
diff changeset
2225 or 0x60 diff diff
d6157b7eb20c Implemented DAA in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1736
diff changeset
2226 end
d6157b7eb20c Implemented DAA in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1736
diff changeset
2227 end
d6157b7eb20c Implemented DAA in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1736
diff changeset
2228
d6157b7eb20c Implemented DAA in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1736
diff changeset
2229 if nflag
d6157b7eb20c Implemented DAA in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1736
diff changeset
2230
d6157b7eb20c Implemented DAA in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1736
diff changeset
2231 sub diff a a
d6157b7eb20c Implemented DAA in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1736
diff changeset
2232 update_flags SZYHPXC
d6157b7eb20c Implemented DAA in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1736
diff changeset
2233
d6157b7eb20c Implemented DAA in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1736
diff changeset
2234 else
d6157b7eb20c Implemented DAA in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1736
diff changeset
2235
d6157b7eb20c Implemented DAA in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1736
diff changeset
2236 add diff a a
d6157b7eb20c Implemented DAA in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1736
diff changeset
2237 update_flags SZYHPXC
d6157b7eb20c Implemented DAA in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1736
diff changeset
2238
d6157b7eb20c Implemented DAA in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1736
diff changeset
2239 end
d6157b7eb20c Implemented DAA in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1736
diff changeset
2240
1740
28ab56ff8cea Implement DD/FD prefixes for instructions that don't reference HL
Michael Pavone <pavone@retrodev.com>
parents: 1739
diff changeset
2241 dd OOOOOOOO dd_normal
28ab56ff8cea Implement DD/FD prefixes for instructions that don't reference HL
Michael Pavone <pavone@retrodev.com>
parents: 1739
diff changeset
2242 dispatch O
1738
d6157b7eb20c Implemented DAA in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1736
diff changeset
2243
1740
28ab56ff8cea Implement DD/FD prefixes for instructions that don't reference HL
Michael Pavone <pavone@retrodev.com>
parents: 1739
diff changeset
2244 fd OOOOOOOO fd_normal
28ab56ff8cea Implement DD/FD prefixes for instructions that don't reference HL
Michael Pavone <pavone@retrodev.com>
parents: 1739
diff changeset
2245 dispatch O
1741
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2246
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2247 ed 01101111 rld
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2248 local tmp 8
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2249 local tmp2 8
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2250 z80_fetch_hl
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2251 cycles 4
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2252
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2253 lsr scratch1 4 tmp
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2254
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2255 lsl scratch1 4 scratch1
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2256
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2257 and 0xF a tmp2
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2258 or tmp2 scratch1 scratch1
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2259
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2260 and 0xF0 a a
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2261 or tmp a a
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2262 update_flags SZYH0XPN0
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2263 z80_store_hl
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2264
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2265 ed 01100111 rrd
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2266 local tmp 8
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2267 local tmp2 8
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2268 z80_fetch_hl
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2269 cycles 4
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2270
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2271 and 0xF scratch1 tmp
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2272 lsr scratch1 4 scratch1
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2273
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2274 lsl a 4 tmp2
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2275 or tmp2 scratch1 scratch1
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2276
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2277 and 0xF0 a a
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2278 or tmp a a
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2279 update_flags SZYH0XPN0
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2280 z80_store_hl
1733
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2281