repos/blastem: gen_x86.c annotate

annotate gen_x86.c @ 51:937b47c9b79b

Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.

author	Mike Pavone <pavone@retrodev.com>
date	Sat, 15 Dec 2012 23:01:32 -0800
parents	d2e43d64e999
children	918468c623e9

rev	line source
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1 #include "gen_x86.h"
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	2 #include "68kinst.h"
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	3 #include <stddef.h>
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	4 #include <stdio.h>
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	5
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	6 #define REX_RM_FIELD 0x1
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	7 #define REX_SIB_FIELD 0x2
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	8 #define REX_REG_FIELD 0x4
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	9 #define REX_QUAD 0x8
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	10
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	11 #define OP_ADD 0x00
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	12 #define OP_OR 0x08
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	13 #define PRE_2BYTE 0x0F
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	14 #define OP_ADC 0x10
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	15 #define OP_SBB 0x18
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	16 #define OP_AND 0x20
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	17 #define OP_SUB 0x28
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	18 #define OP_XOR 0x30
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	19 #define OP_CMP 0x38
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	20 #define PRE_REX 0x40
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	21 #define OP_PUSH 0x50
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	22 #define OP_POP 0x58
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	23 #define PRE_SIZE 0x66
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	24 #define OP_JCC 0x70
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	25 #define OP_IMMED_ARITH 0x80
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	26 #define OP_MOV 0x88
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	27 #define OP_PUSHF 0x9C
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	28 #define OP_POPF 0x9D
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	29 #define OP_MOV_I8R 0xB0
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	30 #define OP_MOV_IR 0xB8
49 d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	31 #define OP_SHIFTROT_IR 0xC0
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	32 #define OP_RETN 0xC3
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	33 #define OP_MOV_IEA 0xC6
49 d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	34 #define OP_SHIFTROT_1 0xD0
51 937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	35 #define OP_SHIFTROT_CL 0xD2
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	36 #define OP_CALL 0xE8
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	37 #define OP_JMP 0xE9
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	38 #define OP_JMP_BYTE 0xEB
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	39 #define OP_CALL_EA 0xFF
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	40
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	41 #define OP2_JCC 0x80
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	42 #define OP2_SETCC 0x90
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	43
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	44 #define OP_EX_ADDI 0x0
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	45 #define OP_EX_ORI 0x1
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	46 #define OP_EX_ADCI 0x2
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	47 #define OP_EX_SBBI 0x3
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	48 #define OP_EX_ANDI 0x4
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	49 #define OP_EX_SUBI 0x5
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	50 #define OP_EX_XORI 0x6
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	51 #define OP_EX_CMPI 0x7
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	52
49 d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	53 #define OP_EX_ROL 0x0
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	54 #define OP_EX_ROR 0x1
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	55 #define OP_EX_RCL 0x2
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	56 #define OP_EX_RCR 0x3
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	57 #define OP_EX_SHL 0x4
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	58 #define OP_EX_SHR 0x5
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	59 #define OP_EX_SAL 0x6 //identical to SHL
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	60 #define OP_EX_SAR 0x7
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	61
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	62 #define BIT_IMMED_RAX 0x4
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	63 #define BIT_DIR 0x2
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	64 #define BIT_SIZE 0x1
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	65
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	66
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	67 enum {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	68 X86_RAX = 0,
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	69 X86_RCX,
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	70 X86_RDX,
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	71 X86_RBX,
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	72 X86_RSP,
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	73 X86_RBP,
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	74 X86_RSI,
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	75 X86_RDI,
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	76 X86_AH=4,
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	77 X86_CH,
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	78 X86_DH,
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	79 X86_BH,
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	80 X86_R8=0,
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	81 X86_R9,
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	82 X86_R10,
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	83 X86_R11,
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	84 X86_R12,
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	85 X86_R13,
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	86 X86_R14,
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	87 X86_R15
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	88 } x86_regs_enc;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	89
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	90 uint8_t * x86_rr_sizedir(uint8_t * out, uint8_t opcode, uint8_t src, uint8_t dst, uint8_t size)
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	91 {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	92 //TODO: Deal with the fact that AH, BH, CH and DH can only be in the R/M param when there's a REX prefix
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	93 uint8_t tmp;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	94 if (size == SZ_W) {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	95 *(out++) = PRE_SIZE;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	96 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	97 if (size == SZ_B && dst >= RSP && dst <= RDI) {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	98 opcode \|= BIT_DIR;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	99 tmp = dst;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	100 dst = src;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	101 src = dst;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	102 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	103 if (size == SZ_Q \|\| src >= R8 \|\| dst >= R8 \|\| (size == SZ_B && src >= RSP && src <= RDI)) {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	104 *out = PRE_REX;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	105 if (size == SZ_Q) {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	106 *out \|= REX_QUAD;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	107 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	108 if (src >= R8) {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	109 *out \|= REX_REG_FIELD;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	110 src -= (R8 - X86_R8);
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	111 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	112 if (dst >= R8) {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	113 *out \|= REX_RM_FIELD;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	114 dst -= (R8 - X86_R8);
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	115 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	116 out++;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	117 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	118 if (size == SZ_B) {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	119 if (src >= AH && src <= BH) {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	120 src -= (AH-X86_AH);
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	121 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	122 if (dst >= AH && dst <= BH) {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	123 dst -= (AH-X86_AH);
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	124 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	125 } else {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	126 opcode \|= BIT_SIZE;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	127 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	128 *(out++) = opcode;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	129 *(out++) = MODE_REG_DIRECT \| dst \| (src << 3);
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	130 return out;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	131 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	132
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	133 uint8_t * x86_rrdisp8_sizedir(uint8_t * out, uint8_t opcode, uint8_t reg, uint8_t base, int8_t disp, uint8_t size, uint8_t dir)
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	134 {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	135 //TODO: Deal with the fact that AH, BH, CH and DH can only be in the R/M param when there's a REX prefix
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	136 uint8_t tmp;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	137 if (size == SZ_W) {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	138 *(out++) = PRE_SIZE;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	139 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	140 if (size == SZ_Q \|\| reg >= R8 \|\| base >= R8 \|\| (size == SZ_B && reg >= RSP && reg <= RDI)) {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	141 *out = PRE_REX;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	142 if (size == SZ_Q) {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	143 *out \|= REX_QUAD;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	144 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	145 if (reg >= R8) {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	146 *out \|= REX_REG_FIELD;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	147 reg -= (R8 - X86_R8);
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	148 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	149 if (base >= R8) {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	150 *out \|= REX_RM_FIELD;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	151 base -= (R8 - X86_R8);
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	152 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	153 out++;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	154 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	155 if (size == SZ_B) {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	156 if (reg >= AH && reg <= BH) {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	157 reg -= (AH-X86_AH);
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	158 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	159 } else {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	160 opcode \|= BIT_SIZE;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	161 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	162 *(out++) = opcode \| dir;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	163 *(out++) = MODE_REG_DISPLACE8 \| base \| (reg << 3);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	164 if (base == RSP) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	165 //add SIB byte, with no index and RSP as base
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	166 *(out++) = (RSP << 3) \| RSP;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	167 }
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	168 *(out++) = disp;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	169 return out;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	170 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	171
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	172 uint8_t * x86_rrind_sizedir(uint8_t * out, uint8_t opcode, uint8_t reg, uint8_t base, uint8_t size, uint8_t dir)
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	173 {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	174 //TODO: Deal with the fact that AH, BH, CH and DH can only be in the R/M param when there's a REX prefix
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	175 uint8_t tmp;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	176 if (size == SZ_W) {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	177 *(out++) = PRE_SIZE;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	178 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	179 if (size == SZ_Q \|\| reg >= R8 \|\| base >= R8 \|\| (size == SZ_B && reg >= RSP && reg <= RDI)) {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	180 *out = PRE_REX;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	181 if (size == SZ_Q) {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	182 *out \|= REX_QUAD;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	183 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	184 if (reg >= R8) {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	185 *out \|= REX_REG_FIELD;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	186 reg -= (R8 - X86_R8);
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	187 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	188 if (base >= R8) {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	189 *out \|= REX_RM_FIELD;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	190 base -= (R8 - X86_R8);
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	191 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	192 out++;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	193 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	194 if (size == SZ_B) {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	195 if (reg >= AH && reg <= BH) {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	196 reg -= (AH-X86_AH);
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	197 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	198 } else {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	199 opcode \|= BIT_SIZE;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	200 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	201 *(out++) = opcode \| dir;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	202 *(out++) = MODE_REG_INDIRECT \| base \| (reg << 3);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	203 if (base == RSP) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	204 //add SIB byte, with no index and RSP as base
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	205 *(out++) = (RSP << 3) \| RSP;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	206 }
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	207 return out;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	208 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	209
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	210 uint8_t * x86_ir(uint8_t * out, uint8_t opcode, uint8_t op_ex, uint8_t al_opcode, int32_t val, uint8_t dst, uint8_t size)
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	211 {
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	212 uint8_t sign_extend = 0;
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	213 if ((size == SZ_D \|\| size == SZ_Q) && val <= 0x7F && val >= -0x80) {
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	214 sign_extend = 1;
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	215 opcode \|= BIT_DIR;
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	216 }
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	217 if (size == SZ_W) {
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	218 *(out++) = PRE_SIZE;
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	219 }
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	220 if (dst == RAX && !sign_extend) {
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	221 if (size != SZ_B) {
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	222 al_opcode \|= BIT_SIZE;
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	223 if (size == SZ_Q) {
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	224 *out = PRE_REX \| REX_QUAD;
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	225 }
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	226 }
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	227 *(out++) = al_opcode \| BIT_IMMED_RAX;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	228 } else {
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	229 if (size == SZ_Q \|\| dst >= R8 \|\| (size == SZ_B && dst >= RSP && dst <= RDI)) {
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	230 *out = PRE_REX;
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	231 if (size == SZ_Q) {
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	232 *out \|= REX_QUAD;
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	233 }
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	234 if (dst >= R8) {
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	235 *out \|= REX_RM_FIELD;
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	236 dst -= (R8 - X86_R8);
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	237 }
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	238 out++;
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	239 }
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	240 if (dst >= AH && dst <= BH) {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	241 dst -= (AH-X86_AH);
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	242 }
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	243 if (size != SZ_B) {
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	244 opcode \|= BIT_SIZE;
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	245 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	246 *(out++) = opcode;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	247 *(out++) = MODE_REG_DIRECT \| dst \| (op_ex << 3);
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	248 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	249 *(out++) = val;
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	250 if (size != SZ_B && !sign_extend) {
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	251 val >>= 8;
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	252 *(out++) = val;
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	253 if (size != SZ_W) {
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	254 val >>= 8;
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	255 *(out++) = val;
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	256 val >>= 8;
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	257 *(out++) = val;
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	258 }
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	259 }
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	260 return out;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	261 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	262
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	263 uint8_t * x86_irdisp8(uint8_t * out, uint8_t opcode, uint8_t op_ex, int32_t val, uint8_t dst, int8_t disp, uint8_t size)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	264 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	265 uint8_t sign_extend = 0;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	266 if ((size == SZ_D \|\| size == SZ_Q) && val <= 0x7F && val >= -0x80) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	267 sign_extend = 1;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	268 opcode \|= BIT_DIR;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	269 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	270 if (size == SZ_W) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	271 *(out++) = PRE_SIZE;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	272 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	273
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	274 if (size == SZ_Q \|\| dst >= R8 \|\| (size == SZ_B && dst >= RSP && dst <= RDI)) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	275 *out = PRE_REX;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	276 if (size == SZ_Q) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	277 *out \|= REX_QUAD;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	278 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	279 if (dst >= R8) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	280 *out \|= REX_RM_FIELD;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	281 dst -= (R8 - X86_R8);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	282 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	283 out++;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	284 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	285 if (dst >= AH && dst <= BH) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	286 dst -= (AH-X86_AH);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	287 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	288 if (size != SZ_B) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	289 opcode \|= BIT_SIZE;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	290 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	291 *(out++) = opcode;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	292 *(out++) = MODE_REG_DISPLACE8 \| dst \| (op_ex << 3);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	293 *(out++) = disp;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	294 *(out++) = val;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	295 if (size != SZ_B && !sign_extend) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	296 val >>= 8;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	297 *(out++) = val;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	298 if (size != SZ_W) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	299 val >>= 8;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	300 *(out++) = val;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	301 val >>= 8;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	302 *(out++) = val;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	303 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	304 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	305 return out;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	306 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	307
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	308
49 d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	309 uint8_t * x86_shiftrot_ir(uint8_t * out, uint8_t op_ex, uint8_t val, uint8_t dst, uint8_t size)
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	310 {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	311 if (size == SZ_W) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	312 *(out++) = PRE_SIZE;
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	313 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	314 if (size == SZ_Q \|\| dst >= R8 \|\| (size == SZ_B && dst >= RSP && dst <= RDI)) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	315 *out = PRE_REX;
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	316 if (size == SZ_Q) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	317 *out \|= REX_QUAD;
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	318 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	319 if (dst >= R8) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	320 *out \|= REX_RM_FIELD;
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	321 dst -= (R8 - X86_R8);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	322 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	323 out++;
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	324 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	325 if (dst >= AH && dst <= BH) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	326 dst -= (AH-X86_AH);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	327 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	328
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	329 *(out++) = (val == 1 ? OP_SHIFTROT_1: OP_SHIFTROT_IR) \| (size == SZ_B ? 0 : BIT_SIZE);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	330 *(out++) = MODE_REG_DIRECT \| dst \| (op_ex << 3);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	331 if (val != 1) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	332 *(out++) = val;
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	333 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	334 return out;
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	335 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	336
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	337 uint8_t * x86_shiftrot_irdisp8(uint8_t * out, uint8_t op_ex, uint8_t val, uint8_t dst, int8_t disp, uint8_t size)
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	338 {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	339 if (size == SZ_W) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	340 *(out++) = PRE_SIZE;
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	341 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	342 if (size == SZ_Q \|\| dst >= R8 \|\| (size == SZ_B && dst >= RSP && dst <= RDI)) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	343 *out = PRE_REX;
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	344 if (size == SZ_Q) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	345 *out \|= REX_QUAD;
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	346 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	347 if (dst >= R8) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	348 *out \|= REX_RM_FIELD;
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	349 dst -= (R8 - X86_R8);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	350 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	351 out++;
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	352 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	353 if (dst >= AH && dst <= BH) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	354 dst -= (AH-X86_AH);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	355 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	356
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	357 *(out++) = (val == 1 ? OP_SHIFTROT_1: OP_SHIFTROT_IR) \| (size == SZ_B ? 0 : BIT_SIZE);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	358 *(out++) = MODE_REG_DISPLACE8 \| dst \| (op_ex << 3);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	359 *(out++) = disp;
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	360 if (val != 1) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	361 *(out++) = val;
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	362 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	363 return out;
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	364 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	365
51 937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	366 uint8_t * x86_shiftrot_clr(uint8_t * out, uint8_t op_ex, uint8_t dst, uint8_t size)
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	367 {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	368 if (size == SZ_W) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	369 *(out++) = PRE_SIZE;
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	370 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	371 if (size == SZ_Q \|\| dst >= R8 \|\| (size == SZ_B && dst >= RSP && dst <= RDI)) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	372 *out = PRE_REX;
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	373 if (size == SZ_Q) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	374 *out \|= REX_QUAD;
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	375 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	376 if (dst >= R8) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	377 *out \|= REX_RM_FIELD;
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	378 dst -= (R8 - X86_R8);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	379 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	380 out++;
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	381 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	382 if (dst >= AH && dst <= BH) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	383 dst -= (AH-X86_AH);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	384 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	385
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	386 *(out++) = OP_SHIFTROT_CL \| (size == SZ_B ? 0 : BIT_SIZE);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	387 *(out++) = MODE_REG_DIRECT \| dst \| (op_ex << 3);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	388 return out;
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	389 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	390
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	391 uint8_t * x86_shiftrot_clrdisp8(uint8_t * out, uint8_t op_ex, uint8_t dst, int8_t disp, uint8_t size)
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	392 {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	393 if (size == SZ_W) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	394 *(out++) = PRE_SIZE;
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	395 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	396 if (size == SZ_Q \|\| dst >= R8 \|\| (size == SZ_B && dst >= RSP && dst <= RDI)) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	397 *out = PRE_REX;
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	398 if (size == SZ_Q) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	399 *out \|= REX_QUAD;
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	400 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	401 if (dst >= R8) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	402 *out \|= REX_RM_FIELD;
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	403 dst -= (R8 - X86_R8);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	404 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	405 out++;
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	406 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	407 if (dst >= AH && dst <= BH) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	408 dst -= (AH-X86_AH);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	409 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	410
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	411 *(out++) = OP_SHIFTROT_CL \| (size == SZ_B ? 0 : BIT_SIZE);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	412 *(out++) = MODE_REG_DISPLACE8 \| dst \| (op_ex << 3);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	413 *(out++) = disp;
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	414 return out;
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	415 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	416
49 d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	417 uint8_t * rol_ir(uint8_t * out, uint8_t val, uint8_t dst, uint8_t size)
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	418 {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	419 return x86_shiftrot_ir(out, OP_EX_ROL, val, dst, size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	420 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	421
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	422 uint8_t * ror_ir(uint8_t * out, uint8_t val, uint8_t dst, uint8_t size)
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	423 {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	424 return x86_shiftrot_ir(out, OP_EX_ROR, val, dst, size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	425 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	426
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	427 uint8_t * rcl_ir(uint8_t * out, uint8_t val, uint8_t dst, uint8_t size)
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	428 {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	429 return x86_shiftrot_ir(out, OP_EX_RCL, val, dst, size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	430 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	431
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	432 uint8_t * rcr_ir(uint8_t * out, uint8_t val, uint8_t dst, uint8_t size)
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	433 {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	434 return x86_shiftrot_ir(out, OP_EX_RCR, val, dst, size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	435 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	436
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	437 uint8_t * shl_ir(uint8_t * out, uint8_t val, uint8_t dst, uint8_t size)
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	438 {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	439 return x86_shiftrot_ir(out, OP_EX_SHL, val, dst, size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	440 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	441
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	442 uint8_t * shr_ir(uint8_t * out, uint8_t val, uint8_t dst, uint8_t size)
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	443 {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	444 return x86_shiftrot_ir(out, OP_EX_SHR, val, dst, size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	445 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	446
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	447 uint8_t * sar_ir(uint8_t * out, uint8_t val, uint8_t dst, uint8_t size)
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	448 {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	449 return x86_shiftrot_ir(out, OP_EX_SAR, val, dst, size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	450 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	451
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	452 uint8_t * rol_irdisp8(uint8_t * out, uint8_t val, uint8_t dst_base, int8_t disp, uint8_t size)
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	453 {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	454 return x86_shiftrot_irdisp8(out, OP_EX_ROL, val, dst_base, disp, size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	455 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	456
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	457 uint8_t * ror_irdisp8(uint8_t * out, uint8_t val, uint8_t dst_base, int8_t disp, uint8_t size)
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	458 {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	459 return x86_shiftrot_irdisp8(out, OP_EX_ROR, val, dst_base, disp, size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	460 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	461
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	462 uint8_t * rcl_irdisp8(uint8_t * out, uint8_t val, uint8_t dst_base, int8_t disp, uint8_t size)
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	463 {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	464 return x86_shiftrot_irdisp8(out, OP_EX_RCL, val, dst_base, disp, size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	465 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	466
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	467 uint8_t * rcr_irdisp8(uint8_t * out, uint8_t val, uint8_t dst_base, int8_t disp, uint8_t size)
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	468 {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	469 return x86_shiftrot_irdisp8(out, OP_EX_RCR, val, dst_base, disp, size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	470 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	471
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	472 uint8_t * shl_irdisp8(uint8_t * out, uint8_t val, uint8_t dst_base, int8_t disp, uint8_t size)
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	473 {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	474 return x86_shiftrot_irdisp8(out, OP_EX_SHL, val, dst_base, disp, size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	475 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	476
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	477 uint8_t * shr_irdisp8(uint8_t * out, uint8_t val, uint8_t dst_base, int8_t disp, uint8_t size)
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	478 {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	479 return x86_shiftrot_irdisp8(out, OP_EX_SHR, val, dst_base, disp, size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	480 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	481
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	482 uint8_t * sar_irdisp8(uint8_t * out, uint8_t val, uint8_t dst_base, int8_t disp, uint8_t size)
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	483 {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	484 return x86_shiftrot_irdisp8(out, OP_EX_SAR, val, dst_base, disp, size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	485 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	486
51 937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	487 uint8_t * rol_clr(uint8_t * out, uint8_t dst, uint8_t size)
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	488 {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	489 return x86_shiftrot_clr(out, OP_EX_ROL, dst, size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	490 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	491
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	492 uint8_t * ror_clr(uint8_t * out, uint8_t dst, uint8_t size)
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	493 {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	494 return x86_shiftrot_clr(out, OP_EX_ROR, dst, size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	495 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	496
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	497 uint8_t * rcl_clr(uint8_t * out, uint8_t dst, uint8_t size)
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	498 {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	499 return x86_shiftrot_clr(out, OP_EX_RCL, dst, size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	500 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	501
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	502 uint8_t * rcr_clr(uint8_t * out, uint8_t dst, uint8_t size)
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	503 {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	504 return x86_shiftrot_clr(out, OP_EX_RCR, dst, size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	505 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	506
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	507 uint8_t * shl_clr(uint8_t * out, uint8_t dst, uint8_t size)
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	508 {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	509 return x86_shiftrot_clr(out, OP_EX_SHL, dst, size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	510 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	511
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	512 uint8_t * shr_clr(uint8_t * out, uint8_t dst, uint8_t size)
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	513 {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	514 return x86_shiftrot_clr(out, OP_EX_SHR, dst, size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	515 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	516
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	517 uint8_t * sar_clr(uint8_t * out, uint8_t dst, uint8_t size)
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	518 {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	519 return x86_shiftrot_clr(out, OP_EX_SAR, dst, size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	520 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	521
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	522 uint8_t * rol_clrdisp8(uint8_t * out, uint8_t dst_base, int8_t disp, uint8_t size)
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	523 {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	524 return x86_shiftrot_clrdisp8(out, OP_EX_ROL, dst_base, disp, size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	525 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	526
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	527 uint8_t * ror_clrdisp8(uint8_t * out, uint8_t dst_base, int8_t disp, uint8_t size)
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	528 {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	529 return x86_shiftrot_clrdisp8(out, OP_EX_ROR, dst_base, disp, size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	530 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	531
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	532 uint8_t * rcl_clrdisp8(uint8_t * out, uint8_t dst_base, int8_t disp, uint8_t size)
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	533 {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	534 return x86_shiftrot_clrdisp8(out, OP_EX_RCL, dst_base, disp, size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	535 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	536
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	537 uint8_t * rcr_clrdisp8(uint8_t * out, uint8_t dst_base, int8_t disp, uint8_t size)
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	538 {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	539 return x86_shiftrot_clrdisp8(out, OP_EX_RCR, dst_base, disp, size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	540 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	541
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	542 uint8_t * shl_clrdisp8(uint8_t * out, uint8_t dst_base, int8_t disp, uint8_t size)
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	543 {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	544 return x86_shiftrot_clrdisp8(out, OP_EX_SHL, dst_base, disp, size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	545 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	546
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	547 uint8_t * shr_clrdisp8(uint8_t * out, uint8_t dst_base, int8_t disp, uint8_t size)
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	548 {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	549 return x86_shiftrot_clrdisp8(out, OP_EX_SHR, dst_base, disp, size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	550 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	551
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	552 uint8_t * sar_clrdisp8(uint8_t * out, uint8_t dst_base, int8_t disp, uint8_t size)
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	553 {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	554 return x86_shiftrot_clrdisp8(out, OP_EX_SAR, dst_base, disp, size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	555 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	556
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	557 uint8_t * add_rr(uint8_t * out, uint8_t src, uint8_t dst, uint8_t size)
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	558 {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	559 return x86_rr_sizedir(out, OP_ADD, src, dst, size);
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	560 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	561
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	562 uint8_t * add_ir(uint8_t * out, int32_t val, uint8_t dst, uint8_t size)
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	563 {
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	564 return x86_ir(out, OP_IMMED_ARITH, OP_EX_ADDI, OP_ADD, val, dst, size);
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	565 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	566
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	567 uint8_t * add_irdisp8(uint8_t * out, int32_t val, uint8_t dst_base, int8_t disp, uint8_t size)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	568 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	569 return x86_irdisp8(out, OP_IMMED_ARITH, OP_EX_ADDI, val, dst_base, disp, size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	570 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	571
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	572 uint8_t * add_rrdisp8(uint8_t * out, uint8_t src, uint8_t dst_base, int8_t disp, uint8_t size)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	573 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	574 return x86_rrdisp8_sizedir(out, OP_ADD, src, dst_base, disp, size, 0);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	575 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	576
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	577 uint8_t * add_rdisp8r(uint8_t * out, uint8_t src_base, int8_t disp, uint8_t dst, uint8_t size)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	578 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	579 return x86_rrdisp8_sizedir(out, OP_ADD, dst, src_base, disp, size, BIT_DIR);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	580 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	581
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	582 uint8_t * or_rr(uint8_t * out, uint8_t src, uint8_t dst, uint8_t size)
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	583 {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	584 return x86_rr_sizedir(out, OP_OR, src, dst, size);
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	585 }
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	586 uint8_t * or_ir(uint8_t * out, int32_t val, uint8_t dst, uint8_t size)
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	587 {
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	588 return x86_ir(out, OP_IMMED_ARITH, OP_EX_ORI, OP_OR, val, dst, size);
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	589 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	590
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	591 uint8_t * or_irdisp8(uint8_t * out, int32_t val, uint8_t dst_base, int8_t disp, uint8_t size)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	592 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	593 return x86_irdisp8(out, OP_IMMED_ARITH, OP_EX_ORI, val, dst_base, disp, size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	594 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	595
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	596 uint8_t * or_rrdisp8(uint8_t * out, uint8_t src, uint8_t dst_base, int8_t disp, uint8_t size)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	597 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	598 return x86_rrdisp8_sizedir(out, OP_OR, src, dst_base, disp, size, 0);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	599 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	600
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	601 uint8_t * or_rdisp8r(uint8_t * out, uint8_t src_base, int8_t disp, uint8_t dst, uint8_t size)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	602 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	603 return x86_rrdisp8_sizedir(out, OP_OR, dst, src_base, disp, size, BIT_DIR);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	604 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	605
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	606 uint8_t * and_rr(uint8_t * out, uint8_t src, uint8_t dst, uint8_t size)
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	607 {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	608 return x86_rr_sizedir(out, OP_AND, src, dst, size);
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	609 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	610
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	611 uint8_t * and_ir(uint8_t * out, int32_t val, uint8_t dst, uint8_t size)
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	612 {
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	613 return x86_ir(out, OP_IMMED_ARITH, OP_EX_ANDI, OP_AND, val, dst, size);
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	614 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	615
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	616 uint8_t * and_irdisp8(uint8_t * out, int32_t val, uint8_t dst_base, int8_t disp, uint8_t size)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	617 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	618 return x86_irdisp8(out, OP_IMMED_ARITH, OP_EX_ANDI, val, dst_base, disp, size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	619 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	620
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	621 uint8_t * and_rrdisp8(uint8_t * out, uint8_t src, uint8_t dst_base, int8_t disp, uint8_t size)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	622 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	623 return x86_rrdisp8_sizedir(out, OP_AND, src, dst_base, disp, size, 0);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	624 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	625
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	626 uint8_t * and_rdisp8r(uint8_t * out, uint8_t src_base, int8_t disp, uint8_t dst, uint8_t size)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	627 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	628 return x86_rrdisp8_sizedir(out, OP_AND, dst, src_base, disp, size, BIT_DIR);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	629 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	630
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	631 uint8_t * xor_rr(uint8_t * out, uint8_t src, uint8_t dst, uint8_t size)
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	632 {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	633 return x86_rr_sizedir(out, OP_XOR, src, dst, size);
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	634 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	635
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	636 uint8_t * xor_ir(uint8_t * out, int32_t val, uint8_t dst, uint8_t size)
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	637 {
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	638 return x86_ir(out, OP_IMMED_ARITH, OP_EX_XORI, OP_XOR, val, dst, size);
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	639 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	640
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	641 uint8_t * xor_irdisp8(uint8_t * out, int32_t val, uint8_t dst_base, int8_t disp, uint8_t size)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	642 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	643 return x86_irdisp8(out, OP_IMMED_ARITH, OP_EX_XORI, val, dst_base, disp, size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	644 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	645
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	646 uint8_t * xor_rrdisp8(uint8_t * out, uint8_t src, uint8_t dst_base, int8_t disp, uint8_t size)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	647 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	648 return x86_rrdisp8_sizedir(out, OP_XOR, src, dst_base, disp, size, 0);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	649 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	650
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	651 uint8_t * xor_rdisp8r(uint8_t * out, uint8_t src_base, int8_t disp, uint8_t dst, uint8_t size)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	652 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	653 return x86_rrdisp8_sizedir(out, OP_XOR, dst, src_base, disp, size, BIT_DIR);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	654 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	655
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	656 uint8_t * sub_rr(uint8_t * out, uint8_t src, uint8_t dst, uint8_t size)
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	657 {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	658 return x86_rr_sizedir(out, OP_SUB, src, dst, size);
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	659 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	660
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	661 uint8_t * sub_ir(uint8_t * out, int32_t val, uint8_t dst, uint8_t size)
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	662 {
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	663 return x86_ir(out, OP_IMMED_ARITH, OP_EX_SUBI, OP_SUB, val, dst, size);
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	664 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	665
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	666 uint8_t * sub_irdisp8(uint8_t * out, int32_t val, uint8_t dst_base, int8_t disp, uint8_t size)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	667 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	668 return x86_irdisp8(out, OP_IMMED_ARITH, OP_EX_SUBI, val, dst_base, disp, size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	669 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	670
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	671 uint8_t * sub_rrdisp8(uint8_t * out, uint8_t src, uint8_t dst_base, int8_t disp, uint8_t size)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	672 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	673 return x86_rrdisp8_sizedir(out, OP_SUB, src, dst_base, disp, size, 0);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	674 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	675
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	676 uint8_t * sub_rdisp8r(uint8_t * out, uint8_t src_base, int8_t disp, uint8_t dst, uint8_t size)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	677 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	678 return x86_rrdisp8_sizedir(out, OP_SUB, dst, src_base, disp, size, BIT_DIR);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	679 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	680
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	681 uint8_t * cmp_rr(uint8_t * out, uint8_t src, uint8_t dst, uint8_t size)
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	682 {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	683 return x86_rr_sizedir(out, OP_CMP, src, dst, size);
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	684 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	685
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	686 uint8_t * cmp_ir(uint8_t * out, int32_t val, uint8_t dst, uint8_t size)
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	687 {
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	688 return x86_ir(out, OP_IMMED_ARITH, OP_EX_CMPI, OP_CMP, val, dst, size);
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	689 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	690
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	691 uint8_t * cmp_irdisp8(uint8_t * out, int32_t val, uint8_t dst_base, int8_t disp, uint8_t size)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	692 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	693 return x86_irdisp8(out, OP_IMMED_ARITH, OP_EX_CMPI, val, dst_base, disp, size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	694 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	695
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	696 uint8_t * cmp_rrdisp8(uint8_t * out, uint8_t src, uint8_t dst_base, int8_t disp, uint8_t size)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	697 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	698 return x86_rrdisp8_sizedir(out, OP_CMP, src, dst_base, disp, size, 0);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	699 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	700
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	701 uint8_t * cmp_rdisp8r(uint8_t * out, uint8_t src_base, int8_t disp, uint8_t dst, uint8_t size)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	702 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	703 return x86_rrdisp8_sizedir(out, OP_CMP, dst, src_base, disp, size, BIT_DIR);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	704 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	705
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	706 uint8_t * mov_rr(uint8_t * out, uint8_t src, uint8_t dst, uint8_t size)
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	707 {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	708 return x86_rr_sizedir(out, OP_MOV, src, dst, size);
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	709 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	710
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	711 uint8_t * mov_rrdisp8(uint8_t * out, uint8_t src, uint8_t dst_base, int8_t disp, uint8_t size)
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	712 {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	713 return x86_rrdisp8_sizedir(out, OP_MOV, src, dst_base, disp, size, 0);
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	714 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	715
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	716 uint8_t * mov_rdisp8r(uint8_t * out, uint8_t src_base, int8_t disp, uint8_t dst, uint8_t size)
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	717 {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	718 return x86_rrdisp8_sizedir(out, OP_MOV, dst, src_base, disp, size, BIT_DIR);
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	719 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	720
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	721 uint8_t * mov_rrind(uint8_t * out, uint8_t src, uint8_t dst, uint8_t size)
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	722 {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	723 return x86_rrind_sizedir(out, OP_MOV, src, dst, size, 0);
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	724 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	725
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	726 uint8_t * mov_rindr(uint8_t * out, uint8_t src, uint8_t dst, uint8_t size)
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	727 {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	728 return x86_rrind_sizedir(out, OP_MOV, dst, src, size, BIT_DIR);
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	729 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	730
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	731 uint8_t * mov_ir(uint8_t * out, int64_t val, uint8_t dst, uint8_t size)
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	732 {
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	733 uint8_t sign_extend = 0;
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	734 if (size == SZ_Q && val <= 0x7FFFFFFF && val >= -2147483648) {
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	735 sign_extend = 1;
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	736 }
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	737 if (size == SZ_W) {
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	738 *(out++) = PRE_SIZE;
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	739 }
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	740 if (size == SZ_Q \|\| dst >= R8 \|\| (size == SZ_B && dst >= RSP && dst <= RDI)) {
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	741 *out = PRE_REX;
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	742 if (size == SZ_Q) {
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	743 *out \|= REX_QUAD;
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	744 }
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	745 if (dst >= R8) {
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	746 *out \|= REX_RM_FIELD;
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	747 dst -= (R8 - X86_R8);
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	748 }
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	749 out++;
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	750 }
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	751 if (dst >= AH && dst <= BH) {
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	752 dst -= (AH-X86_AH);
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	753 }
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	754 if (size == SZ_B) {
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	755 *(out++) = OP_MOV_I8R \| dst;
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	756 } else if (size == SZ_Q && sign_extend) {
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	757 *(out++) = OP_MOV_IEA \| BIT_SIZE;
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	758 *(out++) = MODE_REG_DIRECT \| dst;
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	759 } else {
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	760 *(out++) = OP_MOV_IR \| dst;
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	761 }
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	762 *(out++) = val;
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	763 if (size != SZ_B) {
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	764 val >>= 8;
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	765 *(out++) = val;
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	766 if (size != SZ_W) {
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	767 val >>= 8;
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	768 *(out++) = val;
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	769 val >>= 8;
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	770 *(out++) = val;
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	771 if (size == SZ_Q && !sign_extend) {
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	772 val >>= 8;
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	773 *(out++) = val;
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	774 val >>= 8;
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	775 *(out++) = val;
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	776 val >>= 8;
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	777 *(out++) = val;
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	778 val >>= 8;
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	779 *(out++) = val;
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	780 }
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	781 }
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	782 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	783 return out;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	784 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	785
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	786 uint8_t * mov_irdisp8(uint8_t * out, int32_t val, uint8_t dst, int8_t disp, uint8_t size)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	787 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	788 if (size == SZ_W) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	789 *(out++) = PRE_SIZE;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	790 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	791 if (size == SZ_Q \|\| dst >= R8 \|\| (size == SZ_B && dst >= RSP && dst <= RDI)) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	792 *out = PRE_REX;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	793 if (size == SZ_Q) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	794 *out \|= REX_QUAD;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	795 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	796 if (dst >= R8) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	797 *out \|= REX_RM_FIELD;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	798 dst -= (R8 - X86_R8);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	799 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	800 out++;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	801 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	802 if (dst >= AH && dst <= BH) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	803 dst -= (AH-X86_AH);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	804 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	805 *(out++) = OP_MOV_IEA \| (size == SZ_B ? 0 : BIT_SIZE);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	806 *(out++) = MODE_REG_DISPLACE8 \| dst;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	807 *(out++) = disp;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	808
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	809 *(out++) = val;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	810 if (size != SZ_B) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	811 val >>= 8;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	812 *(out++) = val;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	813 if (size != SZ_W) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	814 val >>= 8;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	815 *(out++) = val;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	816 val >>= 8;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	817 *(out++) = val;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	818 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	819 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	820 return out;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	821 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	822
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	823 uint8_t * pushf(uint8_t * out)
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	824 {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	825 *(out++) = OP_PUSHF;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	826 return out;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	827 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	828
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	829 uint8_t * popf(uint8_t * out)
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	830 {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	831 *(out++) = OP_POPF;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	832 return out;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	833 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	834
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	835 uint8_t * push_r(uint8_t * out, uint8_t reg)
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	836 {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	837 if (reg >= R8) {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	838 *(out++) = PRE_REX \| REX_RM_FIELD;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	839 reg -= R8 - X86_R8;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	840 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	841 *(out++) = OP_PUSH \| reg;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	842 return out;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	843 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	844
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	845 uint8_t * pop_r(uint8_t * out, uint8_t reg)
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	846 {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	847 if (reg >= R8) {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	848 *(out++) = PRE_REX \| REX_RM_FIELD;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	849 reg -= R8 - X86_R8;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	850 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	851 *(out++) = OP_POP \| reg;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	852 return out;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	853 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	854
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	855 uint8_t * setcc_r(uint8_t * out, uint8_t cc, uint8_t dst)
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	856 {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	857 if (dst >= R8) {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	858 *(out++) = PRE_REX \| REX_RM_FIELD;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	859 dst -= R8 - X86_R8;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	860 } else if (dst >= RSP && dst <= RDI) {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	861 *(out++) = PRE_REX;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	862 } else if (dst >= AH && dst <= BH) {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	863 dst -= AH - X86_AH;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	864 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	865 *(out++) = PRE_2BYTE;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	866 *(out++) = OP2_SETCC \| cc;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	867 *(out++) = MODE_REG_DIRECT \| dst;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	868 return out;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	869 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	870
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	871 uint8_t * setcc_rind(uint8_t * out, uint8_t cc, uint8_t dst)
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	872 {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	873 if (dst >= R8) {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	874 *(out++) = PRE_REX \| REX_RM_FIELD;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	875 dst -= R8 - X86_R8;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	876 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	877 *(out++) = PRE_2BYTE;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	878 *(out++) = OP2_SETCC \| cc;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	879 *(out++) = MODE_REG_INDIRECT \| dst;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	880 return out;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	881 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	882
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	883 uint8_t * jcc(uint8_t * out, uint8_t cc, uint8_t * dest)
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	884 {
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	885 ptrdiff_t disp = dest-(out+2);
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	886 if (disp <= 0x7F && disp >= -0x80) {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	887 *(out++) = OP_JCC \| cc;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	888 *(out++) = disp;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	889 } else {
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	890 disp = dest-(out+6);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	891 if (disp <= 0x7FFFFFFF && disp >= -2147483648) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	892 *(out++) = PRE_2BYTE;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	893 *(out++) = OP2_JCC \| cc;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	894 *(out++) = disp;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	895 disp >>= 8;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	896 *(out++) = disp;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	897 disp >>= 8;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	898 *(out++) = disp;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	899 disp >>= 8;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	900 *(out++) = disp;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	901 } else {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	902 printf("%p - %p = %lX\n", dest, out + 6, disp);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	903 return NULL;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	904 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	905 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	906 return out;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	907 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	908
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	909 uint8_t * jmp(uint8_t * out, uint8_t * dest)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	910 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	911 ptrdiff_t disp = dest-(out+2);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	912 if (disp <= 0x7F && disp >= -0x80) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	913 *(out++) = OP_JMP_BYTE;
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	914 *(out++) = disp;
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	915 } else {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	916 disp = dest-(out+5);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	917 if (disp <= 0x7FFFFFFF && disp >= -2147483648) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	918 *(out++) = OP_JMP;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	919 *(out++) = disp;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	920 disp >>= 8;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	921 *(out++) = disp;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	922 disp >>= 8;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	923 *(out++) = disp;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	924 disp >>= 8;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	925 *(out++) = disp;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	926 } else {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	927 printf("%p - %p = %lX\n", dest, out + 6, disp);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	928 return NULL;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	929 }
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	930 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	931 return out;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	932 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	933
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	934 uint8_t * call(uint8_t * out, uint8_t * fun)
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	935 {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	936 ptrdiff_t disp = fun-(out+5);
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	937 if (disp <= 0x7FFFFFFF && disp >= -2147483648) {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	938 *(out++) = OP_CALL;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	939 *(out++) = disp;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	940 disp >>= 8;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	941 *(out++) = disp;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	942 disp >>= 8;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	943 *(out++) = disp;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	944 disp >>= 8;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	945 *(out++) = disp;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	946 } else {
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	947 //TODO: Implement far call???
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	948 printf("%p - %p = %lX\n", fun, out + 5, disp);
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	949 return NULL;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	950 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	951 return out;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	952 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	953
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	954 uint8_t * retn(uint8_t * out)
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	955 {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	956 *(out++) = OP_RETN;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	957 return out;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	958 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	959
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	960

Mercurial > repos > blastem

annotate gen_x86.c @ 51:937b47c9b79b