Mercurial > repos > blastem
annotate z80_to_x86.c @ 272:9b04b57434b5
Implement LDI
author | Mike Pavone <pavone@retrodev.com> |
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date | Thu, 02 May 2013 22:26:47 -0700 |
parents | 3c054d977175 |
children | 719b9fea2fe9 |
rev | line source |
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1 #include "z80inst.h" |
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2 #include "z80_to_x86.h" |
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3 #include "gen_x86.h" |
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4 #include "mem.h" |
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5 #include <stdio.h> |
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6 #include <stdlib.h> |
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7 #include <stddef.h> |
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8 #include <string.h> |
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9 |
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10 #define MODE_UNUSED (MODE_IMMED-1) |
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11 |
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12 #define ZCYCLES RBP |
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13 #define ZLIMIT RDI |
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14 #define SCRATCH1 R13 |
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15 #define SCRATCH2 R14 |
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16 #define CONTEXT RSI |
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17 |
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18 #ifdef DO_DEBUG_PRINT |
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19 #define dprintf printf |
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20 #else |
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21 #define dprintf |
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22 #endif |
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23 |
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24 void z80_read_byte(); |
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25 void z80_read_word(); |
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26 void z80_write_byte(); |
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27 void z80_write_word_highfirst(); |
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28 void z80_write_word_lowfirst(); |
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29 void z80_save_context(); |
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30 void z80_native_addr(); |
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31 void z80_do_sync(); |
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32 void z80_handle_cycle_limit_int(); |
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33 void z80_retrans_stub(); |
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34 |
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35 uint8_t z80_size(z80inst * inst) |
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36 { |
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37 uint8_t reg = (inst->reg & 0x1F); |
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38 if (reg != Z80_UNUSED && reg != Z80_USE_IMMED) { |
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39 return reg < Z80_BC ? SZ_B : SZ_W; |
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40 } |
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41 //TODO: Handle any necessary special cases |
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42 return SZ_B; |
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43 } |
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44 |
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45 uint8_t z80_high_reg(uint8_t reg) |
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46 { |
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47 switch(reg) |
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48 { |
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49 case Z80_C: |
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50 case Z80_BC: |
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51 return Z80_B; |
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52 case Z80_E: |
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53 case Z80_DE: |
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54 return Z80_D; |
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55 case Z80_L: |
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56 case Z80_HL: |
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57 return Z80_H; |
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58 case Z80_IXL: |
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59 case Z80_IX: |
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60 return Z80_IXH; |
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61 case Z80_IYL: |
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62 case Z80_IY: |
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63 return Z80_IYH; |
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64 default: |
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65 return Z80_UNUSED; |
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66 } |
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67 } |
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68 |
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69 uint8_t z80_low_reg(uint8_t reg) |
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70 { |
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71 switch(reg) |
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72 { |
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73 case Z80_B: |
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74 case Z80_BC: |
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75 return Z80_C; |
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76 case Z80_D: |
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77 case Z80_DE: |
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78 return Z80_E; |
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79 case Z80_H: |
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80 case Z80_HL: |
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81 return Z80_L; |
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82 case Z80_IXH: |
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83 case Z80_IX: |
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84 return Z80_IXL; |
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85 case Z80_IYH: |
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86 case Z80_IY: |
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87 return Z80_IYL; |
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88 default: |
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89 return Z80_UNUSED; |
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90 } |
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91 } |
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92 |
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93 uint8_t * zcycles(uint8_t * dst, uint32_t num_cycles) |
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94 { |
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95 return add_ir(dst, num_cycles, ZCYCLES, SZ_D); |
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96 } |
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97 |
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98 uint8_t * z80_check_cycles_int(uint8_t * dst, uint16_t address) |
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99 { |
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100 dst = cmp_rr(dst, ZCYCLES, ZLIMIT, SZ_D); |
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101 uint8_t * jmp_off = dst+1; |
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102 dst = jcc(dst, CC_NC, dst + 7); |
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103 dst = mov_ir(dst, address, SCRATCH1, SZ_W); |
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104 dst = call(dst, (uint8_t *)z80_handle_cycle_limit_int); |
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105 *jmp_off = dst - (jmp_off+1); |
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106 return dst; |
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107 } |
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108 |
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109 uint8_t * translate_z80_reg(z80inst * inst, x86_ea * ea, uint8_t * dst, x86_z80_options * opts) |
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110 { |
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111 if (inst->reg == Z80_USE_IMMED) { |
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112 ea->mode = MODE_IMMED; |
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113 ea->disp = inst->immed; |
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114 } else if ((inst->reg & 0x1F) == Z80_UNUSED) { |
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115 ea->mode = MODE_UNUSED; |
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116 } else { |
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117 ea->mode = MODE_REG_DIRECT; |
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118 if (inst->reg == Z80_IYH) { |
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119 ea->base = opts->regs[Z80_IYL]; |
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120 dst = ror_ir(dst, 8, opts->regs[Z80_IY], SZ_W); |
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121 } else if(opts->regs[inst->reg] >= 0) { |
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122 ea->base = opts->regs[inst->reg]; |
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123 if (ea->base >= AH && ea->base <= BH) { |
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124 if ((inst->addr_mode & 0x1F) == Z80_REG) { |
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125 uint8_t other_reg = opts->regs[inst->ea_reg]; |
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126 if (other_reg >= R8 || (other_reg >= RSP && other_reg <= RDI)) { |
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127 //we can't mix an *H reg with a register that requires the REX prefix |
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128 ea->base = opts->regs[z80_low_reg(inst->reg)]; |
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129 dst = ror_ir(dst, 8, ea->base, SZ_W); |
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130 } |
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131 } else if((inst->addr_mode & 0x1F) != Z80_UNUSED && (inst->addr_mode & 0x1F) != Z80_IMMED) { |
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132 //temp regs require REX prefix too |
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133 ea->base = opts->regs[z80_low_reg(inst->reg)]; |
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134 dst = ror_ir(dst, 8, ea->base, SZ_W); |
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135 } |
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136 } |
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137 } else { |
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138 ea->mode = MODE_REG_DISPLACE8; |
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139 ea->base = CONTEXT; |
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140 ea->disp = offsetof(z80_context, regs) + inst->reg; |
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141 } |
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142 } |
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143 return dst; |
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144 } |
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145 |
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146 uint8_t * z80_save_reg(uint8_t * dst, z80inst * inst, x86_z80_options * opts) |
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147 { |
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148 if (inst->reg == Z80_IYH) { |
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149 dst = ror_ir(dst, 8, opts->regs[Z80_IY], SZ_W); |
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150 } else if (opts->regs[inst->reg] >= AH && opts->regs[inst->reg] <= BH) { |
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151 if ((inst->addr_mode & 0x1F) == Z80_REG) { |
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152 uint8_t other_reg = opts->regs[inst->ea_reg]; |
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153 if (other_reg >= R8 || (other_reg >= RSP && other_reg <= RDI)) { |
268
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154 //we can't mix an *H reg with a register that requires the REX prefix |
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155 dst = ror_ir(dst, 8, opts->regs[z80_low_reg(inst->reg)], SZ_W); |
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156 } |
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157 } else if((inst->addr_mode & 0x1F) != Z80_UNUSED && (inst->addr_mode & 0x1F) != Z80_IMMED) { |
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158 //temp regs require REX prefix too |
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159 dst = ror_ir(dst, 8, opts->regs[z80_low_reg(inst->reg)], SZ_W); |
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160 } |
213
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161 } |
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162 return dst; |
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163 } |
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164 |
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165 uint8_t * translate_z80_ea(z80inst * inst, x86_ea * ea, uint8_t * dst, x86_z80_options * opts, uint8_t read, uint8_t modify) |
213
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166 { |
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167 uint8_t size, reg, areg; |
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168 ea->mode = MODE_REG_DIRECT; |
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169 areg = read ? SCRATCH1 : SCRATCH2; |
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170 switch(inst->addr_mode & 0x1F) |
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171 { |
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172 case Z80_REG: |
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173 if (inst->ea_reg == Z80_IYH) { |
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174 ea->base = opts->regs[Z80_IYL]; |
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175 dst = ror_ir(dst, 8, opts->regs[Z80_IY], SZ_W); |
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176 } else { |
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177 ea->base = opts->regs[inst->ea_reg]; |
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178 if (ea->base >= AH && ea->base <= BH && inst->reg != Z80_UNUSED && inst->reg != Z80_USE_IMMED) { |
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179 uint8_t other_reg = opts->regs[inst->reg]; |
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180 if (other_reg >= R8 || (other_reg >= RSP && other_reg <= RDI)) { |
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181 //we can't mix an *H reg with a register that requires the REX prefix |
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182 ea->base = opts->regs[z80_low_reg(inst->ea_reg)]; |
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183 dst = ror_ir(dst, 8, ea->base, SZ_W); |
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184 } |
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185 } |
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186 } |
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187 break; |
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188 case Z80_REG_INDIRECT: |
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189 dst = mov_rr(dst, opts->regs[inst->ea_reg], areg, SZ_W); |
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190 size = z80_size(inst); |
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191 if (read) { |
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192 if (modify) { |
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193 dst = push_r(dst, SCRATCH1); |
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194 } |
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195 if (size == SZ_B) { |
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196 dst = call(dst, (uint8_t *)z80_read_byte); |
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197 } else { |
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198 dst = call(dst, (uint8_t *)z80_read_word); |
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199 } |
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200 if (modify) { |
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201 dst = pop_r(dst, SCRATCH2); |
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202 } |
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203 } |
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204 ea->base = SCRATCH1; |
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205 break; |
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206 case Z80_IMMED: |
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207 ea->mode = MODE_IMMED; |
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208 ea->disp = inst->immed; |
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209 break; |
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210 case Z80_IMMED_INDIRECT: |
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211 dst = mov_ir(dst, inst->immed, areg, SZ_W); |
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212 size = z80_size(inst); |
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213 if (read) { |
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214 if (modify) { |
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215 dst = push_r(dst, SCRATCH1); |
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216 } |
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217 if (size == SZ_B) { |
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218 dst = call(dst, (uint8_t *)z80_read_byte); |
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219 } else { |
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220 dst = call(dst, (uint8_t *)z80_read_word); |
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221 } |
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222 if (modify) { |
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223 dst = pop_r(dst, SCRATCH2); |
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224 } |
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225 } |
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226 ea->base = SCRATCH1; |
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227 break; |
235
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228 case Z80_IX_DISPLACE: |
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229 case Z80_IY_DISPLACE: |
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230 reg = opts->regs[inst->addr_mode == Z80_IX_DISPLACE ? Z80_IX : Z80_IY]; |
213
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231 dst = mov_rr(dst, reg, areg, SZ_W); |
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232 dst = add_ir(dst, inst->immed, areg, SZ_W); |
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233 size = z80_size(inst); |
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234 if (read) { |
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235 if (modify) { |
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236 dst = push_r(dst, SCRATCH1); |
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237 } |
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238 if (size == SZ_B) { |
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239 dst = call(dst, (uint8_t *)z80_read_byte); |
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240 } else { |
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241 dst = call(dst, (uint8_t *)z80_read_word); |
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242 } |
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243 if (modify) { |
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244 dst = pop_r(dst, SCRATCH2); |
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245 } |
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246 } |
269
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247 ea->base = SCRATCH1; |
213
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248 break; |
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249 case Z80_UNUSED: |
235
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250 ea->mode = MODE_UNUSED; |
213
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251 break; |
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252 default: |
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253 fprintf(stderr, "Unrecognized Z80 addressing mode %d\n", inst->addr_mode); |
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254 exit(1); |
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255 } |
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256 return dst; |
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257 } |
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258 |
235
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259 uint8_t * z80_save_ea(uint8_t * dst, z80inst * inst, x86_z80_options * opts) |
213
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260 { |
267
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261 if ((inst->addr_mode & 0x1F) == Z80_REG) { |
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262 if (inst->ea_reg == Z80_IYH) { |
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263 dst = ror_ir(dst, 8, opts->regs[Z80_IY], SZ_W); |
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264 } else if (inst->reg != Z80_UNUSED && inst->reg != Z80_USE_IMMED && opts->regs[inst->ea_reg] >= AH && opts->regs[inst->ea_reg] <= BH) { |
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265 uint8_t other_reg = opts->regs[inst->reg]; |
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266 if (other_reg >= R8 || (other_reg >= RSP && other_reg <= RDI)) { |
267
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267 //we can't mix an *H reg with a register that requires the REX prefix |
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268 dst = ror_ir(dst, 8, opts->regs[z80_low_reg(inst->ea_reg)], SZ_W); |
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269 } |
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270 } |
213
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271 } |
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272 return dst; |
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273 } |
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274 |
235
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275 uint8_t * z80_save_result(uint8_t * dst, z80inst * inst) |
213
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276 { |
253
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277 switch(inst->addr_mode & 0x1f) |
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278 { |
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279 case Z80_REG_INDIRECT: |
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280 case Z80_IMMED_INDIRECT: |
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281 case Z80_IX_DISPLACE: |
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282 case Z80_IY_DISPLACE: |
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283 if (z80_size(inst) == SZ_B) { |
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284 dst = call(dst, (uint8_t *)z80_write_byte); |
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285 } else { |
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286 dst = call(dst, (uint8_t *)z80_write_word_lowfirst); |
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287 } |
213
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288 } |
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289 return dst; |
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290 } |
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291 |
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292 enum { |
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293 DONT_READ=0, |
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294 READ |
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295 }; |
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296 |
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297 enum { |
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298 DONT_MODIFY=0, |
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299 MODIFY |
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300 }; |
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301 |
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302 uint8_t zf_off(uint8_t flag) |
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303 { |
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304 return offsetof(z80_context, flags) + flag; |
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305 } |
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306 |
241
2586d49ddd46
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307 uint8_t zaf_off(uint8_t flag) |
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308 { |
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309 return offsetof(z80_context, alt_flags) + flag; |
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310 } |
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311 |
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312 uint8_t zar_off(uint8_t reg) |
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313 { |
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314 return offsetof(z80_context, alt_regs) + reg; |
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315 } |
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316 |
235
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317 void z80_print_regs_exit(z80_context * context) |
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318 { |
243
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319 printf("A: %X\nB: %X\nC: %X\nD: %X\nE: %X\nHL: %X\nIX: %X\nIY: %X\nSP: %X\n\nIM: %d, IFF1: %d, IFF2: %d\n", |
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320 context->regs[Z80_A], context->regs[Z80_B], context->regs[Z80_C], |
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321 context->regs[Z80_D], context->regs[Z80_E], |
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322 (context->regs[Z80_H] << 8) | context->regs[Z80_L], |
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323 (context->regs[Z80_IXH] << 8) | context->regs[Z80_IXL], |
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324 (context->regs[Z80_IYH] << 8) | context->regs[Z80_IYL], |
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325 context->sp, context->im, context->iff1, context->iff2); |
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326 puts("--Alternate Regs--"); |
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327 printf("A: %X\nB: %X\nC: %X\nD: %X\nE: %X\nHL: %X\nIX: %X\nIY: %X\n", |
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328 context->alt_regs[Z80_A], context->alt_regs[Z80_B], context->alt_regs[Z80_C], |
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329 context->alt_regs[Z80_D], context->alt_regs[Z80_E], |
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330 (context->alt_regs[Z80_H] << 8) | context->alt_regs[Z80_L], |
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331 (context->alt_regs[Z80_IXH] << 8) | context->alt_regs[Z80_IXL], |
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332 (context->alt_regs[Z80_IYH] << 8) | context->alt_regs[Z80_IYL]); |
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333 exit(0); |
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334 } |
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335 |
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336 uint8_t * translate_z80inst(z80inst * inst, uint8_t * dst, z80_context * context, uint16_t address) |
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337 { |
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338 uint32_t cycles; |
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339 x86_ea src_op, dst_op; |
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340 uint8_t size; |
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341 x86_z80_options *opts = context->options; |
261
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342 uint8_t * start = dst; |
250
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343 dst = z80_check_cycles_int(dst, address); |
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344 switch(inst->op) |
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345 { |
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346 case Z80_LD: |
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347 size = z80_size(inst); |
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348 switch (inst->addr_mode & 0x1F) |
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349 { |
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350 case Z80_REG: |
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351 case Z80_REG_INDIRECT: |
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352 cycles = size == SZ_B ? 4 : 6; |
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353 if (inst->ea_reg == Z80_IX || inst->ea_reg == Z80_IY) { |
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354 cycles += 4; |
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355 } |
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356 break; |
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357 case Z80_IMMED: |
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358 cycles = size == SZ_B ? 7 : 10; |
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359 break; |
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360 case Z80_IMMED_INDIRECT: |
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361 cycles = 10; |
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362 break; |
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363 case Z80_IX_DISPLACE: |
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364 case Z80_IY_DISPLACE: |
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365 cycles = 12; |
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366 break; |
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367 } |
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368 if ((inst->reg >= Z80_IXL && inst->reg <= Z80_IYH) || inst->reg == Z80_IX || inst->reg == Z80_IY) { |
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369 cycles += 4; |
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370 } |
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371 dst = zcycles(dst, cycles); |
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372 if (inst->addr_mode & Z80_DIR) { |
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373 dst = translate_z80_reg(inst, &src_op, dst, opts); |
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374 dst = translate_z80_ea(inst, &dst_op, dst, opts, DONT_READ, MODIFY); |
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375 } else { |
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376 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
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377 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
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378 } |
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379 if (src_op.mode == MODE_REG_DIRECT) { |
262
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380 if(dst_op.mode == MODE_REG_DISPLACE8) { |
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381 dst = mov_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, size); |
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382 } else { |
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383 dst = mov_rr(dst, src_op.base, dst_op.base, size); |
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384 } |
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385 } else if(src_op.mode == MODE_IMMED) { |
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386 dst = mov_ir(dst, src_op.disp, dst_op.base, size); |
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387 } else { |
262
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388 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, size); |
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389 } |
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390 dst = z80_save_reg(dst, inst, opts); |
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391 dst = z80_save_ea(dst, inst, opts); |
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392 if (inst->addr_mode & Z80_DIR) { |
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393 dst = z80_save_result(dst, inst); |
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394 } |
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395 break; |
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396 case Z80_PUSH: |
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397 dst = zcycles(dst, (inst->reg == Z80_IX || inst->reg == Z80_IY) ? 9 : 5); |
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398 dst = sub_ir(dst, 2, opts->regs[Z80_SP], SZ_W); |
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399 if (inst->reg == Z80_AF) { |
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400 dst = mov_rdisp8r(dst, CONTEXT, zf_off(ZF_S), SCRATCH1, SZ_B); |
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401 dst = shl_ir(dst, 1, SCRATCH1, SZ_B); |
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402 dst = or_rdisp8r(dst, CONTEXT, zf_off(ZF_Z), SCRATCH1, SZ_B); |
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403 dst = shl_ir(dst, 2, SCRATCH1, SZ_B); |
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404 dst = or_rdisp8r(dst, CONTEXT, zf_off(ZF_H), SCRATCH1, SZ_B); |
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405 dst = shl_ir(dst, 2, SCRATCH1, SZ_B); |
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406 dst = or_rdisp8r(dst, CONTEXT, zf_off(ZF_PV), SCRATCH1, SZ_B); |
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407 dst = shl_ir(dst, 1, SCRATCH1, SZ_B); |
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408 dst = or_rdisp8r(dst, CONTEXT, zf_off(ZF_N), SCRATCH1, SZ_B); |
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409 dst = shl_ir(dst, 1, SCRATCH1, SZ_B); |
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410 dst = or_rdisp8r(dst, CONTEXT, zf_off(ZF_C), SCRATCH1, SZ_B); |
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411 dst = shl_ir(dst, 8, SCRATCH1, SZ_W); |
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412 dst = mov_rr(dst, opts->regs[Z80_A], SCRATCH1, SZ_B); |
235
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413 } else { |
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414 dst = translate_z80_reg(inst, &src_op, dst, opts); |
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415 dst = mov_rr(dst, src_op.base, SCRATCH1, SZ_W); |
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416 } |
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417 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH2, SZ_W); |
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418 dst = call(dst, (uint8_t *)z80_write_word_highfirst); |
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419 //no call to save_z80_reg needed since there's no chance we'll use the only |
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420 //the upper half of a register pair |
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421 break; |
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422 case Z80_POP: |
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423 dst = zcycles(dst, (inst->reg == Z80_IX || inst->reg == Z80_IY) ? 8 : 4); |
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424 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH1, SZ_W); |
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425 dst = call(dst, (uint8_t *)z80_read_word); |
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426 dst = add_ir(dst, 2, opts->regs[Z80_SP], SZ_W); |
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427 if (inst->reg == Z80_AF) { |
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428 dst = mov_rr(dst, SCRATCH1, opts->regs[Z80_A], SZ_B); |
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429 dst = bt_ir(dst, 8, SCRATCH1, SZ_W); |
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430 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
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431 dst = bt_ir(dst, 9, SCRATCH1, SZ_W); |
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432 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_N)); |
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433 dst = bt_ir(dst, 10, SCRATCH1, SZ_W); |
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434 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_PV)); |
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435 dst = bt_ir(dst, 12, SCRATCH1, SZ_W); |
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436 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_H)); |
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437 dst = bt_ir(dst, 14, SCRATCH1, SZ_W); |
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438 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_Z)); |
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439 dst = bt_ir(dst, 15, SCRATCH1, SZ_W); |
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440 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_S)); |
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441 } else { |
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442 dst = translate_z80_reg(inst, &src_op, dst, opts); |
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443 dst = mov_rr(dst, SCRATCH1, src_op.base, SZ_W); |
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444 } |
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445 //no call to save_z80_reg needed since there's no chance we'll use the only |
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446 //the upper half of a register pair |
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447 break; |
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448 case Z80_EX: |
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449 if (inst->addr_mode == Z80_REG || inst->reg == Z80_HL) { |
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450 cycles = 4; |
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451 } else { |
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452 cycles = 8; |
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453 } |
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454 dst = zcycles(dst, cycles); |
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455 if (inst->addr_mode == Z80_REG) { |
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456 if(inst->reg == Z80_AF) { |
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457 dst = mov_rr(dst, opts->regs[Z80_A], SCRATCH1, SZ_B); |
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458 dst = mov_rdisp8r(dst, CONTEXT, zar_off(Z80_A), opts->regs[Z80_A], SZ_B); |
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459 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, zar_off(Z80_A), SZ_B); |
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460 |
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461 //Flags are currently word aligned, so we can move |
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462 //them efficiently a word at a time |
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463 for (int f = ZF_C; f < ZF_NUM; f+=2) { |
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464 dst = mov_rdisp8r(dst, CONTEXT, zf_off(f), SCRATCH1, SZ_W); |
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465 dst = mov_rdisp8r(dst, CONTEXT, zaf_off(f), SCRATCH2, SZ_W); |
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466 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, zaf_off(f), SZ_W); |
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467 dst = mov_rrdisp8(dst, SCRATCH2, CONTEXT, zf_off(f), SZ_W); |
241
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468 } |
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469 } else { |
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470 dst = xchg_rr(dst, opts->regs[Z80_DE], opts->regs[Z80_HL], SZ_W); |
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471 } |
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472 } else { |
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473 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH1, SZ_W); |
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474 dst = call(dst, (uint8_t *)z80_read_byte); |
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475 dst = xchg_rr(dst, opts->regs[inst->reg], SCRATCH1, SZ_B); |
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476 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH2, SZ_W); |
241
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477 dst = call(dst, (uint8_t *)z80_write_byte); |
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478 dst = zcycles(dst, 1); |
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479 uint8_t high_reg = z80_high_reg(inst->reg); |
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480 uint8_t use_reg; |
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481 //even though some of the upper halves can be used directly |
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482 //the limitations on mixing *H regs with the REX prefix |
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483 //prevent us from taking advantage of it |
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484 use_reg = opts->regs[inst->reg]; |
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485 dst = ror_ir(dst, 8, use_reg, SZ_W); |
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486 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH1, SZ_W); |
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487 dst = add_ir(dst, 1, SCRATCH1, SZ_W); |
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488 dst = call(dst, (uint8_t *)z80_read_byte); |
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489 dst = xchg_rr(dst, use_reg, SCRATCH1, SZ_B); |
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490 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH2, SZ_W); |
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491 dst = add_ir(dst, 1, SCRATCH2, SZ_W); |
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492 dst = call(dst, (uint8_t *)z80_write_byte); |
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493 //restore reg to normal rotation |
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494 dst = ror_ir(dst, 8, use_reg, SZ_W); |
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495 dst = zcycles(dst, 2); |
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496 } |
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497 break; |
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498 case Z80_EXX: |
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499 dst = zcycles(dst, 4); |
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500 dst = mov_rr(dst, opts->regs[Z80_BC], SCRATCH1, SZ_W); |
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501 dst = mov_rr(dst, opts->regs[Z80_HL], SCRATCH2, SZ_W); |
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502 dst = mov_rdisp8r(dst, CONTEXT, zar_off(Z80_C), opts->regs[Z80_BC], SZ_W); |
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503 dst = mov_rdisp8r(dst, CONTEXT, zar_off(Z80_L), opts->regs[Z80_HL], SZ_W); |
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504 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, zar_off(Z80_C), SZ_W); |
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505 dst = mov_rrdisp8(dst, SCRATCH2, CONTEXT, zar_off(Z80_L), SZ_W); |
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506 dst = mov_rr(dst, opts->regs[Z80_DE], SCRATCH1, SZ_W); |
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507 dst = mov_rdisp8r(dst, CONTEXT, zar_off(Z80_E), opts->regs[Z80_DE], SZ_W); |
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508 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, zar_off(Z80_E), SZ_W); |
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509 break; |
272 | 510 case Z80_LDI: { |
511 dst = zcycles(dst, 8); | |
512 dst = mov_rr(dst, opts->regs[Z80_HL], SCRATCH1, SZ_W); | |
513 dst = call(dst, (uint8_t *)z80_read_byte); | |
514 dst = mov_rr(dst, opts->regs[Z80_DE], SCRATCH2, SZ_W); | |
515 dst = call(dst, (uint8_t *)z80_read_byte); | |
516 dst = zcycles(dst, 2); | |
517 dst = add_ir(dst, 1, opts->regs[Z80_DE], SZ_W); | |
518 dst = add_ir(dst, 1, opts->regs[Z80_HL], SZ_W); | |
519 dst = sub_ir(dst, 1, opts->regs[Z80_BC], SZ_W); | |
520 //TODO: Implement half-carry | |
521 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); | |
522 dst = setcc_rdisp8(dst, CC_NZ, CONTEXT, zf_off(ZF_PV)); | |
523 break; | |
524 } | |
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525 case Z80_LDIR: { |
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526 dst = zcycles(dst, 8); |
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527 dst = mov_rr(dst, opts->regs[Z80_HL], SCRATCH1, SZ_W); |
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528 dst = call(dst, (uint8_t *)z80_read_byte); |
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529 dst = mov_rr(dst, opts->regs[Z80_DE], SCRATCH2, SZ_W); |
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530 dst = call(dst, (uint8_t *)z80_read_byte); |
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531 dst = add_ir(dst, 1, opts->regs[Z80_DE], SZ_W); |
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532 dst = add_ir(dst, 1, opts->regs[Z80_HL], SZ_W); |
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533 |
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534 dst = sub_ir(dst, 1, opts->regs[Z80_BC], SZ_W); |
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535 uint8_t * cont = dst+1; |
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536 dst = jcc(dst, CC_Z, dst+2); |
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537 dst = zcycles(dst, 7); |
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538 //TODO: Figure out what the flag state should be here |
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539 //TODO: Figure out whether an interrupt can interrupt this |
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540 dst = jmp(dst, start); |
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541 *cont = dst - (cont + 1); |
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542 dst = zcycles(dst, 2); |
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543 //TODO: Implement half-carry |
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544 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
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545 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_PV), SZ_B); |
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546 break; |
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547 } |
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548 /*case Z80_LDD: |
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549 case Z80_LDDR: |
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550 case Z80_CPI: |
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551 case Z80_CPIR: |
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552 case Z80_CPD: |
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|
553 case Z80_CPDR: |
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|
554 break;*/ |
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555 case Z80_ADD: |
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|
556 cycles = 4; |
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557 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
213
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558 cycles += 12; |
4d4559b04c59
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559 } else if(inst->addr_mode == Z80_IMMED) { |
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560 cycles += 3; |
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561 } else if(z80_size(inst) == SZ_W) { |
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562 cycles += 4; |
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563 } |
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564 dst = zcycles(dst, cycles); |
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565 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
4d4559b04c59
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566 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
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567 if (src_op.mode == MODE_REG_DIRECT) { |
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568 dst = add_rr(dst, src_op.base, dst_op.base, z80_size(inst)); |
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569 } else { |
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570 dst = add_ir(dst, src_op.disp, dst_op.base, z80_size(inst)); |
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571 } |
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572 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
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573 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
213
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changeset
|
574 //TODO: Implement half-carry flag |
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575 if (z80_size(inst) == SZ_B) { |
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576 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV)); |
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577 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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578 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
213
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579 } |
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580 dst = z80_save_reg(dst, inst, opts); |
4d4559b04c59
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diff
changeset
|
581 dst = z80_save_ea(dst, inst, opts); |
4d4559b04c59
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582 break; |
248
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583 case Z80_ADC: |
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584 cycles = 4; |
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585 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
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|
586 cycles += 12; |
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587 } else if(inst->addr_mode == Z80_IMMED) { |
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588 cycles += 3; |
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589 } else if(z80_size(inst) == SZ_W) { |
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590 cycles += 4; |
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591 } |
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592 dst = zcycles(dst, cycles); |
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593 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
9c7a3db7bcd0
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|
594 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
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595 if (src_op.mode == MODE_REG_DIRECT) { |
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|
596 dst = adc_rr(dst, src_op.base, dst_op.base, z80_size(inst)); |
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597 } else { |
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Implement ADC and SBC in Z80 core (untested)
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|
598 dst = adc_ir(dst, src_op.disp, dst_op.base, z80_size(inst)); |
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599 } |
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600 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
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changeset
|
601 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
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|
602 //TODO: Implement half-carry flag |
9c7a3db7bcd0
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changeset
|
603 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV)); |
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604 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
9c7a3db7bcd0
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605 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
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606 dst = z80_save_reg(dst, inst, opts); |
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607 dst = z80_save_ea(dst, inst, opts); |
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608 break; |
213
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|
609 case Z80_SUB: |
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|
610 cycles = 4; |
235
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611 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
213
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changeset
|
612 cycles += 12; |
4d4559b04c59
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|
613 } else if(inst->addr_mode == Z80_IMMED) { |
4d4559b04c59
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|
614 cycles += 3; |
4d4559b04c59
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|
615 } |
4d4559b04c59
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|
616 dst = zcycles(dst, cycles); |
4d4559b04c59
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changeset
|
617 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
4d4559b04c59
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|
618 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
4d4559b04c59
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diff
changeset
|
619 if (src_op.mode == MODE_REG_DIRECT) { |
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diff
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620 dst = sub_rr(dst, src_op.base, dst_op.base, z80_size(inst)); |
4d4559b04c59
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diff
changeset
|
621 } else { |
4d4559b04c59
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Mike Pavone <pavone@retrodev.com>
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622 dst = sub_ir(dst, src_op.disp, dst_op.base, z80_size(inst)); |
4d4559b04c59
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diff
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|
623 } |
4d4559b04c59
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Mike Pavone <pavone@retrodev.com>
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|
624 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
235
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625 dst = mov_irdisp8(dst, 1, CONTEXT, zf_off(ZF_N), SZ_B); |
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626 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV)); |
213
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627 //TODO: Implement half-carry flag |
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628 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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629 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
213
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changeset
|
630 dst = z80_save_reg(dst, inst, opts); |
4d4559b04c59
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|
631 dst = z80_save_ea(dst, inst, opts); |
4d4559b04c59
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|
632 break; |
248
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633 case Z80_SBC: |
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634 cycles = 4; |
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635 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
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636 cycles += 12; |
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637 } else if(inst->addr_mode == Z80_IMMED) { |
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638 cycles += 3; |
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639 } else if(z80_size(inst) == SZ_W) { |
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640 cycles += 4; |
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641 } |
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642 dst = zcycles(dst, cycles); |
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643 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
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644 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
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645 if (src_op.mode == MODE_REG_DIRECT) { |
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646 dst = sbb_rr(dst, src_op.base, dst_op.base, z80_size(inst)); |
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647 } else { |
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648 dst = sbb_ir(dst, src_op.disp, dst_op.base, z80_size(inst)); |
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649 } |
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650 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
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651 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
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652 //TODO: Implement half-carry flag |
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653 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV)); |
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654 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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655 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
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656 dst = z80_save_reg(dst, inst, opts); |
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657 dst = z80_save_ea(dst, inst, opts); |
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658 break; |
213
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Mike Pavone <pavone@retrodev.com>
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659 case Z80_AND: |
236
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660 cycles = 4; |
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661 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
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662 cycles += 12; |
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663 } else if(inst->addr_mode == Z80_IMMED) { |
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664 cycles += 3; |
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665 } else if(z80_size(inst) == SZ_W) { |
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666 cycles += 4; |
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667 } |
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668 dst = zcycles(dst, cycles); |
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669 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
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670 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
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671 if (src_op.mode == MODE_REG_DIRECT) { |
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672 dst = and_rr(dst, src_op.base, dst_op.base, z80_size(inst)); |
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673 } else { |
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674 dst = and_ir(dst, src_op.disp, dst_op.base, z80_size(inst)); |
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675 } |
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676 //TODO: Cleanup flags |
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677 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
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678 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
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679 //TODO: Implement half-carry flag |
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680 if (z80_size(inst) == SZ_B) { |
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681 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV)); |
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682 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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683 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
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|
684 } |
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|
685 dst = z80_save_reg(dst, inst, opts); |
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686 dst = z80_save_ea(dst, inst, opts); |
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687 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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diff
changeset
|
688 case Z80_OR: |
236
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689 cycles = 4; |
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690 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
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691 cycles += 12; |
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|
692 } else if(inst->addr_mode == Z80_IMMED) { |
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diff
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|
693 cycles += 3; |
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694 } else if(z80_size(inst) == SZ_W) { |
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695 cycles += 4; |
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|
696 } |
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697 dst = zcycles(dst, cycles); |
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698 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
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699 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
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700 if (src_op.mode == MODE_REG_DIRECT) { |
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|
701 dst = or_rr(dst, src_op.base, dst_op.base, z80_size(inst)); |
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702 } else { |
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|
703 dst = or_ir(dst, src_op.disp, dst_op.base, z80_size(inst)); |
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704 } |
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|
705 //TODO: Cleanup flags |
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|
706 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
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707 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
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|
708 //TODO: Implement half-carry flag |
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|
709 if (z80_size(inst) == SZ_B) { |
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|
710 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV)); |
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|
711 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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712 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
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|
713 } |
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|
714 dst = z80_save_reg(dst, inst, opts); |
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|
715 dst = z80_save_ea(dst, inst, opts); |
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|
716 break; |
213
4d4559b04c59
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diff
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|
717 case Z80_XOR: |
236
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|
718 cycles = 4; |
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|
719 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
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|
720 cycles += 12; |
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|
721 } else if(inst->addr_mode == Z80_IMMED) { |
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|
722 cycles += 3; |
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|
723 } else if(z80_size(inst) == SZ_W) { |
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724 cycles += 4; |
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725 } |
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726 dst = zcycles(dst, cycles); |
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727 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
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728 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
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729 if (src_op.mode == MODE_REG_DIRECT) { |
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730 dst = add_rr(dst, src_op.base, dst_op.base, z80_size(inst)); |
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731 } else { |
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732 dst = add_ir(dst, src_op.disp, dst_op.base, z80_size(inst)); |
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733 } |
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734 //TODO: Cleanup flags |
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735 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
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736 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
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737 //TODO: Implement half-carry flag |
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738 if (z80_size(inst) == SZ_B) { |
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739 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV)); |
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740 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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741 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
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742 } |
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743 dst = z80_save_reg(dst, inst, opts); |
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744 dst = z80_save_ea(dst, inst, opts); |
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745 break; |
242 | 746 case Z80_CP: |
747 cycles = 4; | |
748 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { | |
749 cycles += 12; | |
750 } else if(inst->addr_mode == Z80_IMMED) { | |
751 cycles += 3; | |
752 } | |
753 dst = zcycles(dst, cycles); | |
754 dst = translate_z80_reg(inst, &dst_op, dst, opts); | |
755 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); | |
756 if (src_op.mode == MODE_REG_DIRECT) { | |
757 dst = cmp_rr(dst, src_op.base, dst_op.base, z80_size(inst)); | |
758 } else { | |
759 dst = cmp_ir(dst, src_op.disp, dst_op.base, z80_size(inst)); | |
760 } | |
761 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); | |
762 dst = mov_irdisp8(dst, 1, CONTEXT, zf_off(ZF_N), SZ_B); | |
763 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV)); | |
764 //TODO: Implement half-carry flag | |
765 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); | |
766 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); | |
767 dst = z80_save_reg(dst, inst, opts); | |
768 dst = z80_save_ea(dst, inst, opts); | |
769 break; | |
213
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diff
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|
770 case Z80_INC: |
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changeset
|
771 cycles = 4; |
4d4559b04c59
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|
772 if (inst->reg == Z80_IX || inst->reg == Z80_IY) { |
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changeset
|
773 cycles += 6; |
4d4559b04c59
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|
774 } else if(z80_size(inst) == SZ_W) { |
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diff
changeset
|
775 cycles += 2; |
4d4559b04c59
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|
776 } else if(inst->reg == Z80_IXH || inst->reg == Z80_IXL || inst->reg == Z80_IYH || inst->reg == Z80_IYL || inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
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diff
changeset
|
777 cycles += 4; |
4d4559b04c59
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|
778 } |
4d4559b04c59
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diff
changeset
|
779 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
4d4559b04c59
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diff
changeset
|
780 if (dst_op.mode == MODE_UNUSED) { |
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|
781 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY); |
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782 } |
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783 dst = add_ir(dst, 1, dst_op.base, z80_size(inst)); |
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784 if (z80_size(inst) == SZ_B) { |
235
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785 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
213
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|
786 //TODO: Implement half-carry flag |
235
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787 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV)); |
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788 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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789 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
213
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|
790 } |
4d4559b04c59
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|
791 dst = z80_save_reg(dst, inst, opts); |
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792 dst = z80_save_ea(dst, inst, opts); |
4d4559b04c59
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793 break; |
236
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794 case Z80_DEC: |
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795 cycles = 4; |
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796 if (inst->reg == Z80_IX || inst->reg == Z80_IY) { |
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797 cycles += 6; |
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798 } else if(z80_size(inst) == SZ_W) { |
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799 cycles += 2; |
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800 } else if(inst->reg == Z80_IXH || inst->reg == Z80_IXL || inst->reg == Z80_IYH || inst->reg == Z80_IYL || inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
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801 cycles += 4; |
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802 } |
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803 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
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804 if (dst_op.mode == MODE_UNUSED) { |
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235
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805 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY); |
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806 } |
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|
807 dst = sub_ir(dst, 1, dst_op.base, z80_size(inst)); |
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|
808 if (z80_size(inst) == SZ_B) { |
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809 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
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810 //TODO: Implement half-carry flag |
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|
811 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV)); |
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812 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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813 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
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814 } |
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815 dst = z80_save_reg(dst, inst, opts); |
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235
diff
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816 dst = z80_save_ea(dst, inst, opts); |
213
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diff
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|
817 break; |
236
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|
818 /*case Z80_DAA: |
213
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|
819 case Z80_CPL: |
257 | 820 case Z80_NEG:*/ |
213
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diff
changeset
|
821 case Z80_CCF: |
257 | 822 dst = zcycles(dst, 4); |
823 dst = xor_irdisp8(dst, 1, CONTEXT, zf_off(ZF_C), SZ_B); | |
824 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); | |
825 //TODO: Implement half-carry flag | |
826 break; | |
827 case Z80_SCF: | |
828 dst = zcycles(dst, 4); | |
829 dst = mov_irdisp8(dst, 1, CONTEXT, zf_off(ZF_C), SZ_B); | |
830 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); | |
831 //TODO: Implement half-carry flag | |
832 break; | |
213
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|
833 case Z80_NOP: |
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Mike Pavone <pavone@retrodev.com>
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|
834 if (inst->immed == 42) { |
4d4559b04c59
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|
835 dst = call(dst, (uint8_t *)z80_save_context); |
4d4559b04c59
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|
836 dst = mov_rr(dst, CONTEXT, RDI, SZ_Q); |
4d4559b04c59
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changeset
|
837 dst = jmp(dst, (uint8_t *)z80_print_regs_exit); |
4d4559b04c59
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diff
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|
838 } else { |
4d4559b04c59
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diff
changeset
|
839 dst = zcycles(dst, 4 * inst->immed); |
4d4559b04c59
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diff
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|
840 } |
4d4559b04c59
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diff
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|
841 break; |
243
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diff
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|
842 //case Z80_HALT: |
213
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|
843 case Z80_DI: |
243
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242
diff
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|
844 dst = zcycles(dst, 4); |
2f069a0b487e
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242
diff
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|
845 dst = mov_irdisp8(dst, 0, CONTEXT, offsetof(z80_context, iff1), SZ_B); |
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242
diff
changeset
|
846 dst = mov_irdisp8(dst, 0, CONTEXT, offsetof(z80_context, iff2), SZ_B); |
250
5f1b68cecfc7
Implemented basic interrupt support in Z80 core.
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248
diff
changeset
|
847 dst = mov_rdisp8r(dst, CONTEXT, offsetof(z80_context, sync_cycle), ZLIMIT, SZ_D); |
243
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242
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|
848 break; |
213
4d4559b04c59
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parents:
diff
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|
849 case Z80_EI: |
243
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242
diff
changeset
|
850 //TODO: Implement interrupt enable latency of 1 instruction afer EI |
2f069a0b487e
Implement EI, DI and IM in the Z80 core
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diff
changeset
|
851 dst = zcycles(dst, 4); |
2f069a0b487e
Implement EI, DI and IM in the Z80 core
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242
diff
changeset
|
852 dst = mov_irdisp8(dst, 1, CONTEXT, offsetof(z80_context, iff1), SZ_B); |
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Implement EI, DI and IM in the Z80 core
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diff
changeset
|
853 dst = mov_irdisp8(dst, 1, CONTEXT, offsetof(z80_context, iff2), SZ_B); |
250
5f1b68cecfc7
Implemented basic interrupt support in Z80 core.
Mike Pavone <pavone@retrodev.com>
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248
diff
changeset
|
854 dst = call(dst, (uint8_t *)z80_do_sync); |
243
2f069a0b487e
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Mike Pavone <pavone@retrodev.com>
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242
diff
changeset
|
855 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
856 case Z80_IM: |
243
2f069a0b487e
Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
242
diff
changeset
|
857 dst = zcycles(dst, 4); |
2f069a0b487e
Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
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242
diff
changeset
|
858 dst = mov_irdisp8(dst, inst->immed, CONTEXT, offsetof(z80_context, im), SZ_B); |
2f069a0b487e
Implement EI, DI and IM in the Z80 core
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parents:
242
diff
changeset
|
859 break; |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
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246
diff
changeset
|
860 case Z80_RLC: |
682e505f5757
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246
diff
changeset
|
861 cycles = inst->immed == 1 ? 4 : (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8); |
682e505f5757
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246
diff
changeset
|
862 dst = zcycles(dst, cycles); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
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246
diff
changeset
|
863 if (inst->reg == Z80_UNUSED) { |
682e505f5757
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246
diff
changeset
|
864 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY); |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
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246
diff
changeset
|
865 dst = zcycles(dst, 1); |
682e505f5757
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parents:
246
diff
changeset
|
866 } else { |
682e505f5757
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parents:
246
diff
changeset
|
867 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
682e505f5757
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parents:
246
diff
changeset
|
868 } |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
869 dst = rol_ir(dst, 1, dst_op.base, SZ_B); |
682e505f5757
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246
diff
changeset
|
870 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
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246
diff
changeset
|
871 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
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246
diff
changeset
|
872 //TODO: Implement half-carry flag |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
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246
diff
changeset
|
873 dst = cmp_ir(dst, 0, dst_op.base, SZ_B); |
682e505f5757
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parents:
246
diff
changeset
|
874 dst = setcc_rdisp8(dst, CC_P, CONTEXT, zf_off(ZF_PV)); |
682e505f5757
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246
diff
changeset
|
875 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
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246
diff
changeset
|
876 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
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246
diff
changeset
|
877 if (inst->reg == Z80_UNUSED) { |
682e505f5757
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246
diff
changeset
|
878 dst = z80_save_result(dst, inst); |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
879 } else { |
682e505f5757
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parents:
246
diff
changeset
|
880 dst = z80_save_reg(dst, inst, opts); |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
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246
diff
changeset
|
881 } |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
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246
diff
changeset
|
882 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
883 case Z80_RL: |
247
682e505f5757
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Mike Pavone <pavone@retrodev.com>
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246
diff
changeset
|
884 cycles = inst->immed == 1 ? 4 : (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8); |
682e505f5757
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parents:
246
diff
changeset
|
885 dst = zcycles(dst, cycles); |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
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246
diff
changeset
|
886 if (inst->reg == Z80_UNUSED) { |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
887 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY); |
682e505f5757
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246
diff
changeset
|
888 dst = zcycles(dst, 1); |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
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246
diff
changeset
|
889 } else { |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
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246
diff
changeset
|
890 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
682e505f5757
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246
diff
changeset
|
891 } |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
892 dst = bt_irdisp8(dst, 0, CONTEXT, zf_off(ZF_C), SZ_B); |
682e505f5757
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246
diff
changeset
|
893 dst = rcl_ir(dst, 1, dst_op.base, SZ_B); |
682e505f5757
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246
diff
changeset
|
894 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
682e505f5757
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246
diff
changeset
|
895 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
682e505f5757
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246
diff
changeset
|
896 //TODO: Implement half-carry flag |
682e505f5757
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246
diff
changeset
|
897 dst = cmp_ir(dst, 0, dst_op.base, SZ_B); |
682e505f5757
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246
diff
changeset
|
898 dst = setcc_rdisp8(dst, CC_P, CONTEXT, zf_off(ZF_PV)); |
682e505f5757
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246
diff
changeset
|
899 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
682e505f5757
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246
diff
changeset
|
900 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
682e505f5757
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246
diff
changeset
|
901 if (inst->reg == Z80_UNUSED) { |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
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parents:
246
diff
changeset
|
902 dst = z80_save_result(dst, inst); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
903 } else { |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
904 dst = z80_save_reg(dst, inst, opts); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
905 } |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
906 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
907 case Z80_RRC: |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
908 cycles = inst->immed == 1 ? 4 : (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
909 dst = zcycles(dst, cycles); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
910 if (inst->reg == Z80_UNUSED) { |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
911 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
912 dst = zcycles(dst, 1); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
913 } else { |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
914 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
915 } |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
916 dst = ror_ir(dst, 1, dst_op.base, SZ_B); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
917 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
918 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
919 //TODO: Implement half-carry flag |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
920 dst = cmp_ir(dst, 0, dst_op.base, SZ_B); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
921 dst = setcc_rdisp8(dst, CC_P, CONTEXT, zf_off(ZF_PV)); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
922 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
923 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
924 if (inst->reg == Z80_UNUSED) { |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
925 dst = z80_save_result(dst, inst); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
926 } else { |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
927 dst = z80_save_reg(dst, inst, opts); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
928 } |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
929 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
930 case Z80_RR: |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
931 cycles = inst->immed == 1 ? 4 : (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
932 dst = zcycles(dst, cycles); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
933 if (inst->reg == Z80_UNUSED) { |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
934 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
935 dst = zcycles(dst, 1); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
936 } else { |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
937 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
938 } |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
939 dst = bt_irdisp8(dst, 0, CONTEXT, zf_off(ZF_C), SZ_B); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
940 dst = rcr_ir(dst, 1, dst_op.base, SZ_B); |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
941 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
942 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
943 //TODO: Implement half-carry flag |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
944 dst = cmp_ir(dst, 0, dst_op.base, SZ_B); |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
945 dst = setcc_rdisp8(dst, CC_P, CONTEXT, zf_off(ZF_PV)); |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
946 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
947 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
948 if (inst->reg == Z80_UNUSED) { |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
949 dst = z80_save_result(dst, inst); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
950 } else { |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
951 dst = z80_save_reg(dst, inst, opts); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
952 } |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
953 break; |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
954 /*case Z80_SLA: |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
955 case Z80_SRA: |
4d4559b04c59
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Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
956 case Z80_SLL: |
4d4559b04c59
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Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
957 case Z80_SRL: |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
958 case Z80_RLD: |
239
a5bea9711a46
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Mike Pavone <pavone@retrodev.com>
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238
diff
changeset
|
959 case Z80_RRD:*/ |
213
4d4559b04c59
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Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
960 case Z80_BIT: |
239
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238
diff
changeset
|
961 cycles = (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) ? 8 : 16; |
a5bea9711a46
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diff
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|
962 dst = zcycles(dst, cycles); |
a5bea9711a46
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238
diff
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|
963 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
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|
964 if (inst->addr_mode != Z80_REG) { |
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238
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|
965 //Reads normally take 3 cycles, but the read at the end of a bit instruction takes 4 |
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238
diff
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|
966 dst = zcycles(dst, 1); |
a5bea9711a46
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238
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|
967 } |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
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|
968 dst = bt_ir(dst, inst->immed, src_op.base, SZ_B); |
a5bea9711a46
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|
969 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_Z)); |
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238
diff
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|
970 break; |
247
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246
diff
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|
971 case Z80_SET: |
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246
diff
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|
972 cycles = (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) ? 8 : 16; |
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|
973 dst = zcycles(dst, cycles); |
682e505f5757
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246
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|
974 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
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246
diff
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|
975 if (inst->addr_mode != Z80_REG) { |
682e505f5757
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246
diff
changeset
|
976 //Reads normally take 3 cycles, but the read in the middle of a set instruction takes 4 |
682e505f5757
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246
diff
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|
977 dst = zcycles(dst, 1); |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
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246
diff
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|
978 } |
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parents:
246
diff
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|
979 dst = bts_ir(dst, inst->immed, src_op.base, SZ_B); |
682e505f5757
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246
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changeset
|
980 if (inst->addr_mode != Z80_REG) { |
682e505f5757
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246
diff
changeset
|
981 dst = z80_save_result(dst, inst); |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
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|
982 } |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
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|
983 break; |
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Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
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|
984 case Z80_RES: |
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parents:
246
diff
changeset
|
985 cycles = (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) ? 8 : 16; |
682e505f5757
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parents:
246
diff
changeset
|
986 dst = zcycles(dst, cycles); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
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parents:
246
diff
changeset
|
987 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
682e505f5757
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246
diff
changeset
|
988 if (inst->addr_mode != Z80_REG) { |
682e505f5757
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246
diff
changeset
|
989 //Reads normally take 3 cycles, but the read in the middle of a set instruction takes 4 |
682e505f5757
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246
diff
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|
990 dst = zcycles(dst, 1); |
682e505f5757
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246
diff
changeset
|
991 } |
682e505f5757
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246
diff
changeset
|
992 dst = btr_ir(dst, inst->immed, src_op.base, SZ_B); |
682e505f5757
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parents:
246
diff
changeset
|
993 if (inst->addr_mode != Z80_REG) { |
682e505f5757
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parents:
246
diff
changeset
|
994 dst = z80_save_result(dst, inst); |
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246
diff
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|
995 } |
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|
996 break; |
236
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diff
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|
997 case Z80_JP: { |
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diff
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|
998 cycles = 4; |
239
a5bea9711a46
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parents:
238
diff
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|
999 if (inst->addr_mode != Z80_REG) { |
236
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diff
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|
1000 cycles += 6; |
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|
1001 } else if(inst->ea_reg == Z80_IX || inst->ea_reg == Z80_IY) { |
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|
1002 cycles += 4; |
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|
1003 } |
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|
1004 dst = zcycles(dst, cycles); |
239
a5bea9711a46
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238
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|
1005 if (inst->addr_mode != Z80_REG_INDIRECT && inst->immed < 0x4000) { |
236
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|
1006 uint8_t * call_dst = z80_get_native_address(context, inst->immed); |
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|
1007 if (!call_dst) { |
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|
1008 opts->deferred = defer_address(opts->deferred, inst->immed, dst + 1); |
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|
1009 //fake address to force large displacement |
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|
1010 call_dst = dst + 256; |
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|
1011 } |
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|
1012 dst = jmp(dst, call_dst); |
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|
1013 } else { |
239
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238
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|
1014 if (inst->addr_mode == Z80_REG_INDIRECT) { |
236
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|
1015 dst = mov_rr(dst, opts->regs[inst->ea_reg], SCRATCH1, SZ_W); |
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|
1016 } else { |
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|
1017 dst = mov_ir(dst, inst->immed, SCRATCH1, SZ_W); |
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|
1018 } |
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|
1019 dst = call(dst, (uint8_t *)z80_native_addr); |
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|
1020 dst = jmp_r(dst, SCRATCH1); |
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|
1021 } |
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|
1022 break; |
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|
1023 } |
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|
1024 case Z80_JPCC: { |
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235
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|
1025 dst = zcycles(dst, 7);//T States: 4,3 |
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235
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|
1026 uint8_t cond = CC_Z; |
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235
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|
1027 switch (inst->reg) |
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235
diff
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|
1028 { |
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diff
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|
1029 case Z80_CC_NZ: |
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|
1030 cond = CC_NZ; |
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|
1031 case Z80_CC_Z: |
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235
diff
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|
1032 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_Z), SZ_B); |
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235
diff
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|
1033 break; |
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|
1034 case Z80_CC_NC: |
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235
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|
1035 cond = CC_NZ; |
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|
1036 case Z80_CC_C: |
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235
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|
1037 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_C), SZ_B); |
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235
diff
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|
1038 break; |
238
827ebce557bf
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236
diff
changeset
|
1039 case Z80_CC_PO: |
827ebce557bf
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236
diff
changeset
|
1040 cond = CC_NZ; |
827ebce557bf
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236
diff
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|
1041 case Z80_CC_PE: |
827ebce557bf
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236
diff
changeset
|
1042 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_PV), SZ_B); |
827ebce557bf
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236
diff
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|
1043 break; |
827ebce557bf
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236
diff
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|
1044 case Z80_CC_P: |
827ebce557bf
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236
diff
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|
1045 case Z80_CC_M: |
827ebce557bf
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236
diff
changeset
|
1046 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_S), SZ_B); |
827ebce557bf
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236
diff
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|
1047 break; |
236
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235
diff
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|
1048 } |
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235
diff
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|
1049 uint8_t *no_jump_off = dst+1; |
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diff
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|
1050 dst = jcc(dst, cond, dst+2); |
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235
diff
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|
1051 dst = zcycles(dst, 5);//T States: 5 |
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|
1052 uint16_t dest_addr = inst->immed; |
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|
1053 if (dest_addr < 0x4000) { |
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diff
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|
1054 uint8_t * call_dst = z80_get_native_address(context, dest_addr); |
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|
1055 if (!call_dst) { |
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diff
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|
1056 opts->deferred = defer_address(opts->deferred, dest_addr, dst + 1); |
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diff
changeset
|
1057 //fake address to force large displacement |
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|
1058 call_dst = dst + 256; |
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235
diff
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|
1059 } |
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|
1060 dst = jmp(dst, call_dst); |
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diff
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|
1061 } else { |
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|
1062 dst = mov_ir(dst, dest_addr, SCRATCH1, SZ_W); |
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|
1063 dst = call(dst, (uint8_t *)z80_native_addr); |
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|
1064 dst = jmp_r(dst, SCRATCH1); |
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1065 } |
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1066 *no_jump_off = dst - (no_jump_off+1); |
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1067 break; |
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1068 } |
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1069 case Z80_JR: { |
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1070 dst = zcycles(dst, 12);//T States: 4,3,5 |
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1071 uint16_t dest_addr = address + inst->immed + 2; |
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1072 if (dest_addr < 0x4000) { |
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1073 uint8_t * call_dst = z80_get_native_address(context, dest_addr); |
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1074 if (!call_dst) { |
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1075 opts->deferred = defer_address(opts->deferred, dest_addr, dst + 1); |
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1076 //fake address to force large displacement |
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1077 call_dst = dst + 256; |
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1078 } |
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1079 dst = jmp(dst, call_dst); |
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1080 } else { |
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1081 dst = mov_ir(dst, dest_addr, SCRATCH1, SZ_W); |
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1082 dst = call(dst, (uint8_t *)z80_native_addr); |
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1083 dst = jmp_r(dst, SCRATCH1); |
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1084 } |
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1085 break; |
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1086 } |
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1087 case Z80_JRCC: { |
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1088 dst = zcycles(dst, 7);//T States: 4,3 |
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1089 uint8_t cond = CC_Z; |
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1090 switch (inst->reg) |
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1091 { |
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1092 case Z80_CC_NZ: |
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1093 cond = CC_NZ; |
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1094 case Z80_CC_Z: |
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1095 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_Z), SZ_B); |
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1096 break; |
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1097 case Z80_CC_NC: |
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1098 cond = CC_NZ; |
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1099 case Z80_CC_C: |
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1100 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_C), SZ_B); |
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1101 break; |
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1102 } |
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1103 uint8_t *no_jump_off = dst+1; |
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1104 dst = jcc(dst, cond, dst+2); |
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1105 dst = zcycles(dst, 5);//T States: 5 |
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1106 uint16_t dest_addr = address + inst->immed + 2; |
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1107 if (dest_addr < 0x4000) { |
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1108 uint8_t * call_dst = z80_get_native_address(context, dest_addr); |
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1109 if (!call_dst) { |
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1110 opts->deferred = defer_address(opts->deferred, dest_addr, dst + 1); |
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1111 //fake address to force large displacement |
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1112 call_dst = dst + 256; |
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1113 } |
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1114 dst = jmp(dst, call_dst); |
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1115 } else { |
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1116 dst = mov_ir(dst, dest_addr, SCRATCH1, SZ_W); |
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1117 dst = call(dst, (uint8_t *)z80_native_addr); |
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1118 dst = jmp_r(dst, SCRATCH1); |
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1119 } |
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1120 *no_jump_off = dst - (no_jump_off+1); |
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1121 break; |
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1122 } |
239
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1123 case Z80_DJNZ: |
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1124 dst = zcycles(dst, 8);//T States: 5,3 |
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1125 dst = sub_ir(dst, 1, opts->regs[Z80_B], SZ_B); |
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1126 uint8_t *no_jump_off = dst+1; |
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1127 dst = jcc(dst, CC_Z, dst+2); |
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1128 dst = zcycles(dst, 5);//T States: 5 |
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1129 uint16_t dest_addr = address + inst->immed + 2; |
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1130 if (dest_addr < 0x4000) { |
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1131 uint8_t * call_dst = z80_get_native_address(context, dest_addr); |
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1132 if (!call_dst) { |
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1133 opts->deferred = defer_address(opts->deferred, dest_addr, dst + 1); |
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1134 //fake address to force large displacement |
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1135 call_dst = dst + 256; |
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1136 } |
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1137 dst = jmp(dst, call_dst); |
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1138 } else { |
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1139 dst = mov_ir(dst, dest_addr, SCRATCH1, SZ_W); |
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1140 dst = call(dst, (uint8_t *)z80_native_addr); |
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1141 dst = jmp_r(dst, SCRATCH1); |
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1142 } |
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1143 *no_jump_off = dst - (no_jump_off+1); |
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|
1144 break; |
235
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1145 case Z80_CALL: { |
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1146 dst = zcycles(dst, 11);//T States: 4,3,4 |
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1147 dst = sub_ir(dst, 2, opts->regs[Z80_SP], SZ_W); |
253
3b34deba4ca0
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|
1148 dst = mov_ir(dst, address + 3, SCRATCH1, SZ_W); |
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1149 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH2, SZ_W); |
235
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1150 dst = call(dst, (uint8_t *)z80_write_word_highfirst);//T States: 3, 3 |
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1151 if (inst->immed < 0x4000) { |
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1152 uint8_t * call_dst = z80_get_native_address(context, inst->immed); |
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1153 if (!call_dst) { |
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1154 opts->deferred = defer_address(opts->deferred, inst->immed, dst + 1); |
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1155 //fake address to force large displacement |
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|
1156 call_dst = dst + 256; |
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|
1157 } |
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1158 dst = jmp(dst, call_dst); |
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1159 } else { |
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1160 dst = mov_ir(dst, inst->immed, SCRATCH1, SZ_W); |
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1161 dst = call(dst, (uint8_t *)z80_native_addr); |
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1162 dst = jmp_r(dst, SCRATCH1); |
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1163 } |
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1164 break; |
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|
1165 } |
238
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|
1166 case Z80_CALLCC: |
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1167 dst = zcycles(dst, 10);//T States: 4,3,3 (false case) |
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1168 uint8_t cond = CC_Z; |
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1169 switch (inst->reg) |
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1170 { |
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1171 case Z80_CC_NZ: |
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|
1172 cond = CC_NZ; |
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|
1173 case Z80_CC_Z: |
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|
1174 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_Z), SZ_B); |
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|
1175 break; |
827ebce557bf
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diff
changeset
|
1176 case Z80_CC_NC: |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1177 cond = CC_NZ; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1178 case Z80_CC_C: |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1179 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_C), SZ_B); |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1180 break; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1181 case Z80_CC_PO: |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1182 cond = CC_NZ; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1183 case Z80_CC_PE: |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1184 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_PV), SZ_B); |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1185 break; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1186 case Z80_CC_P: |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1187 case Z80_CC_M: |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1188 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_S), SZ_B); |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1189 break; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1190 } |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1191 uint8_t *no_call_off = dst+1; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1192 dst = jcc(dst, cond, dst+2); |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1193 dst = zcycles(dst, 1);//Last of the above T states takes an extra cycle in the true case |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1194 dst = sub_ir(dst, 2, opts->regs[Z80_SP], SZ_W); |
253
3b34deba4ca0
Squashing some bugs introduced when I switched the register assignments for z80_write_byte around.
Mike Pavone <pavone@retrodev.com>
parents:
252
diff
changeset
|
1195 dst = mov_ir(dst, address + 3, SCRATCH1, SZ_W); |
3b34deba4ca0
Squashing some bugs introduced when I switched the register assignments for z80_write_byte around.
Mike Pavone <pavone@retrodev.com>
parents:
252
diff
changeset
|
1196 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH2, SZ_W); |
238
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1197 dst = call(dst, (uint8_t *)z80_write_word_highfirst);//T States: 3, 3 |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1198 if (inst->immed < 0x4000) { |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1199 uint8_t * call_dst = z80_get_native_address(context, inst->immed); |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1200 if (!call_dst) { |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1201 opts->deferred = defer_address(opts->deferred, inst->immed, dst + 1); |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1202 //fake address to force large displacement |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1203 call_dst = dst + 256; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1204 } |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1205 dst = jmp(dst, call_dst); |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1206 } else { |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1207 dst = mov_ir(dst, inst->immed, SCRATCH1, SZ_W); |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1208 dst = call(dst, (uint8_t *)z80_native_addr); |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1209 dst = jmp_r(dst, SCRATCH1); |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1210 } |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1211 *no_call_off = dst - (no_call_off+1); |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1212 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1213 case Z80_RET: |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1214 dst = zcycles(dst, 4);//T States: 4 |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1215 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH1, SZ_W); |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1216 dst = call(dst, (uint8_t *)z80_read_word);//T STates: 3, 3 |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1217 dst = add_ir(dst, 2, opts->regs[Z80_SP], SZ_W); |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1218 dst = call(dst, (uint8_t *)z80_native_addr); |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1219 dst = jmp_r(dst, SCRATCH1); |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1220 break; |
246
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1221 case Z80_RETCC: { |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1222 dst = zcycles(dst, 5);//T States: 5 |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1223 uint8_t cond = CC_Z; |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1224 switch (inst->reg) |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1225 { |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1226 case Z80_CC_NZ: |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1227 cond = CC_NZ; |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1228 case Z80_CC_Z: |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1229 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_Z), SZ_B); |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1230 break; |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1231 case Z80_CC_NC: |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1232 cond = CC_NZ; |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1233 case Z80_CC_C: |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1234 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_C), SZ_B); |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1235 break; |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1236 case Z80_CC_PO: |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1237 cond = CC_NZ; |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1238 case Z80_CC_PE: |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1239 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_PV), SZ_B); |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1240 break; |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1241 case Z80_CC_P: |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1242 case Z80_CC_M: |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1243 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_S), SZ_B); |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1244 break; |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1245 } |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1246 uint8_t *no_call_off = dst+1; |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1247 dst = jcc(dst, cond, dst+2); |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1248 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH1, SZ_W); |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1249 dst = call(dst, (uint8_t *)z80_read_word);//T STates: 3, 3 |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1250 dst = add_ir(dst, 2, opts->regs[Z80_SP], SZ_W); |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1251 dst = call(dst, (uint8_t *)z80_native_addr); |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1252 dst = jmp_r(dst, SCRATCH1); |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1253 *no_call_off = dst - (no_call_off+1); |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1254 break; |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1255 } |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1256 /*case Z80_RETI: |
241
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1257 case Z80_RETN:*/ |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1258 case Z80_RST: { |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1259 //RST is basically CALL to an address in page 0 |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1260 dst = zcycles(dst, 5);//T States: 5 |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1261 dst = sub_ir(dst, 2, opts->regs[Z80_SP], SZ_W); |
253
3b34deba4ca0
Squashing some bugs introduced when I switched the register assignments for z80_write_byte around.
Mike Pavone <pavone@retrodev.com>
parents:
252
diff
changeset
|
1262 dst = mov_ir(dst, address + 3, SCRATCH1, SZ_W); |
3b34deba4ca0
Squashing some bugs introduced when I switched the register assignments for z80_write_byte around.
Mike Pavone <pavone@retrodev.com>
parents:
252
diff
changeset
|
1263 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH2, SZ_W); |
241
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1264 dst = call(dst, (uint8_t *)z80_write_word_highfirst);//T States: 3, 3 |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1265 uint8_t * call_dst = z80_get_native_address(context, inst->immed); |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1266 if (!call_dst) { |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1267 opts->deferred = defer_address(opts->deferred, inst->immed, dst + 1); |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1268 //fake address to force large displacement |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1269 call_dst = dst + 256; |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1270 } |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1271 dst = jmp(dst, call_dst); |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1272 break; |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1273 } |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1274 /*case Z80_IN: |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1275 case Z80_INI: |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1276 case Z80_INIR: |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1277 case Z80_IND: |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1278 case Z80_INDR: |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1279 case Z80_OUT: |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1280 case Z80_OUTI: |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1281 case Z80_OTIR: |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1282 case Z80_OUTD: |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1283 case Z80_OTDR:*/ |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1284 default: { |
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1285 char disbuf[80]; |
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1286 z80_disasm(inst, disbuf); |
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1287 fprintf(stderr, "unimplemented instruction: %s\n", disbuf); |
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1288 FILE * f = fopen("zram.bin", "wb"); |
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1289 fwrite(context->mem_pointers[0], 1, 8 * 1024, f); |
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1290 fclose(f); |
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1291 exit(1); |
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1292 } |
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1293 } |
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1294 return dst; |
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1295 } |
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1296 |
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1297 uint8_t * z80_get_native_address(z80_context * context, uint32_t address) |
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1298 { |
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1299 native_map_slot *map; |
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1300 if (address < 0x4000) { |
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1301 address &= 0x1FFF; |
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1302 map = context->static_code_map; |
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1303 } else if (address >= 0x8000) { |
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1304 address &= 0x7FFF; |
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1305 map = context->banked_code_map + (context->bank_reg << 15); |
235
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1306 } else { |
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1307 dprintf("z80_get_native_address: %X NULL\n", address); |
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1308 return NULL; |
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1309 } |
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1310 if (!map->base || !map->offsets || map->offsets[address] == INVALID_OFFSET || map->offsets[address] == EXTENSION_WORD) { |
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1311 dprintf("z80_get_native_address: %X NULL\n", address); |
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1312 return NULL; |
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1313 } |
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1314 dprintf("z80_get_native_address: %X %p\n", address, map->base + map->offsets[address]); |
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1315 return map->base + map->offsets[address]; |
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1316 } |
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1317 |
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1318 uint8_t z80_get_native_inst_size(x86_z80_options * opts, uint32_t address) |
235
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1319 { |
252
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1320 if (address >= 0x4000) { |
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1321 return 0; |
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1322 } |
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1323 return opts->ram_inst_sizes[address & 0x1FFF]; |
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1324 } |
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1325 |
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1326 void z80_map_native_address(z80_context * context, uint32_t address, uint8_t * native_address, uint8_t size, uint8_t native_size) |
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1327 { |
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1328 uint32_t orig_address = address; |
235
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1329 native_map_slot *map; |
252
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1330 x86_z80_options * opts = context->options; |
235
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1331 if (address < 0x4000) { |
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1332 address &= 0x1FFF; |
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1333 map = context->static_code_map; |
252
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1334 opts->ram_inst_sizes[address] = native_size; |
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1335 context->ram_code_flags[(address & 0x1C00) >> 10] |= 1 << ((address & 0x380) >> 7); |
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1336 context->ram_code_flags[((address + size) & 0x1C00) >> 10] |= 1 << (((address + size) & 0x380) >> 7); |
235
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1337 } else if (address >= 0x8000) { |
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1338 address &= 0x7FFF; |
252
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1339 map = context->banked_code_map + (context->bank_reg << 15); |
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1340 if (!map->offsets) { |
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1341 map->offsets = malloc(sizeof(int32_t) * 0x8000); |
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1342 memset(map->offsets, 0xFF, sizeof(int32_t) * 0x8000); |
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1343 } |
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1344 } else { |
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|
1345 return; |
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1346 } |
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1347 if (!map->base) { |
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1348 map->base = native_address; |
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1349 } |
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1350 map->offsets[address] = native_address - map->base; |
253
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1351 for(--size, orig_address++; size; --size, orig_address++) { |
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1352 address = orig_address; |
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1353 if (address < 0x4000) { |
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1354 address &= 0x1FFF; |
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1355 map = context->static_code_map; |
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1356 } else if (address >= 0x8000) { |
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1357 address &= 0x7FFF; |
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1358 map = context->banked_code_map + (context->bank_reg << 15); |
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1359 } else { |
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1360 return; |
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1361 } |
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1362 if (!map->offsets) { |
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1363 map->offsets = malloc(sizeof(int32_t) * 0x8000); |
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1364 memset(map->offsets, 0xFF, sizeof(int32_t) * 0x8000); |
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1365 } |
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1366 map->offsets[address] = EXTENSION_WORD; |
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1367 } |
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1368 } |
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1369 |
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1370 #define INVALID_INSTRUCTION_START 0xFEEDFEED |
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1371 |
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1372 uint32_t z80_get_instruction_start(native_map_slot * static_code_map, uint32_t address) |
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1373 { |
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1374 if (!static_code_map->base || address >= 0x4000) { |
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1375 return INVALID_INSTRUCTION_START; |
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1376 } |
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1377 address &= 0x1FFF; |
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1378 if (static_code_map->offsets[address] == INVALID_OFFSET) { |
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1379 return INVALID_INSTRUCTION_START; |
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1380 } |
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1381 while (static_code_map->offsets[address] == EXTENSION_WORD) { |
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1382 --address; |
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1383 address &= 0x1FFF; |
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1384 } |
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1385 return address; |
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1386 } |
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Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1387 |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1388 z80_context * z80_handle_code_write(uint32_t address, z80_context * context) |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1389 { |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1390 uint32_t inst_start = z80_get_instruction_start(context->static_code_map, address); |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1391 if (inst_start != INVALID_INSTRUCTION_START) { |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1392 uint8_t * dst = z80_get_native_address(context, inst_start); |
268
6c2d7e003a55
Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset
Mike Pavone <pavone@retrodev.com>
parents:
267
diff
changeset
|
1393 dprintf("patching code at %p for Z80 instruction at %X due to write to %X\n", dst, inst_start, address); |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1394 dst = mov_ir(dst, inst_start, SCRATCH1, SZ_D); |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1395 dst = jmp(dst, (uint8_t *)z80_retrans_stub); |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1396 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1397 return context; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1398 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1399 |
264
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1400 uint8_t * z80_get_native_address_trans(z80_context * context, uint32_t address) |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1401 { |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1402 uint8_t * addr = z80_get_native_address(context, address); |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1403 if (!addr) { |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1404 translate_z80_stream(context, address); |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1405 addr = z80_get_native_address(context, address); |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1406 if (!addr) { |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1407 printf("Failed to translate %X to native code\n", address); |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1408 } |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1409 } |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1410 return addr; |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1411 } |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1412 |
266
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1413 void z80_handle_deferred(z80_context * context) |
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1414 { |
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1415 x86_z80_options * opts = context->options; |
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1416 process_deferred(&opts->deferred, context, (native_addr_func)z80_get_native_address); |
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1417 if (opts->deferred) { |
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1418 translate_z80_stream(context, opts->deferred->address); |
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1419 } |
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1420 } |
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1421 |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1422 void * z80_retranslate_inst(uint32_t address, z80_context * context) |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1423 { |
266
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1424 char disbuf[80]; |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1425 x86_z80_options * opts = context->options; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1426 uint8_t orig_size = z80_get_native_inst_size(opts, address); |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1427 uint8_t * orig_start = z80_get_native_address(context, address); |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1428 uint32_t orig = address; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1429 address &= 0x1FFF; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1430 uint8_t * dst = opts->cur_code; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1431 uint8_t * dst_end = opts->code_end; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1432 uint8_t *after, *inst = context->mem_pointers[0] + address; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1433 z80inst instbuf; |
268
6c2d7e003a55
Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset
Mike Pavone <pavone@retrodev.com>
parents:
267
diff
changeset
|
1434 dprintf("Retranslating code at Z80 address %X, native address %p\n", address, orig_start); |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1435 after = z80_decode(inst, &instbuf); |
268
6c2d7e003a55
Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset
Mike Pavone <pavone@retrodev.com>
parents:
267
diff
changeset
|
1436 #ifdef DO_DEBUG_PRINT |
267
1788e3f29c28
Don't mix *H regs with the REX prefix
Mike Pavone <pavone@retrodev.com>
parents:
266
diff
changeset
|
1437 z80_disasm(&instbuf, disbuf); |
266
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1438 if (instbuf.op == Z80_NOP) { |
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1439 printf("%X\t%s(%d)\n", address, disbuf, instbuf.immed); |
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1440 } else { |
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1441 printf("%X\t%s\n", address, disbuf); |
267
1788e3f29c28
Don't mix *H regs with the REX prefix
Mike Pavone <pavone@retrodev.com>
parents:
266
diff
changeset
|
1442 } |
268
6c2d7e003a55
Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset
Mike Pavone <pavone@retrodev.com>
parents:
267
diff
changeset
|
1443 #endif |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1444 if (orig_size != ZMAX_NATIVE_SIZE) { |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1445 if (dst_end - dst < ZMAX_NATIVE_SIZE) { |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1446 size_t size = 1024*1024; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1447 dst = alloc_code(&size); |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1448 opts->code_end = dst_end = dst + size; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1449 opts->cur_code = dst; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1450 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1451 uint8_t * native_end = translate_z80inst(&instbuf, dst, context, address); |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1452 if ((native_end - dst) <= orig_size) { |
264
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1453 uint8_t * native_next = z80_get_native_address(context, address + after-inst); |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1454 if (native_next && ((native_next == orig_start + orig_size) || (orig_size - (native_end - dst)) > 5)) { |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1455 native_end = translate_z80inst(&instbuf, orig_start, context, address); |
266
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1456 if (native_next == orig_start + orig_size && (native_next-native_end) < 2) { |
264
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1457 while (native_end < orig_start + orig_size) { |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1458 *(native_end++) = 0x90; //NOP |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1459 } |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1460 } else { |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1461 jmp(native_end, native_next); |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1462 } |
266
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1463 z80_handle_deferred(context); |
264
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1464 return orig_start; |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1465 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1466 } |
264
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1467 z80_map_native_address(context, address, dst, after-inst, ZMAX_NATIVE_SIZE); |
266
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1468 opts->cur_code = dst+ZMAX_NATIVE_SIZE; |
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1469 jmp(orig_start, dst); |
264
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1470 if(!(instbuf.op == Z80_RET || instbuf.op == Z80_RETI || instbuf.op == Z80_RETN || instbuf.op == Z80_JP || (instbuf.op == Z80_NOP && instbuf.immed == 42))) { |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1471 jmp(native_end, z80_get_native_address_trans(context, address + after-inst)); |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1472 } |
266
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1473 z80_handle_deferred(context); |
264
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1474 return dst; |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1475 } else { |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1476 dst = translate_z80inst(&instbuf, orig_start, context, address); |
254
64feb6b67244
Fix bug in end condition inside translate_z80_stream.
Mike Pavone <pavone@retrodev.com>
parents:
253
diff
changeset
|
1477 if(!(instbuf.op == Z80_RET || instbuf.op == Z80_RETI || instbuf.op == Z80_RETN || instbuf.op == Z80_JP || (instbuf.op == Z80_NOP && instbuf.immed == 42))) { |
264
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1478 dst = jmp(dst, z80_get_native_address_trans(context, address + after-inst)); |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1479 } |
266
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1480 z80_handle_deferred(context); |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1481 return orig_start; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1482 } |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1483 } |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1484 |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1485 void translate_z80_stream(z80_context * context, uint32_t address) |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1486 { |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1487 char disbuf[80]; |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1488 if (z80_get_native_address(context, address)) { |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1489 return; |
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1490 } |
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|
1491 x86_z80_options * opts = context->options; |
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1492 uint8_t * encoded = NULL, *next; |
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1493 if (address < 0x4000) { |
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1494 encoded = context->mem_pointers[0] + (address & 0x1FFF); |
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1495 } else if(address >= 0x8000 && context->mem_pointers[1]) { |
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1496 encoded = context->mem_pointers[1] + (address & 0x7FFF); |
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|
1497 } |
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|
1498 while (encoded != NULL) |
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|
1499 { |
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|
1500 z80inst inst; |
268
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1501 dprintf("translating Z80 code at address %X\n", address); |
235
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1502 do { |
252
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|
1503 if (opts->code_end-opts->cur_code < ZMAX_NATIVE_SIZE) { |
235
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1504 if (opts->code_end-opts->cur_code < 5) { |
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|
1505 puts("out of code memory, not enough space for jmp to next chunk"); |
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|
1506 exit(1); |
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diff
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|
1507 } |
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|
1508 size_t size = 1024*1024; |
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1509 opts->cur_code = alloc_code(&size); |
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1510 opts->code_end = opts->cur_code + size; |
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1511 jmp(opts->cur_code, opts->cur_code); |
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|
1512 } |
255
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|
1513 if (address > 0x4000 && address < 0x8000) { |
235
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1514 opts->cur_code = xor_rr(opts->cur_code, RDI, RDI, SZ_D); |
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1515 opts->cur_code = call(opts->cur_code, (uint8_t *)exit); |
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|
1516 break; |
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|
1517 } |
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|
1518 uint8_t * existing = z80_get_native_address(context, address); |
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1519 if (existing) { |
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1520 opts->cur_code = jmp(opts->cur_code, existing); |
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|
1521 break; |
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diff
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|
1522 } |
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|
1523 next = z80_decode(encoded, &inst); |
268
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Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset
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|
1524 #ifdef DO_DEBUG_PRINT |
235
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1525 z80_disasm(&inst, disbuf); |
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|
1526 if (inst.op == Z80_NOP) { |
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1527 printf("%X\t%s(%d)\n", address, disbuf, inst.immed); |
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diff
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|
1528 } else { |
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Get Z80 core working for simple programs
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diff
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|
1529 printf("%X\t%s\n", address, disbuf); |
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diff
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|
1530 } |
268
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Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset
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diff
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|
1531 #endif |
248
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Implement ADC and SBC in Z80 core (untested)
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|
1532 uint8_t *after = translate_z80inst(&inst, opts->cur_code, context, address); |
252
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Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
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|
1533 z80_map_native_address(context, address, opts->cur_code, next-encoded, after - opts->cur_code); |
248
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Implement ADC and SBC in Z80 core (untested)
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|
1534 opts->cur_code = after; |
235
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1535 address += next-encoded; |
255
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Properly handle wrapping around to 0 in translate_z80_stream
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254
diff
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|
1536 if (address > 0xFFFF) { |
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Properly handle wrapping around to 0 in translate_z80_stream
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diff
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|
1537 address &= 0xFFFF; |
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Properly handle wrapping around to 0 in translate_z80_stream
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diff
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|
1538 |
572b935dd030
Properly handle wrapping around to 0 in translate_z80_stream
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diff
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|
1539 } else { |
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Properly handle wrapping around to 0 in translate_z80_stream
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254
diff
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|
1540 encoded = next; |
572b935dd030
Properly handle wrapping around to 0 in translate_z80_stream
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254
diff
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|
1541 } |
254
64feb6b67244
Fix bug in end condition inside translate_z80_stream.
Mike Pavone <pavone@retrodev.com>
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253
diff
changeset
|
1542 } while (!(inst.op == Z80_RET || inst.op == Z80_RETI || inst.op == Z80_RETN || inst.op == Z80_JP || (inst.op == Z80_NOP && inst.immed == 42))); |
235
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diff
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|
1543 process_deferred(&opts->deferred, context, (native_addr_func)z80_get_native_address); |
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Get Z80 core working for simple programs
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diff
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|
1544 if (opts->deferred) { |
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Get Z80 core working for simple programs
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diff
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|
1545 address = opts->deferred->address; |
268
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Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset
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267
diff
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|
1546 dprintf("defferred address: %X\n", address); |
235
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diff
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|
1547 if (address < 0x4000) { |
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Get Z80 core working for simple programs
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diff
changeset
|
1548 encoded = context->mem_pointers[0] + (address & 0x1FFF); |
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Get Z80 core working for simple programs
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diff
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|
1549 } else if (address > 0x8000 && context->mem_pointers[1]) { |
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Get Z80 core working for simple programs
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diff
changeset
|
1550 encoded = context->mem_pointers[1] + (address & 0x7FFF); |
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Get Z80 core working for simple programs
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213
diff
changeset
|
1551 } else { |
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Get Z80 core working for simple programs
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213
diff
changeset
|
1552 printf("attempt to translate non-memory address: %X\n", address); |
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Get Z80 core working for simple programs
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213
diff
changeset
|
1553 exit(1); |
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Get Z80 core working for simple programs
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213
diff
changeset
|
1554 } |
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Get Z80 core working for simple programs
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213
diff
changeset
|
1555 } else { |
d9bf8e61c33c
Get Z80 core working for simple programs
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213
diff
changeset
|
1556 encoded = NULL; |
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Get Z80 core working for simple programs
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213
diff
changeset
|
1557 } |
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213
diff
changeset
|
1558 } |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
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diff
changeset
|
1559 } |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
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diff
changeset
|
1560 |
235
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diff
changeset
|
1561 void init_x86_z80_opts(x86_z80_options * options) |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
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diff
changeset
|
1562 { |
235
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diff
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|
1563 options->flags = 0; |
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Get Z80 core working for simple programs
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diff
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|
1564 options->regs[Z80_B] = BH; |
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diff
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|
1565 options->regs[Z80_C] = RBX; |
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Get Z80 core working for simple programs
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diff
changeset
|
1566 options->regs[Z80_D] = CH; |
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Get Z80 core working for simple programs
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213
diff
changeset
|
1567 options->regs[Z80_E] = RCX; |
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Get Z80 core working for simple programs
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diff
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|
1568 options->regs[Z80_H] = AH; |
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Get Z80 core working for simple programs
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diff
changeset
|
1569 options->regs[Z80_L] = RAX; |
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diff
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|
1570 options->regs[Z80_IXH] = DH; |
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Get Z80 core working for simple programs
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diff
changeset
|
1571 options->regs[Z80_IXL] = RDX; |
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213
diff
changeset
|
1572 options->regs[Z80_IYH] = -1; |
239
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
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238
diff
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|
1573 options->regs[Z80_IYL] = R8; |
235
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|
1574 options->regs[Z80_I] = -1; |
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diff
changeset
|
1575 options->regs[Z80_R] = -1; |
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diff
changeset
|
1576 options->regs[Z80_A] = R10; |
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213
diff
changeset
|
1577 options->regs[Z80_BC] = RBX; |
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diff
changeset
|
1578 options->regs[Z80_DE] = RCX; |
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diff
changeset
|
1579 options->regs[Z80_HL] = RAX; |
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diff
changeset
|
1580 options->regs[Z80_SP] = R9; |
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diff
changeset
|
1581 options->regs[Z80_AF] = -1; |
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changeset
|
1582 options->regs[Z80_IX] = RDX; |
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|
1583 options->regs[Z80_IY] = R8; |
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diff
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|
1584 size_t size = 1024 * 1024; |
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changeset
|
1585 options->cur_code = alloc_code(&size); |
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diff
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|
1586 options->code_end = options->cur_code + size; |
252
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changeset
|
1587 options->ram_inst_sizes = malloc(sizeof(uint8_t) * 0x2000); |
63b9a500a00b
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|
1588 memset(options->ram_inst_sizes, 0, sizeof(uint8_t) * 0x2000); |
235
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|
1589 options->deferred = NULL; |
213
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changeset
|
1590 } |
235
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changeset
|
1591 |
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|
1592 void init_z80_context(z80_context * context, x86_z80_options * options) |
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changeset
|
1593 { |
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changeset
|
1594 memset(context, 0, sizeof(*context)); |
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|
1595 context->static_code_map = malloc(sizeof(context->static_code_map)); |
259
d9417261366f
Fix a remaining z80_write reg swap bug. Properly initialize the native map slots. Reset appropriate regs when z80_reset is called.
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|
1596 context->static_code_map->base = NULL; |
235
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|
1597 context->static_code_map->offsets = malloc(sizeof(int32_t) * 0x2000); |
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changeset
|
1598 memset(context->static_code_map->offsets, 0xFF, sizeof(int32_t) * 0x2000); |
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changeset
|
1599 context->banked_code_map = malloc(sizeof(native_map_slot) * (1 << 9)); |
259
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Fix a remaining z80_write reg swap bug. Properly initialize the native map slots. Reset appropriate regs when z80_reset is called.
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1600 memset(context->banked_code_map, 0, sizeof(native_map_slot) * (1 << 9)); |
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1601 context->options = options; |
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1602 } |
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1603 |
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1604 void z80_reset(z80_context * context) |
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1605 { |
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Fix a remaining z80_write reg swap bug. Properly initialize the native map slots. Reset appropriate regs when z80_reset is called.
Mike Pavone <pavone@retrodev.com>
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1606 context->im = 0; |
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Fix a remaining z80_write reg swap bug. Properly initialize the native map slots. Reset appropriate regs when z80_reset is called.
Mike Pavone <pavone@retrodev.com>
parents:
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1607 context->iff1 = context->iff2 = 0; |
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1608 context->native_pc = z80_get_native_address_trans(context, 0); |
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1609 context->extra_pc = NULL; |
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1610 } |
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Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
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1611 |
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Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
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1612 |