repos/blastem: z80_to_x86.c annotate

annotate z80_to_x86.c @ 272:9b04b57434b5

Implement LDI

author	Mike Pavone <pavone@retrodev.com>
date	Thu, 02 May 2013 22:26:47 -0700
parents	3c054d977175
children	719b9fea2fe9

rev	line source
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1 #include "z80inst.h"
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	2 #include "z80_to_x86.h"
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	3 #include "gen_x86.h"
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	4 #include "mem.h"
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	5 #include <stdio.h>
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	6 #include <stdlib.h>
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	7 #include <stddef.h>
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	8 #include <string.h>
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	9
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	10 #define MODE_UNUSED (MODE_IMMED-1)
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	11
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	12 #define ZCYCLES RBP
250 5f1b68cecfc7 Implemented basic interrupt support in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 248 diff changeset	13 #define ZLIMIT RDI
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	14 #define SCRATCH1 R13
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	15 #define SCRATCH2 R14
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	16 #define CONTEXT RSI
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	17
268 6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	18 #ifdef DO_DEBUG_PRINT
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	19 #define dprintf printf
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	20 #else
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	21 #define dprintf
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	22 #endif
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	23
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	24 void z80_read_byte();
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	25 void z80_read_word();
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	26 void z80_write_byte();
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	27 void z80_write_word_highfirst();
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	28 void z80_write_word_lowfirst();
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	29 void z80_save_context();
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	30 void z80_native_addr();
250 5f1b68cecfc7 Implemented basic interrupt support in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 248 diff changeset	31 void z80_do_sync();
5f1b68cecfc7 Implemented basic interrupt support in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 248 diff changeset	32 void z80_handle_cycle_limit_int();
252 63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	33 void z80_retrans_stub();
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	34
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	35 uint8_t z80_size(z80inst * inst)
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	36 {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	37 uint8_t reg = (inst->reg & 0x1F);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	38 if (reg != Z80_UNUSED && reg != Z80_USE_IMMED) {
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	39 return reg < Z80_BC ? SZ_B : SZ_W;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	40 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	41 //TODO: Handle any necessary special cases
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	42 return SZ_B;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	43 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	44
241 2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	45 uint8_t z80_high_reg(uint8_t reg)
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	46 {
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	47 switch(reg)
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	48 {
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	49 case Z80_C:
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	50 case Z80_BC:
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	51 return Z80_B;
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	52 case Z80_E:
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	53 case Z80_DE:
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	54 return Z80_D;
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	55 case Z80_L:
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	56 case Z80_HL:
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	57 return Z80_H;
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	58 case Z80_IXL:
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	59 case Z80_IX:
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	60 return Z80_IXH;
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	61 case Z80_IYL:
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	62 case Z80_IY:
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	63 return Z80_IYH;
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	64 default:
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	65 return Z80_UNUSED;
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	66 }
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	67 }
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	68
267 1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	69 uint8_t z80_low_reg(uint8_t reg)
1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	70 {
1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	71 switch(reg)
1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	72 {
1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	73 case Z80_B:
1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	74 case Z80_BC:
1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	75 return Z80_C;
1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	76 case Z80_D:
1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	77 case Z80_DE:
1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	78 return Z80_E;
1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	79 case Z80_H:
1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	80 case Z80_HL:
1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	81 return Z80_L;
1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	82 case Z80_IXH:
1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	83 case Z80_IX:
1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	84 return Z80_IXL;
1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	85 case Z80_IYH:
1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	86 case Z80_IY:
1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	87 return Z80_IYL;
1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	88 default:
1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	89 return Z80_UNUSED;
1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	90 }
1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	91 }
1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	92
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	93 uint8_t * zcycles(uint8_t * dst, uint32_t num_cycles)
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	94 {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	95 return add_ir(dst, num_cycles, ZCYCLES, SZ_D);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	96 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	97
250 5f1b68cecfc7 Implemented basic interrupt support in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 248 diff changeset	98 uint8_t * z80_check_cycles_int(uint8_t * dst, uint16_t address)
5f1b68cecfc7 Implemented basic interrupt support in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 248 diff changeset	99 {
5f1b68cecfc7 Implemented basic interrupt support in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 248 diff changeset	100 dst = cmp_rr(dst, ZCYCLES, ZLIMIT, SZ_D);
5f1b68cecfc7 Implemented basic interrupt support in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 248 diff changeset	101 uint8_t * jmp_off = dst+1;
5f1b68cecfc7 Implemented basic interrupt support in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 248 diff changeset	102 dst = jcc(dst, CC_NC, dst + 7);
259 d9417261366f Fix a remaining z80_write reg swap bug. Properly initialize the native map slots. Reset appropriate regs when z80_reset is called. Mike Pavone <pavone@retrodev.com> parents: 257 diff changeset	103 dst = mov_ir(dst, address, SCRATCH1, SZ_W);
250 5f1b68cecfc7 Implemented basic interrupt support in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 248 diff changeset	104 dst = call(dst, (uint8_t *)z80_handle_cycle_limit_int);
5f1b68cecfc7 Implemented basic interrupt support in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 248 diff changeset	105 *jmp_off = dst - (jmp_off+1);
5f1b68cecfc7 Implemented basic interrupt support in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 248 diff changeset	106 return dst;
5f1b68cecfc7 Implemented basic interrupt support in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 248 diff changeset	107 }
5f1b68cecfc7 Implemented basic interrupt support in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 248 diff changeset	108
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	109 uint8_t * translate_z80_reg(z80inst * inst, x86_ea * ea, uint8_t * dst, x86_z80_options * opts)
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	110 {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	111 if (inst->reg == Z80_USE_IMMED) {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	112 ea->mode = MODE_IMMED;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	113 ea->disp = inst->immed;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	114 } else if ((inst->reg & 0x1F) == Z80_UNUSED) {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	115 ea->mode = MODE_UNUSED;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	116 } else {
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	117 ea->mode = MODE_REG_DIRECT;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	118 if (inst->reg == Z80_IYH) {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	119 ea->base = opts->regs[Z80_IYL];
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	120 dst = ror_ir(dst, 8, opts->regs[Z80_IY], SZ_W);
262 d97c9eca49f4 Implement ld to and from the I and R registers Mike Pavone <pavone@retrodev.com> parents: 261 diff changeset	121 } else if(opts->regs[inst->reg] >= 0) {
d97c9eca49f4 Implement ld to and from the I and R registers Mike Pavone <pavone@retrodev.com> parents: 261 diff changeset	122 ea->base = opts->regs[inst->reg];
268 6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	123 if (ea->base >= AH && ea->base <= BH) {
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	124 if ((inst->addr_mode & 0x1F) == Z80_REG) {
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	125 uint8_t other_reg = opts->regs[inst->ea_reg];
269 3c054d977175 Fix IX/IY displace modes. Fix check for registers requiring REX. Mike Pavone <pavone@retrodev.com> parents: 268 diff changeset	126 if (other_reg >= R8 \|\| (other_reg >= RSP && other_reg <= RDI)) {
268 6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	127 //we can't mix an *H reg with a register that requires the REX prefix
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	128 ea->base = opts->regs[z80_low_reg(inst->reg)];
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	129 dst = ror_ir(dst, 8, ea->base, SZ_W);
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	130 }
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	131 } else if((inst->addr_mode & 0x1F) != Z80_UNUSED && (inst->addr_mode & 0x1F) != Z80_IMMED) {
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	132 //temp regs require REX prefix too
267 1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	133 ea->base = opts->regs[z80_low_reg(inst->reg)];
1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	134 dst = ror_ir(dst, 8, ea->base, SZ_W);
1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	135 }
1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	136 }
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	137 } else {
262 d97c9eca49f4 Implement ld to and from the I and R registers Mike Pavone <pavone@retrodev.com> parents: 261 diff changeset	138 ea->mode = MODE_REG_DISPLACE8;
d97c9eca49f4 Implement ld to and from the I and R registers Mike Pavone <pavone@retrodev.com> parents: 261 diff changeset	139 ea->base = CONTEXT;
d97c9eca49f4 Implement ld to and from the I and R registers Mike Pavone <pavone@retrodev.com> parents: 261 diff changeset	140 ea->disp = offsetof(z80_context, regs) + inst->reg;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	141 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	142 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	143 return dst;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	144 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	145
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	146 uint8_t * z80_save_reg(uint8_t * dst, z80inst * inst, x86_z80_options * opts)
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	147 {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	148 if (inst->reg == Z80_IYH) {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	149 dst = ror_ir(dst, 8, opts->regs[Z80_IY], SZ_W);
268 6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	150 } else if (opts->regs[inst->reg] >= AH && opts->regs[inst->reg] <= BH) {
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	151 if ((inst->addr_mode & 0x1F) == Z80_REG) {
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	152 uint8_t other_reg = opts->regs[inst->ea_reg];
269 3c054d977175 Fix IX/IY displace modes. Fix check for registers requiring REX. Mike Pavone <pavone@retrodev.com> parents: 268 diff changeset	153 if (other_reg >= R8 \|\| (other_reg >= RSP && other_reg <= RDI)) {
268 6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	154 //we can't mix an *H reg with a register that requires the REX prefix
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	155 dst = ror_ir(dst, 8, opts->regs[z80_low_reg(inst->reg)], SZ_W);
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	156 }
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	157 } else if((inst->addr_mode & 0x1F) != Z80_UNUSED && (inst->addr_mode & 0x1F) != Z80_IMMED) {
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	158 //temp regs require REX prefix too
267 1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	159 dst = ror_ir(dst, 8, opts->regs[z80_low_reg(inst->reg)], SZ_W);
1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	160 }
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	161 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	162 return dst;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	163 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	164
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	165 uint8_t * translate_z80_ea(z80inst * inst, x86_ea * ea, uint8_t * dst, x86_z80_options * opts, uint8_t read, uint8_t modify)
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	166 {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	167 uint8_t size, reg, areg;
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	168 ea->mode = MODE_REG_DIRECT;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	169 areg = read ? SCRATCH1 : SCRATCH2;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	170 switch(inst->addr_mode & 0x1F)
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	171 {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	172 case Z80_REG:
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	173 if (inst->ea_reg == Z80_IYH) {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	174 ea->base = opts->regs[Z80_IYL];
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	175 dst = ror_ir(dst, 8, opts->regs[Z80_IY], SZ_W);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	176 } else {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	177 ea->base = opts->regs[inst->ea_reg];
267 1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	178 if (ea->base >= AH && ea->base <= BH && inst->reg != Z80_UNUSED && inst->reg != Z80_USE_IMMED) {
1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	179 uint8_t other_reg = opts->regs[inst->reg];
269 3c054d977175 Fix IX/IY displace modes. Fix check for registers requiring REX. Mike Pavone <pavone@retrodev.com> parents: 268 diff changeset	180 if (other_reg >= R8 \|\| (other_reg >= RSP && other_reg <= RDI)) {
267 1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	181 //we can't mix an *H reg with a register that requires the REX prefix
1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	182 ea->base = opts->regs[z80_low_reg(inst->ea_reg)];
1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	183 dst = ror_ir(dst, 8, ea->base, SZ_W);
1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	184 }
1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	185 }
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	186 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	187 break;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	188 case Z80_REG_INDIRECT:
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	189 dst = mov_rr(dst, opts->regs[inst->ea_reg], areg, SZ_W);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	190 size = z80_size(inst);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	191 if (read) {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	192 if (modify) {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	193 dst = push_r(dst, SCRATCH1);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	194 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	195 if (size == SZ_B) {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	196 dst = call(dst, (uint8_t *)z80_read_byte);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	197 } else {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	198 dst = call(dst, (uint8_t *)z80_read_word);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	199 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	200 if (modify) {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	201 dst = pop_r(dst, SCRATCH2);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	202 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	203 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	204 ea->base = SCRATCH1;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	205 break;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	206 case Z80_IMMED:
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	207 ea->mode = MODE_IMMED;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	208 ea->disp = inst->immed;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	209 break;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	210 case Z80_IMMED_INDIRECT:
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	211 dst = mov_ir(dst, inst->immed, areg, SZ_W);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	212 size = z80_size(inst);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	213 if (read) {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	214 if (modify) {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	215 dst = push_r(dst, SCRATCH1);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	216 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	217 if (size == SZ_B) {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	218 dst = call(dst, (uint8_t *)z80_read_byte);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	219 } else {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	220 dst = call(dst, (uint8_t *)z80_read_word);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	221 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	222 if (modify) {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	223 dst = pop_r(dst, SCRATCH2);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	224 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	225 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	226 ea->base = SCRATCH1;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	227 break;
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	228 case Z80_IX_DISPLACE:
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	229 case Z80_IY_DISPLACE:
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	230 reg = opts->regs[inst->addr_mode == Z80_IX_DISPLACE ? Z80_IX : Z80_IY];
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	231 dst = mov_rr(dst, reg, areg, SZ_W);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	232 dst = add_ir(dst, inst->immed, areg, SZ_W);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	233 size = z80_size(inst);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	234 if (read) {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	235 if (modify) {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	236 dst = push_r(dst, SCRATCH1);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	237 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	238 if (size == SZ_B) {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	239 dst = call(dst, (uint8_t *)z80_read_byte);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	240 } else {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	241 dst = call(dst, (uint8_t *)z80_read_word);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	242 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	243 if (modify) {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	244 dst = pop_r(dst, SCRATCH2);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	245 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	246 }
269 3c054d977175 Fix IX/IY displace modes. Fix check for registers requiring REX. Mike Pavone <pavone@retrodev.com> parents: 268 diff changeset	247 ea->base = SCRATCH1;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	248 break;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	249 case Z80_UNUSED:
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	250 ea->mode = MODE_UNUSED;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	251 break;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	252 default:
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	253 fprintf(stderr, "Unrecognized Z80 addressing mode %d\n", inst->addr_mode);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	254 exit(1);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	255 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	256 return dst;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	257 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	258
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	259 uint8_t * z80_save_ea(uint8_t * dst, z80inst * inst, x86_z80_options * opts)
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	260 {
267 1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	261 if ((inst->addr_mode & 0x1F) == Z80_REG) {
1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	262 if (inst->ea_reg == Z80_IYH) {
1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	263 dst = ror_ir(dst, 8, opts->regs[Z80_IY], SZ_W);
1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	264 } else if (inst->reg != Z80_UNUSED && inst->reg != Z80_USE_IMMED && opts->regs[inst->ea_reg] >= AH && opts->regs[inst->ea_reg] <= BH) {
1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	265 uint8_t other_reg = opts->regs[inst->reg];
269 3c054d977175 Fix IX/IY displace modes. Fix check for registers requiring REX. Mike Pavone <pavone@retrodev.com> parents: 268 diff changeset	266 if (other_reg >= R8 \|\| (other_reg >= RSP && other_reg <= RDI)) {
267 1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	267 //we can't mix an *H reg with a register that requires the REX prefix
1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	268 dst = ror_ir(dst, 8, opts->regs[z80_low_reg(inst->ea_reg)], SZ_W);
1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	269 }
1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	270 }
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	271 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	272 return dst;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	273 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	274
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	275 uint8_t * z80_save_result(uint8_t * dst, z80inst * inst)
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	276 {
253 3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around. Mike Pavone <pavone@retrodev.com> parents: 252 diff changeset	277 switch(inst->addr_mode & 0x1f)
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around. Mike Pavone <pavone@retrodev.com> parents: 252 diff changeset	278 {
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around. Mike Pavone <pavone@retrodev.com> parents: 252 diff changeset	279 case Z80_REG_INDIRECT:
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around. Mike Pavone <pavone@retrodev.com> parents: 252 diff changeset	280 case Z80_IMMED_INDIRECT:
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around. Mike Pavone <pavone@retrodev.com> parents: 252 diff changeset	281 case Z80_IX_DISPLACE:
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around. Mike Pavone <pavone@retrodev.com> parents: 252 diff changeset	282 case Z80_IY_DISPLACE:
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around. Mike Pavone <pavone@retrodev.com> parents: 252 diff changeset	283 if (z80_size(inst) == SZ_B) {
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around. Mike Pavone <pavone@retrodev.com> parents: 252 diff changeset	284 dst = call(dst, (uint8_t *)z80_write_byte);
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around. Mike Pavone <pavone@retrodev.com> parents: 252 diff changeset	285 } else {
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around. Mike Pavone <pavone@retrodev.com> parents: 252 diff changeset	286 dst = call(dst, (uint8_t *)z80_write_word_lowfirst);
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around. Mike Pavone <pavone@retrodev.com> parents: 252 diff changeset	287 }
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	288 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	289 return dst;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	290 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	291
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	292 enum {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	293 DONT_READ=0,
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	294 READ
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	295 };
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	296
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	297 enum {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	298 DONT_MODIFY=0,
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	299 MODIFY
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	300 };
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	301
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	302 uint8_t zf_off(uint8_t flag)
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	303 {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	304 return offsetof(z80_context, flags) + flag;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	305 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	306
241 2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	307 uint8_t zaf_off(uint8_t flag)
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	308 {
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	309 return offsetof(z80_context, alt_flags) + flag;
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	310 }
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	311
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	312 uint8_t zar_off(uint8_t reg)
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	313 {
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	314 return offsetof(z80_context, alt_regs) + reg;
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	315 }
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	316
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	317 void z80_print_regs_exit(z80_context * context)
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	318 {
243 2f069a0b487e Implement EI, DI and IM in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 242 diff changeset	319 printf("A: %X\nB: %X\nC: %X\nD: %X\nE: %X\nHL: %X\nIX: %X\nIY: %X\nSP: %X\n\nIM: %d, IFF1: %d, IFF2: %d\n",
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	320 context->regs[Z80_A], context->regs[Z80_B], context->regs[Z80_C],
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	321 context->regs[Z80_D], context->regs[Z80_E],
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	322 (context->regs[Z80_H] << 8) \| context->regs[Z80_L],
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	323 (context->regs[Z80_IXH] << 8) \| context->regs[Z80_IXL],
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	324 (context->regs[Z80_IYH] << 8) \| context->regs[Z80_IYL],
243 2f069a0b487e Implement EI, DI and IM in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 242 diff changeset	325 context->sp, context->im, context->iff1, context->iff2);
241 2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	326 puts("--Alternate Regs--");
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	327 printf("A: %X\nB: %X\nC: %X\nD: %X\nE: %X\nHL: %X\nIX: %X\nIY: %X\n",
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	328 context->alt_regs[Z80_A], context->alt_regs[Z80_B], context->alt_regs[Z80_C],
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	329 context->alt_regs[Z80_D], context->alt_regs[Z80_E],
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	330 (context->alt_regs[Z80_H] << 8) \| context->alt_regs[Z80_L],
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	331 (context->alt_regs[Z80_IXH] << 8) \| context->alt_regs[Z80_IXL],
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	332 (context->alt_regs[Z80_IYH] << 8) \| context->alt_regs[Z80_IYL]);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	333 exit(0);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	334 }
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	335
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	336 uint8_t * translate_z80inst(z80inst * inst, uint8_t * dst, z80_context * context, uint16_t address)
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	337 {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	338 uint32_t cycles;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	339 x86_ea src_op, dst_op;
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	340 uint8_t size;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	341 x86_z80_options *opts = context->options;
261 f0c53a4bbfa3 Implement LDIR and fix a bug in which context was not restored after a call to z80_handle_code_write Mike Pavone <pavone@retrodev.com> parents: 259 diff changeset	342 uint8_t * start = dst;
250 5f1b68cecfc7 Implemented basic interrupt support in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 248 diff changeset	343 dst = z80_check_cycles_int(dst, address);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	344 switch(inst->op)
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	345 {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	346 case Z80_LD:
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	347 size = z80_size(inst);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	348 switch (inst->addr_mode & 0x1F)
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	349 {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	350 case Z80_REG:
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	351 case Z80_REG_INDIRECT:
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	352 cycles = size == SZ_B ? 4 : 6;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	353 if (inst->ea_reg == Z80_IX \|\| inst->ea_reg == Z80_IY) {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	354 cycles += 4;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	355 }
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	356 break;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	357 case Z80_IMMED:
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	358 cycles = size == SZ_B ? 7 : 10;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	359 break;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	360 case Z80_IMMED_INDIRECT:
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	361 cycles = 10;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	362 break;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	363 case Z80_IX_DISPLACE:
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	364 case Z80_IY_DISPLACE:
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	365 cycles = 12;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	366 break;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	367 }
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	368 if ((inst->reg >= Z80_IXL && inst->reg <= Z80_IYH) \|\| inst->reg == Z80_IX \|\| inst->reg == Z80_IY) {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	369 cycles += 4;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	370 }
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	371 dst = zcycles(dst, cycles);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	372 if (inst->addr_mode & Z80_DIR) {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	373 dst = translate_z80_reg(inst, &src_op, dst, opts);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	374 dst = translate_z80_ea(inst, &dst_op, dst, opts, DONT_READ, MODIFY);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	375 } else {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	376 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	377 dst = translate_z80_reg(inst, &dst_op, dst, opts);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	378 }
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	379 if (src_op.mode == MODE_REG_DIRECT) {
262 d97c9eca49f4 Implement ld to and from the I and R registers Mike Pavone <pavone@retrodev.com> parents: 261 diff changeset	380 if(dst_op.mode == MODE_REG_DISPLACE8) {
d97c9eca49f4 Implement ld to and from the I and R registers Mike Pavone <pavone@retrodev.com> parents: 261 diff changeset	381 dst = mov_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, size);
d97c9eca49f4 Implement ld to and from the I and R registers Mike Pavone <pavone@retrodev.com> parents: 261 diff changeset	382 } else {
d97c9eca49f4 Implement ld to and from the I and R registers Mike Pavone <pavone@retrodev.com> parents: 261 diff changeset	383 dst = mov_rr(dst, src_op.base, dst_op.base, size);
d97c9eca49f4 Implement ld to and from the I and R registers Mike Pavone <pavone@retrodev.com> parents: 261 diff changeset	384 }
d97c9eca49f4 Implement ld to and from the I and R registers Mike Pavone <pavone@retrodev.com> parents: 261 diff changeset	385 } else if(src_op.mode == MODE_IMMED) {
d97c9eca49f4 Implement ld to and from the I and R registers Mike Pavone <pavone@retrodev.com> parents: 261 diff changeset	386 dst = mov_ir(dst, src_op.disp, dst_op.base, size);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	387 } else {
262 d97c9eca49f4 Implement ld to and from the I and R registers Mike Pavone <pavone@retrodev.com> parents: 261 diff changeset	388 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, size);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	389 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	390 dst = z80_save_reg(dst, inst, opts);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	391 dst = z80_save_ea(dst, inst, opts);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	392 if (inst->addr_mode & Z80_DIR) {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	393 dst = z80_save_result(dst, inst);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	394 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	395 break;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	396 case Z80_PUSH:
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	397 dst = zcycles(dst, (inst->reg == Z80_IX \|\| inst->reg == Z80_IY) ? 9 : 5);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	398 dst = sub_ir(dst, 2, opts->regs[Z80_SP], SZ_W);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	399 if (inst->reg == Z80_AF) {
253 3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around. Mike Pavone <pavone@retrodev.com> parents: 252 diff changeset	400 dst = mov_rdisp8r(dst, CONTEXT, zf_off(ZF_S), SCRATCH1, SZ_B);
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around. Mike Pavone <pavone@retrodev.com> parents: 252 diff changeset	401 dst = shl_ir(dst, 1, SCRATCH1, SZ_B);
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around. Mike Pavone <pavone@retrodev.com> parents: 252 diff changeset	402 dst = or_rdisp8r(dst, CONTEXT, zf_off(ZF_Z), SCRATCH1, SZ_B);
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around. Mike Pavone <pavone@retrodev.com> parents: 252 diff changeset	403 dst = shl_ir(dst, 2, SCRATCH1, SZ_B);
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around. Mike Pavone <pavone@retrodev.com> parents: 252 diff changeset	404 dst = or_rdisp8r(dst, CONTEXT, zf_off(ZF_H), SCRATCH1, SZ_B);
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around. Mike Pavone <pavone@retrodev.com> parents: 252 diff changeset	405 dst = shl_ir(dst, 2, SCRATCH1, SZ_B);
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around. Mike Pavone <pavone@retrodev.com> parents: 252 diff changeset	406 dst = or_rdisp8r(dst, CONTEXT, zf_off(ZF_PV), SCRATCH1, SZ_B);
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around. Mike Pavone <pavone@retrodev.com> parents: 252 diff changeset	407 dst = shl_ir(dst, 1, SCRATCH1, SZ_B);
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around. Mike Pavone <pavone@retrodev.com> parents: 252 diff changeset	408 dst = or_rdisp8r(dst, CONTEXT, zf_off(ZF_N), SCRATCH1, SZ_B);
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around. Mike Pavone <pavone@retrodev.com> parents: 252 diff changeset	409 dst = shl_ir(dst, 1, SCRATCH1, SZ_B);
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around. Mike Pavone <pavone@retrodev.com> parents: 252 diff changeset	410 dst = or_rdisp8r(dst, CONTEXT, zf_off(ZF_C), SCRATCH1, SZ_B);
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around. Mike Pavone <pavone@retrodev.com> parents: 252 diff changeset	411 dst = shl_ir(dst, 8, SCRATCH1, SZ_W);
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around. Mike Pavone <pavone@retrodev.com> parents: 252 diff changeset	412 dst = mov_rr(dst, opts->regs[Z80_A], SCRATCH1, SZ_B);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	413 } else {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	414 dst = translate_z80_reg(inst, &src_op, dst, opts);
253 3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around. Mike Pavone <pavone@retrodev.com> parents: 252 diff changeset	415 dst = mov_rr(dst, src_op.base, SCRATCH1, SZ_W);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	416 }
253 3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around. Mike Pavone <pavone@retrodev.com> parents: 252 diff changeset	417 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH2, SZ_W);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	418 dst = call(dst, (uint8_t *)z80_write_word_highfirst);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	419 //no call to save_z80_reg needed since there's no chance we'll use the only
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	420 //the upper half of a register pair
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	421 break;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	422 case Z80_POP:
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	423 dst = zcycles(dst, (inst->reg == Z80_IX \|\| inst->reg == Z80_IY) ? 8 : 4);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	424 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH1, SZ_W);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	425 dst = call(dst, (uint8_t *)z80_read_word);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	426 dst = add_ir(dst, 2, opts->regs[Z80_SP], SZ_W);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	427 if (inst->reg == Z80_AF) {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	428 dst = mov_rr(dst, SCRATCH1, opts->regs[Z80_A], SZ_B);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	429 dst = bt_ir(dst, 8, SCRATCH1, SZ_W);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	430 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C));
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	431 dst = bt_ir(dst, 9, SCRATCH1, SZ_W);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	432 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_N));
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	433 dst = bt_ir(dst, 10, SCRATCH1, SZ_W);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	434 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_PV));
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	435 dst = bt_ir(dst, 12, SCRATCH1, SZ_W);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	436 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_H));
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	437 dst = bt_ir(dst, 14, SCRATCH1, SZ_W);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	438 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_Z));
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	439 dst = bt_ir(dst, 15, SCRATCH1, SZ_W);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	440 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_S));
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	441 } else {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	442 dst = translate_z80_reg(inst, &src_op, dst, opts);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	443 dst = mov_rr(dst, SCRATCH1, src_op.base, SZ_W);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	444 }
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	445 //no call to save_z80_reg needed since there's no chance we'll use the only
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	446 //the upper half of a register pair
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	447 break;
241 2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	448 case Z80_EX:
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	449 if (inst->addr_mode == Z80_REG \|\| inst->reg == Z80_HL) {
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	450 cycles = 4;
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	451 } else {
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	452 cycles = 8;
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	453 }
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	454 dst = zcycles(dst, cycles);
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	455 if (inst->addr_mode == Z80_REG) {
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	456 if(inst->reg == Z80_AF) {
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	457 dst = mov_rr(dst, opts->regs[Z80_A], SCRATCH1, SZ_B);
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	458 dst = mov_rdisp8r(dst, CONTEXT, zar_off(Z80_A), opts->regs[Z80_A], SZ_B);
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	459 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, zar_off(Z80_A), SZ_B);
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	460
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	461 //Flags are currently word aligned, so we can move
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	462 //them efficiently a word at a time
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	463 for (int f = ZF_C; f < ZF_NUM; f+=2) {
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	464 dst = mov_rdisp8r(dst, CONTEXT, zf_off(f), SCRATCH1, SZ_W);
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	465 dst = mov_rdisp8r(dst, CONTEXT, zaf_off(f), SCRATCH2, SZ_W);
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	466 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, zaf_off(f), SZ_W);
253 3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around. Mike Pavone <pavone@retrodev.com> parents: 252 diff changeset	467 dst = mov_rrdisp8(dst, SCRATCH2, CONTEXT, zf_off(f), SZ_W);
241 2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	468 }
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	469 } else {
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	470 dst = xchg_rr(dst, opts->regs[Z80_DE], opts->regs[Z80_HL], SZ_W);
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	471 }
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	472 } else {
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	473 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH1, SZ_W);
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	474 dst = call(dst, (uint8_t *)z80_read_byte);
253 3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around. Mike Pavone <pavone@retrodev.com> parents: 252 diff changeset	475 dst = xchg_rr(dst, opts->regs[inst->reg], SCRATCH1, SZ_B);
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around. Mike Pavone <pavone@retrodev.com> parents: 252 diff changeset	476 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH2, SZ_W);
241 2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	477 dst = call(dst, (uint8_t *)z80_write_byte);
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	478 dst = zcycles(dst, 1);
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	479 uint8_t high_reg = z80_high_reg(inst->reg);
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	480 uint8_t use_reg;
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	481 //even though some of the upper halves can be used directly
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	482 //the limitations on mixing *H regs with the REX prefix
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	483 //prevent us from taking advantage of it
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	484 use_reg = opts->regs[inst->reg];
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	485 dst = ror_ir(dst, 8, use_reg, SZ_W);
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	486 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH1, SZ_W);
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	487 dst = add_ir(dst, 1, SCRATCH1, SZ_W);
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	488 dst = call(dst, (uint8_t *)z80_read_byte);
253 3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around. Mike Pavone <pavone@retrodev.com> parents: 252 diff changeset	489 dst = xchg_rr(dst, use_reg, SCRATCH1, SZ_B);
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around. Mike Pavone <pavone@retrodev.com> parents: 252 diff changeset	490 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH2, SZ_W);
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around. Mike Pavone <pavone@retrodev.com> parents: 252 diff changeset	491 dst = add_ir(dst, 1, SCRATCH2, SZ_W);
241 2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	492 dst = call(dst, (uint8_t *)z80_write_byte);
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	493 //restore reg to normal rotation
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	494 dst = ror_ir(dst, 8, use_reg, SZ_W);
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	495 dst = zcycles(dst, 2);
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	496 }
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	497 break;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	498 case Z80_EXX:
241 2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	499 dst = zcycles(dst, 4);
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	500 dst = mov_rr(dst, opts->regs[Z80_BC], SCRATCH1, SZ_W);
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	501 dst = mov_rr(dst, opts->regs[Z80_HL], SCRATCH2, SZ_W);
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	502 dst = mov_rdisp8r(dst, CONTEXT, zar_off(Z80_C), opts->regs[Z80_BC], SZ_W);
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	503 dst = mov_rdisp8r(dst, CONTEXT, zar_off(Z80_L), opts->regs[Z80_HL], SZ_W);
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	504 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, zar_off(Z80_C), SZ_W);
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	505 dst = mov_rrdisp8(dst, SCRATCH2, CONTEXT, zar_off(Z80_L), SZ_W);
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	506 dst = mov_rr(dst, opts->regs[Z80_DE], SCRATCH1, SZ_W);
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	507 dst = mov_rdisp8r(dst, CONTEXT, zar_off(Z80_E), opts->regs[Z80_DE], SZ_W);
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	508 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, zar_off(Z80_E), SZ_W);
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	509 break;
272 9b04b57434b5 Implement LDI Mike Pavone <pavone@retrodev.com> parents: 269 diff changeset	510 case Z80_LDI: {
9b04b57434b5 Implement LDI Mike Pavone <pavone@retrodev.com> parents: 269 diff changeset	511 dst = zcycles(dst, 8);
9b04b57434b5 Implement LDI Mike Pavone <pavone@retrodev.com> parents: 269 diff changeset	512 dst = mov_rr(dst, opts->regs[Z80_HL], SCRATCH1, SZ_W);
9b04b57434b5 Implement LDI Mike Pavone <pavone@retrodev.com> parents: 269 diff changeset	513 dst = call(dst, (uint8_t *)z80_read_byte);
9b04b57434b5 Implement LDI Mike Pavone <pavone@retrodev.com> parents: 269 diff changeset	514 dst = mov_rr(dst, opts->regs[Z80_DE], SCRATCH2, SZ_W);
9b04b57434b5 Implement LDI Mike Pavone <pavone@retrodev.com> parents: 269 diff changeset	515 dst = call(dst, (uint8_t *)z80_read_byte);
9b04b57434b5 Implement LDI Mike Pavone <pavone@retrodev.com> parents: 269 diff changeset	516 dst = zcycles(dst, 2);
9b04b57434b5 Implement LDI Mike Pavone <pavone@retrodev.com> parents: 269 diff changeset	517 dst = add_ir(dst, 1, opts->regs[Z80_DE], SZ_W);
9b04b57434b5 Implement LDI Mike Pavone <pavone@retrodev.com> parents: 269 diff changeset	518 dst = add_ir(dst, 1, opts->regs[Z80_HL], SZ_W);
9b04b57434b5 Implement LDI Mike Pavone <pavone@retrodev.com> parents: 269 diff changeset	519 dst = sub_ir(dst, 1, opts->regs[Z80_BC], SZ_W);
9b04b57434b5 Implement LDI Mike Pavone <pavone@retrodev.com> parents: 269 diff changeset	520 //TODO: Implement half-carry
9b04b57434b5 Implement LDI Mike Pavone <pavone@retrodev.com> parents: 269 diff changeset	521 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B);
9b04b57434b5 Implement LDI Mike Pavone <pavone@retrodev.com> parents: 269 diff changeset	522 dst = setcc_rdisp8(dst, CC_NZ, CONTEXT, zf_off(ZF_PV));
9b04b57434b5 Implement LDI Mike Pavone <pavone@retrodev.com> parents: 269 diff changeset	523 break;
9b04b57434b5 Implement LDI Mike Pavone <pavone@retrodev.com> parents: 269 diff changeset	524 }
261 f0c53a4bbfa3 Implement LDIR and fix a bug in which context was not restored after a call to z80_handle_code_write Mike Pavone <pavone@retrodev.com> parents: 259 diff changeset	525 case Z80_LDIR: {
f0c53a4bbfa3 Implement LDIR and fix a bug in which context was not restored after a call to z80_handle_code_write Mike Pavone <pavone@retrodev.com> parents: 259 diff changeset	526 dst = zcycles(dst, 8);
f0c53a4bbfa3 Implement LDIR and fix a bug in which context was not restored after a call to z80_handle_code_write Mike Pavone <pavone@retrodev.com> parents: 259 diff changeset	527 dst = mov_rr(dst, opts->regs[Z80_HL], SCRATCH1, SZ_W);
f0c53a4bbfa3 Implement LDIR and fix a bug in which context was not restored after a call to z80_handle_code_write Mike Pavone <pavone@retrodev.com> parents: 259 diff changeset	528 dst = call(dst, (uint8_t *)z80_read_byte);
f0c53a4bbfa3 Implement LDIR and fix a bug in which context was not restored after a call to z80_handle_code_write Mike Pavone <pavone@retrodev.com> parents: 259 diff changeset	529 dst = mov_rr(dst, opts->regs[Z80_DE], SCRATCH2, SZ_W);
f0c53a4bbfa3 Implement LDIR and fix a bug in which context was not restored after a call to z80_handle_code_write Mike Pavone <pavone@retrodev.com> parents: 259 diff changeset	530 dst = call(dst, (uint8_t *)z80_read_byte);
f0c53a4bbfa3 Implement LDIR and fix a bug in which context was not restored after a call to z80_handle_code_write Mike Pavone <pavone@retrodev.com> parents: 259 diff changeset	531 dst = add_ir(dst, 1, opts->regs[Z80_DE], SZ_W);
f0c53a4bbfa3 Implement LDIR and fix a bug in which context was not restored after a call to z80_handle_code_write Mike Pavone <pavone@retrodev.com> parents: 259 diff changeset	532 dst = add_ir(dst, 1, opts->regs[Z80_HL], SZ_W);
f0c53a4bbfa3 Implement LDIR and fix a bug in which context was not restored after a call to z80_handle_code_write Mike Pavone <pavone@retrodev.com> parents: 259 diff changeset	533
f0c53a4bbfa3 Implement LDIR and fix a bug in which context was not restored after a call to z80_handle_code_write Mike Pavone <pavone@retrodev.com> parents: 259 diff changeset	534 dst = sub_ir(dst, 1, opts->regs[Z80_BC], SZ_W);
f0c53a4bbfa3 Implement LDIR and fix a bug in which context was not restored after a call to z80_handle_code_write Mike Pavone <pavone@retrodev.com> parents: 259 diff changeset	535 uint8_t * cont = dst+1;
f0c53a4bbfa3 Implement LDIR and fix a bug in which context was not restored after a call to z80_handle_code_write Mike Pavone <pavone@retrodev.com> parents: 259 diff changeset	536 dst = jcc(dst, CC_Z, dst+2);
f0c53a4bbfa3 Implement LDIR and fix a bug in which context was not restored after a call to z80_handle_code_write Mike Pavone <pavone@retrodev.com> parents: 259 diff changeset	537 dst = zcycles(dst, 7);
f0c53a4bbfa3 Implement LDIR and fix a bug in which context was not restored after a call to z80_handle_code_write Mike Pavone <pavone@retrodev.com> parents: 259 diff changeset	538 //TODO: Figure out what the flag state should be here
f0c53a4bbfa3 Implement LDIR and fix a bug in which context was not restored after a call to z80_handle_code_write Mike Pavone <pavone@retrodev.com> parents: 259 diff changeset	539 //TODO: Figure out whether an interrupt can interrupt this
f0c53a4bbfa3 Implement LDIR and fix a bug in which context was not restored after a call to z80_handle_code_write Mike Pavone <pavone@retrodev.com> parents: 259 diff changeset	540 dst = jmp(dst, start);
f0c53a4bbfa3 Implement LDIR and fix a bug in which context was not restored after a call to z80_handle_code_write Mike Pavone <pavone@retrodev.com> parents: 259 diff changeset	541 *cont = dst - (cont + 1);
f0c53a4bbfa3 Implement LDIR and fix a bug in which context was not restored after a call to z80_handle_code_write Mike Pavone <pavone@retrodev.com> parents: 259 diff changeset	542 dst = zcycles(dst, 2);
f0c53a4bbfa3 Implement LDIR and fix a bug in which context was not restored after a call to z80_handle_code_write Mike Pavone <pavone@retrodev.com> parents: 259 diff changeset	543 //TODO: Implement half-carry
f0c53a4bbfa3 Implement LDIR and fix a bug in which context was not restored after a call to z80_handle_code_write Mike Pavone <pavone@retrodev.com> parents: 259 diff changeset	544 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B);
f0c53a4bbfa3 Implement LDIR and fix a bug in which context was not restored after a call to z80_handle_code_write Mike Pavone <pavone@retrodev.com> parents: 259 diff changeset	545 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_PV), SZ_B);
f0c53a4bbfa3 Implement LDIR and fix a bug in which context was not restored after a call to z80_handle_code_write Mike Pavone <pavone@retrodev.com> parents: 259 diff changeset	546 break;
f0c53a4bbfa3 Implement LDIR and fix a bug in which context was not restored after a call to z80_handle_code_write Mike Pavone <pavone@retrodev.com> parents: 259 diff changeset	547 }
f0c53a4bbfa3 Implement LDIR and fix a bug in which context was not restored after a call to z80_handle_code_write Mike Pavone <pavone@retrodev.com> parents: 259 diff changeset	548 /*case Z80_LDD:
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	549 case Z80_LDDR:
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	550 case Z80_CPI:
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	551 case Z80_CPIR:
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	552 case Z80_CPD:
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	553 case Z80_CPDR:
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	554 break;*/
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	555 case Z80_ADD:
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	556 cycles = 4;
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	557 if (inst->addr_mode == Z80_IX_DISPLACE \|\| inst->addr_mode == Z80_IY_DISPLACE) {
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	558 cycles += 12;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	559 } else if(inst->addr_mode == Z80_IMMED) {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	560 cycles += 3;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	561 } else if(z80_size(inst) == SZ_W) {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	562 cycles += 4;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	563 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	564 dst = zcycles(dst, cycles);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	565 dst = translate_z80_reg(inst, &dst_op, dst, opts);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	566 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	567 if (src_op.mode == MODE_REG_DIRECT) {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	568 dst = add_rr(dst, src_op.base, dst_op.base, z80_size(inst));
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	569 } else {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	570 dst = add_ir(dst, src_op.disp, dst_op.base, z80_size(inst));
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	571 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	572 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C));
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	573 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	574 //TODO: Implement half-carry flag
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	575 if (z80_size(inst) == SZ_B) {
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	576 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV));
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	577 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z));
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	578 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S));
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	579 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	580 dst = z80_save_reg(dst, inst, opts);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	581 dst = z80_save_ea(dst, inst, opts);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	582 break;
248 9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	583 case Z80_ADC:
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	584 cycles = 4;
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	585 if (inst->addr_mode == Z80_IX_DISPLACE \|\| inst->addr_mode == Z80_IY_DISPLACE) {
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	586 cycles += 12;
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	587 } else if(inst->addr_mode == Z80_IMMED) {
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	588 cycles += 3;
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	589 } else if(z80_size(inst) == SZ_W) {
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	590 cycles += 4;
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	591 }
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	592 dst = zcycles(dst, cycles);
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	593 dst = translate_z80_reg(inst, &dst_op, dst, opts);
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	594 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY);
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	595 if (src_op.mode == MODE_REG_DIRECT) {
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	596 dst = adc_rr(dst, src_op.base, dst_op.base, z80_size(inst));
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	597 } else {
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	598 dst = adc_ir(dst, src_op.disp, dst_op.base, z80_size(inst));
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	599 }
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	600 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C));
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	601 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B);
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	602 //TODO: Implement half-carry flag
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	603 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV));
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	604 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z));
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	605 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S));
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	606 dst = z80_save_reg(dst, inst, opts);
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	607 dst = z80_save_ea(dst, inst, opts);
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	608 break;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	609 case Z80_SUB:
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	610 cycles = 4;
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	611 if (inst->addr_mode == Z80_IX_DISPLACE \|\| inst->addr_mode == Z80_IY_DISPLACE) {
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	612 cycles += 12;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	613 } else if(inst->addr_mode == Z80_IMMED) {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	614 cycles += 3;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	615 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	616 dst = zcycles(dst, cycles);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	617 dst = translate_z80_reg(inst, &dst_op, dst, opts);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	618 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	619 if (src_op.mode == MODE_REG_DIRECT) {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	620 dst = sub_rr(dst, src_op.base, dst_op.base, z80_size(inst));
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	621 } else {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	622 dst = sub_ir(dst, src_op.disp, dst_op.base, z80_size(inst));
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	623 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	624 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C));
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	625 dst = mov_irdisp8(dst, 1, CONTEXT, zf_off(ZF_N), SZ_B);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	626 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV));
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	627 //TODO: Implement half-carry flag
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	628 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z));
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	629 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S));
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	630 dst = z80_save_reg(dst, inst, opts);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	631 dst = z80_save_ea(dst, inst, opts);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	632 break;
248 9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	633 case Z80_SBC:
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	634 cycles = 4;
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	635 if (inst->addr_mode == Z80_IX_DISPLACE \|\| inst->addr_mode == Z80_IY_DISPLACE) {
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	636 cycles += 12;
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	637 } else if(inst->addr_mode == Z80_IMMED) {
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	638 cycles += 3;
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	639 } else if(z80_size(inst) == SZ_W) {
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	640 cycles += 4;
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	641 }
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	642 dst = zcycles(dst, cycles);
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	643 dst = translate_z80_reg(inst, &dst_op, dst, opts);
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	644 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY);
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	645 if (src_op.mode == MODE_REG_DIRECT) {
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	646 dst = sbb_rr(dst, src_op.base, dst_op.base, z80_size(inst));
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	647 } else {
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	648 dst = sbb_ir(dst, src_op.disp, dst_op.base, z80_size(inst));
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	649 }
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	650 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C));
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	651 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B);
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	652 //TODO: Implement half-carry flag
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	653 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV));
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	654 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z));
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	655 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S));
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	656 dst = z80_save_reg(dst, inst, opts);
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	657 dst = z80_save_ea(dst, inst, opts);
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	658 break;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	659 case Z80_AND:
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	660 cycles = 4;
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	661 if (inst->addr_mode == Z80_IX_DISPLACE \|\| inst->addr_mode == Z80_IY_DISPLACE) {
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	662 cycles += 12;
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	663 } else if(inst->addr_mode == Z80_IMMED) {
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	664 cycles += 3;
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	665 } else if(z80_size(inst) == SZ_W) {
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	666 cycles += 4;
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	667 }
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	668 dst = zcycles(dst, cycles);
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	669 dst = translate_z80_reg(inst, &dst_op, dst, opts);
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	670 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY);
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	671 if (src_op.mode == MODE_REG_DIRECT) {
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	672 dst = and_rr(dst, src_op.base, dst_op.base, z80_size(inst));
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	673 } else {
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	674 dst = and_ir(dst, src_op.disp, dst_op.base, z80_size(inst));
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	675 }
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	676 //TODO: Cleanup flags
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	677 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C));
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	678 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B);
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	679 //TODO: Implement half-carry flag
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	680 if (z80_size(inst) == SZ_B) {
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	681 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV));
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	682 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z));
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	683 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S));
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	684 }
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	685 dst = z80_save_reg(dst, inst, opts);
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	686 dst = z80_save_ea(dst, inst, opts);
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	687 break;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	688 case Z80_OR:
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	689 cycles = 4;
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	690 if (inst->addr_mode == Z80_IX_DISPLACE \|\| inst->addr_mode == Z80_IY_DISPLACE) {
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	691 cycles += 12;
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	692 } else if(inst->addr_mode == Z80_IMMED) {
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	693 cycles += 3;
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	694 } else if(z80_size(inst) == SZ_W) {
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	695 cycles += 4;
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	696 }
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	697 dst = zcycles(dst, cycles);
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	698 dst = translate_z80_reg(inst, &dst_op, dst, opts);
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	699 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY);
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	700 if (src_op.mode == MODE_REG_DIRECT) {
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	701 dst = or_rr(dst, src_op.base, dst_op.base, z80_size(inst));
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	702 } else {
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	703 dst = or_ir(dst, src_op.disp, dst_op.base, z80_size(inst));
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	704 }
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	705 //TODO: Cleanup flags
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	706 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C));
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	707 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B);
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	708 //TODO: Implement half-carry flag
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	709 if (z80_size(inst) == SZ_B) {
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	710 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV));
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	711 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z));
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	712 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S));
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	713 }
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	714 dst = z80_save_reg(dst, inst, opts);
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	715 dst = z80_save_ea(dst, inst, opts);
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	716 break;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	717 case Z80_XOR:
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	718 cycles = 4;
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	719 if (inst->addr_mode == Z80_IX_DISPLACE \|\| inst->addr_mode == Z80_IY_DISPLACE) {
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	720 cycles += 12;
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	721 } else if(inst->addr_mode == Z80_IMMED) {
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	722 cycles += 3;
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	723 } else if(z80_size(inst) == SZ_W) {
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	724 cycles += 4;
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	725 }
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	726 dst = zcycles(dst, cycles);
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	727 dst = translate_z80_reg(inst, &dst_op, dst, opts);
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	728 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY);
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	729 if (src_op.mode == MODE_REG_DIRECT) {
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	730 dst = add_rr(dst, src_op.base, dst_op.base, z80_size(inst));
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	731 } else {
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	732 dst = add_ir(dst, src_op.disp, dst_op.base, z80_size(inst));
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	733 }
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	734 //TODO: Cleanup flags
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	735 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C));
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	736 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B);
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	737 //TODO: Implement half-carry flag
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	738 if (z80_size(inst) == SZ_B) {
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	739 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV));
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	740 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z));
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	741 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S));
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	742 }
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	743 dst = z80_save_reg(dst, inst, opts);
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	744 dst = z80_save_ea(dst, inst, opts);
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	745 break;
242 d3b84b2a4397 Implemente CP (untested) Mike Pavone <pavone@retrodev.com> parents: 241 diff changeset	746 case Z80_CP:
d3b84b2a4397 Implemente CP (untested) Mike Pavone <pavone@retrodev.com> parents: 241 diff changeset	747 cycles = 4;
d3b84b2a4397 Implemente CP (untested) Mike Pavone <pavone@retrodev.com> parents: 241 diff changeset	748 if (inst->addr_mode == Z80_IX_DISPLACE \|\| inst->addr_mode == Z80_IY_DISPLACE) {
d3b84b2a4397 Implemente CP (untested) Mike Pavone <pavone@retrodev.com> parents: 241 diff changeset	749 cycles += 12;
d3b84b2a4397 Implemente CP (untested) Mike Pavone <pavone@retrodev.com> parents: 241 diff changeset	750 } else if(inst->addr_mode == Z80_IMMED) {
d3b84b2a4397 Implemente CP (untested) Mike Pavone <pavone@retrodev.com> parents: 241 diff changeset	751 cycles += 3;
d3b84b2a4397 Implemente CP (untested) Mike Pavone <pavone@retrodev.com> parents: 241 diff changeset	752 }
d3b84b2a4397 Implemente CP (untested) Mike Pavone <pavone@retrodev.com> parents: 241 diff changeset	753 dst = zcycles(dst, cycles);
d3b84b2a4397 Implemente CP (untested) Mike Pavone <pavone@retrodev.com> parents: 241 diff changeset	754 dst = translate_z80_reg(inst, &dst_op, dst, opts);
d3b84b2a4397 Implemente CP (untested) Mike Pavone <pavone@retrodev.com> parents: 241 diff changeset	755 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY);
d3b84b2a4397 Implemente CP (untested) Mike Pavone <pavone@retrodev.com> parents: 241 diff changeset	756 if (src_op.mode == MODE_REG_DIRECT) {
d3b84b2a4397 Implemente CP (untested) Mike Pavone <pavone@retrodev.com> parents: 241 diff changeset	757 dst = cmp_rr(dst, src_op.base, dst_op.base, z80_size(inst));
d3b84b2a4397 Implemente CP (untested) Mike Pavone <pavone@retrodev.com> parents: 241 diff changeset	758 } else {
d3b84b2a4397 Implemente CP (untested) Mike Pavone <pavone@retrodev.com> parents: 241 diff changeset	759 dst = cmp_ir(dst, src_op.disp, dst_op.base, z80_size(inst));
d3b84b2a4397 Implemente CP (untested) Mike Pavone <pavone@retrodev.com> parents: 241 diff changeset	760 }
d3b84b2a4397 Implemente CP (untested) Mike Pavone <pavone@retrodev.com> parents: 241 diff changeset	761 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C));
d3b84b2a4397 Implemente CP (untested) Mike Pavone <pavone@retrodev.com> parents: 241 diff changeset	762 dst = mov_irdisp8(dst, 1, CONTEXT, zf_off(ZF_N), SZ_B);
d3b84b2a4397 Implemente CP (untested) Mike Pavone <pavone@retrodev.com> parents: 241 diff changeset	763 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV));
d3b84b2a4397 Implemente CP (untested) Mike Pavone <pavone@retrodev.com> parents: 241 diff changeset	764 //TODO: Implement half-carry flag
d3b84b2a4397 Implemente CP (untested) Mike Pavone <pavone@retrodev.com> parents: 241 diff changeset	765 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z));
d3b84b2a4397 Implemente CP (untested) Mike Pavone <pavone@retrodev.com> parents: 241 diff changeset	766 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S));
d3b84b2a4397 Implemente CP (untested) Mike Pavone <pavone@retrodev.com> parents: 241 diff changeset	767 dst = z80_save_reg(dst, inst, opts);
d3b84b2a4397 Implemente CP (untested) Mike Pavone <pavone@retrodev.com> parents: 241 diff changeset	768 dst = z80_save_ea(dst, inst, opts);
d3b84b2a4397 Implemente CP (untested) Mike Pavone <pavone@retrodev.com> parents: 241 diff changeset	769 break;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	770 case Z80_INC:
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	771 cycles = 4;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	772 if (inst->reg == Z80_IX \|\| inst->reg == Z80_IY) {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	773 cycles += 6;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	774 } else if(z80_size(inst) == SZ_W) {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	775 cycles += 2;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	776 } else if(inst->reg == Z80_IXH \|\| inst->reg == Z80_IXL \|\| inst->reg == Z80_IYH \|\| inst->reg == Z80_IYL \|\| inst->addr_mode == Z80_IX_DISPLACE \|\| inst->addr_mode == Z80_IY_DISPLACE) {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	777 cycles += 4;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	778 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	779 dst = translate_z80_reg(inst, &dst_op, dst, opts);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	780 if (dst_op.mode == MODE_UNUSED) {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	781 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	782 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	783 dst = add_ir(dst, 1, dst_op.base, z80_size(inst));
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	784 if (z80_size(inst) == SZ_B) {
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	785 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	786 //TODO: Implement half-carry flag
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	787 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV));
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	788 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z));
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	789 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S));
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	790 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	791 dst = z80_save_reg(dst, inst, opts);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	792 dst = z80_save_ea(dst, inst, opts);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	793 break;
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	794 case Z80_DEC:
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	795 cycles = 4;
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	796 if (inst->reg == Z80_IX \|\| inst->reg == Z80_IY) {
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	797 cycles += 6;
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	798 } else if(z80_size(inst) == SZ_W) {
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	799 cycles += 2;
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	800 } else if(inst->reg == Z80_IXH \|\| inst->reg == Z80_IXL \|\| inst->reg == Z80_IYH \|\| inst->reg == Z80_IYL \|\| inst->addr_mode == Z80_IX_DISPLACE \|\| inst->addr_mode == Z80_IY_DISPLACE) {
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	801 cycles += 4;
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	802 }
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	803 dst = translate_z80_reg(inst, &dst_op, dst, opts);
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	804 if (dst_op.mode == MODE_UNUSED) {
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	805 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY);
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	806 }
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	807 dst = sub_ir(dst, 1, dst_op.base, z80_size(inst));
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	808 if (z80_size(inst) == SZ_B) {
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	809 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B);
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	810 //TODO: Implement half-carry flag
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	811 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV));
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	812 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z));
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	813 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S));
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	814 }
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	815 dst = z80_save_reg(dst, inst, opts);
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	816 dst = z80_save_ea(dst, inst, opts);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	817 break;
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	818 /*case Z80_DAA:
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	819 case Z80_CPL:
257 4c7933444df4 Implement CCF and SCF Mike Pavone <pavone@retrodev.com> parents: 255 diff changeset	820 case Z80_NEG:*/
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	821 case Z80_CCF:
257 4c7933444df4 Implement CCF and SCF Mike Pavone <pavone@retrodev.com> parents: 255 diff changeset	822 dst = zcycles(dst, 4);
4c7933444df4 Implement CCF and SCF Mike Pavone <pavone@retrodev.com> parents: 255 diff changeset	823 dst = xor_irdisp8(dst, 1, CONTEXT, zf_off(ZF_C), SZ_B);
4c7933444df4 Implement CCF and SCF Mike Pavone <pavone@retrodev.com> parents: 255 diff changeset	824 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B);
4c7933444df4 Implement CCF and SCF Mike Pavone <pavone@retrodev.com> parents: 255 diff changeset	825 //TODO: Implement half-carry flag
4c7933444df4 Implement CCF and SCF Mike Pavone <pavone@retrodev.com> parents: 255 diff changeset	826 break;
4c7933444df4 Implement CCF and SCF Mike Pavone <pavone@retrodev.com> parents: 255 diff changeset	827 case Z80_SCF:
4c7933444df4 Implement CCF and SCF Mike Pavone <pavone@retrodev.com> parents: 255 diff changeset	828 dst = zcycles(dst, 4);
4c7933444df4 Implement CCF and SCF Mike Pavone <pavone@retrodev.com> parents: 255 diff changeset	829 dst = mov_irdisp8(dst, 1, CONTEXT, zf_off(ZF_C), SZ_B);
4c7933444df4 Implement CCF and SCF Mike Pavone <pavone@retrodev.com> parents: 255 diff changeset	830 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B);
4c7933444df4 Implement CCF and SCF Mike Pavone <pavone@retrodev.com> parents: 255 diff changeset	831 //TODO: Implement half-carry flag
4c7933444df4 Implement CCF and SCF Mike Pavone <pavone@retrodev.com> parents: 255 diff changeset	832 break;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	833 case Z80_NOP:
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	834 if (inst->immed == 42) {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	835 dst = call(dst, (uint8_t *)z80_save_context);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	836 dst = mov_rr(dst, CONTEXT, RDI, SZ_Q);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	837 dst = jmp(dst, (uint8_t *)z80_print_regs_exit);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	838 } else {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	839 dst = zcycles(dst, 4 * inst->immed);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	840 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	841 break;
243 2f069a0b487e Implement EI, DI and IM in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 242 diff changeset	842 //case Z80_HALT:
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	843 case Z80_DI:
243 2f069a0b487e Implement EI, DI and IM in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 242 diff changeset	844 dst = zcycles(dst, 4);
2f069a0b487e Implement EI, DI and IM in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 242 diff changeset	845 dst = mov_irdisp8(dst, 0, CONTEXT, offsetof(z80_context, iff1), SZ_B);
2f069a0b487e Implement EI, DI and IM in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 242 diff changeset	846 dst = mov_irdisp8(dst, 0, CONTEXT, offsetof(z80_context, iff2), SZ_B);
250 5f1b68cecfc7 Implemented basic interrupt support in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 248 diff changeset	847 dst = mov_rdisp8r(dst, CONTEXT, offsetof(z80_context, sync_cycle), ZLIMIT, SZ_D);
243 2f069a0b487e Implement EI, DI and IM in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 242 diff changeset	848 break;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	849 case Z80_EI:
243 2f069a0b487e Implement EI, DI and IM in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 242 diff changeset	850 //TODO: Implement interrupt enable latency of 1 instruction afer EI
2f069a0b487e Implement EI, DI and IM in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 242 diff changeset	851 dst = zcycles(dst, 4);
2f069a0b487e Implement EI, DI and IM in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 242 diff changeset	852 dst = mov_irdisp8(dst, 1, CONTEXT, offsetof(z80_context, iff1), SZ_B);
2f069a0b487e Implement EI, DI and IM in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 242 diff changeset	853 dst = mov_irdisp8(dst, 1, CONTEXT, offsetof(z80_context, iff2), SZ_B);
250 5f1b68cecfc7 Implemented basic interrupt support in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 248 diff changeset	854 dst = call(dst, (uint8_t *)z80_do_sync);
243 2f069a0b487e Implement EI, DI and IM in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 242 diff changeset	855 break;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	856 case Z80_IM:
243 2f069a0b487e Implement EI, DI and IM in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 242 diff changeset	857 dst = zcycles(dst, 4);
2f069a0b487e Implement EI, DI and IM in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 242 diff changeset	858 dst = mov_irdisp8(dst, inst->immed, CONTEXT, offsetof(z80_context, im), SZ_B);
2f069a0b487e Implement EI, DI and IM in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 242 diff changeset	859 break;
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	860 case Z80_RLC:
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	861 cycles = inst->immed == 1 ? 4 : (inst->addr_mode == Z80_IX_DISPLACE \|\| inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8);
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	862 dst = zcycles(dst, cycles);
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	863 if (inst->reg == Z80_UNUSED) {
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	864 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY);
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	865 dst = zcycles(dst, 1);
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	866 } else {
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	867 dst = translate_z80_reg(inst, &dst_op, dst, opts);
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	868 }
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	869 dst = rol_ir(dst, 1, dst_op.base, SZ_B);
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	870 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C));
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	871 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B);
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	872 //TODO: Implement half-carry flag
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	873 dst = cmp_ir(dst, 0, dst_op.base, SZ_B);
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	874 dst = setcc_rdisp8(dst, CC_P, CONTEXT, zf_off(ZF_PV));
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	875 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z));
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	876 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S));
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	877 if (inst->reg == Z80_UNUSED) {
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	878 dst = z80_save_result(dst, inst);
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	879 } else {
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	880 dst = z80_save_reg(dst, inst, opts);
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	881 }
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	882 break;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	883 case Z80_RL:
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	884 cycles = inst->immed == 1 ? 4 : (inst->addr_mode == Z80_IX_DISPLACE \|\| inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8);
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	885 dst = zcycles(dst, cycles);
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	886 if (inst->reg == Z80_UNUSED) {
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	887 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY);
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	888 dst = zcycles(dst, 1);
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	889 } else {
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	890 dst = translate_z80_reg(inst, &dst_op, dst, opts);
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	891 }
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	892 dst = bt_irdisp8(dst, 0, CONTEXT, zf_off(ZF_C), SZ_B);
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	893 dst = rcl_ir(dst, 1, dst_op.base, SZ_B);
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	894 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C));
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	895 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B);
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	896 //TODO: Implement half-carry flag
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	897 dst = cmp_ir(dst, 0, dst_op.base, SZ_B);
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	898 dst = setcc_rdisp8(dst, CC_P, CONTEXT, zf_off(ZF_PV));
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	899 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z));
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	900 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S));
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	901 if (inst->reg == Z80_UNUSED) {
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	902 dst = z80_save_result(dst, inst);
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	903 } else {
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	904 dst = z80_save_reg(dst, inst, opts);
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	905 }
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	906 break;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	907 case Z80_RRC:
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	908 cycles = inst->immed == 1 ? 4 : (inst->addr_mode == Z80_IX_DISPLACE \|\| inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8);
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	909 dst = zcycles(dst, cycles);
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	910 if (inst->reg == Z80_UNUSED) {
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	911 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY);
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	912 dst = zcycles(dst, 1);
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	913 } else {
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	914 dst = translate_z80_reg(inst, &dst_op, dst, opts);
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	915 }
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	916 dst = ror_ir(dst, 1, dst_op.base, SZ_B);
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	917 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C));
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	918 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B);
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	919 //TODO: Implement half-carry flag
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	920 dst = cmp_ir(dst, 0, dst_op.base, SZ_B);
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	921 dst = setcc_rdisp8(dst, CC_P, CONTEXT, zf_off(ZF_PV));
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	922 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z));
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	923 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S));
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	924 if (inst->reg == Z80_UNUSED) {
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	925 dst = z80_save_result(dst, inst);
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	926 } else {
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	927 dst = z80_save_reg(dst, inst, opts);
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	928 }
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	929 break;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	930 case Z80_RR:
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	931 cycles = inst->immed == 1 ? 4 : (inst->addr_mode == Z80_IX_DISPLACE \|\| inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8);
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	932 dst = zcycles(dst, cycles);
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	933 if (inst->reg == Z80_UNUSED) {
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	934 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY);
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	935 dst = zcycles(dst, 1);
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	936 } else {
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	937 dst = translate_z80_reg(inst, &dst_op, dst, opts);
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	938 }
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	939 dst = bt_irdisp8(dst, 0, CONTEXT, zf_off(ZF_C), SZ_B);
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	940 dst = rcr_ir(dst, 1, dst_op.base, SZ_B);
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	941 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C));
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	942 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B);
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	943 //TODO: Implement half-carry flag
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	944 dst = cmp_ir(dst, 0, dst_op.base, SZ_B);
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	945 dst = setcc_rdisp8(dst, CC_P, CONTEXT, zf_off(ZF_PV));
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	946 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z));
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	947 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S));
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	948 if (inst->reg == Z80_UNUSED) {
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	949 dst = z80_save_result(dst, inst);
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	950 } else {
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	951 dst = z80_save_reg(dst, inst, opts);
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	952 }
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	953 break;
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	954 /*case Z80_SLA:
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	955 case Z80_SRA:
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	956 case Z80_SLL:
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	957 case Z80_SRL:
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	958 case Z80_RLD:
239 a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	959 case Z80_RRD:*/
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	960 case Z80_BIT:
239 a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	961 cycles = (inst->addr_mode == Z80_IX_DISPLACE \|\| inst->addr_mode == Z80_IY_DISPLACE) ? 8 : 16;
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	962 dst = zcycles(dst, cycles);
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	963 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY);
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	964 if (inst->addr_mode != Z80_REG) {
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	965 //Reads normally take 3 cycles, but the read at the end of a bit instruction takes 4
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	966 dst = zcycles(dst, 1);
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	967 }
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	968 dst = bt_ir(dst, inst->immed, src_op.base, SZ_B);
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	969 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_Z));
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	970 break;
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	971 case Z80_SET:
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	972 cycles = (inst->addr_mode == Z80_IX_DISPLACE \|\| inst->addr_mode == Z80_IY_DISPLACE) ? 8 : 16;
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	973 dst = zcycles(dst, cycles);
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	974 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY);
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	975 if (inst->addr_mode != Z80_REG) {
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	976 //Reads normally take 3 cycles, but the read in the middle of a set instruction takes 4
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	977 dst = zcycles(dst, 1);
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	978 }
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	979 dst = bts_ir(dst, inst->immed, src_op.base, SZ_B);
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	980 if (inst->addr_mode != Z80_REG) {
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	981 dst = z80_save_result(dst, inst);
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	982 }
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	983 break;
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	984 case Z80_RES:
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	985 cycles = (inst->addr_mode == Z80_IX_DISPLACE \|\| inst->addr_mode == Z80_IY_DISPLACE) ? 8 : 16;
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	986 dst = zcycles(dst, cycles);
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	987 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY);
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	988 if (inst->addr_mode != Z80_REG) {
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	989 //Reads normally take 3 cycles, but the read in the middle of a set instruction takes 4
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	990 dst = zcycles(dst, 1);
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	991 }
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	992 dst = btr_ir(dst, inst->immed, src_op.base, SZ_B);
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	993 if (inst->addr_mode != Z80_REG) {
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	994 dst = z80_save_result(dst, inst);
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	995 }
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	996 break;
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	997 case Z80_JP: {
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	998 cycles = 4;
239 a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	999 if (inst->addr_mode != Z80_REG) {
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1000 cycles += 6;
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1001 } else if(inst->ea_reg == Z80_IX \|\| inst->ea_reg == Z80_IY) {
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1002 cycles += 4;
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1003 }
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1004 dst = zcycles(dst, cycles);
239 a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	1005 if (inst->addr_mode != Z80_REG_INDIRECT && inst->immed < 0x4000) {
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1006 uint8_t * call_dst = z80_get_native_address(context, inst->immed);
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1007 if (!call_dst) {
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1008 opts->deferred = defer_address(opts->deferred, inst->immed, dst + 1);
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1009 //fake address to force large displacement
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1010 call_dst = dst + 256;
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1011 }
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1012 dst = jmp(dst, call_dst);
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1013 } else {
239 a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	1014 if (inst->addr_mode == Z80_REG_INDIRECT) {
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1015 dst = mov_rr(dst, opts->regs[inst->ea_reg], SCRATCH1, SZ_W);
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1016 } else {
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1017 dst = mov_ir(dst, inst->immed, SCRATCH1, SZ_W);
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1018 }
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1019 dst = call(dst, (uint8_t *)z80_native_addr);
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1020 dst = jmp_r(dst, SCRATCH1);
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1021 }
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1022 break;
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1023 }
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1024 case Z80_JPCC: {
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1025 dst = zcycles(dst, 7);//T States: 4,3
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1026 uint8_t cond = CC_Z;
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1027 switch (inst->reg)
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1028 {
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1029 case Z80_CC_NZ:
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1030 cond = CC_NZ;
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1031 case Z80_CC_Z:
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1032 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_Z), SZ_B);
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1033 break;
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1034 case Z80_CC_NC:
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1035 cond = CC_NZ;
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1036 case Z80_CC_C:
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1037 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_C), SZ_B);
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1038 break;
238 827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1039 case Z80_CC_PO:
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1040 cond = CC_NZ;
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1041 case Z80_CC_PE:
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1042 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_PV), SZ_B);
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1043 break;
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1044 case Z80_CC_P:
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1045 case Z80_CC_M:
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1046 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_S), SZ_B);
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1047 break;
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1048 }
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1049 uint8_t *no_jump_off = dst+1;
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1050 dst = jcc(dst, cond, dst+2);
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1051 dst = zcycles(dst, 5);//T States: 5
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1052 uint16_t dest_addr = inst->immed;
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1053 if (dest_addr < 0x4000) {
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1054 uint8_t * call_dst = z80_get_native_address(context, dest_addr);
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1055 if (!call_dst) {
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1056 opts->deferred = defer_address(opts->deferred, dest_addr, dst + 1);
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1057 //fake address to force large displacement
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1058 call_dst = dst + 256;
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1059 }
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1060 dst = jmp(dst, call_dst);
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1061 } else {
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1062 dst = mov_ir(dst, dest_addr, SCRATCH1, SZ_W);
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1063 dst = call(dst, (uint8_t *)z80_native_addr);
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1064 dst = jmp_r(dst, SCRATCH1);
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1065 }
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1066 *no_jump_off = dst - (no_jump_off+1);
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1067 break;
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1068 }
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1069 case Z80_JR: {
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1070 dst = zcycles(dst, 12);//T States: 4,3,5
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1071 uint16_t dest_addr = address + inst->immed + 2;
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1072 if (dest_addr < 0x4000) {
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1073 uint8_t * call_dst = z80_get_native_address(context, dest_addr);
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1074 if (!call_dst) {
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1075 opts->deferred = defer_address(opts->deferred, dest_addr, dst + 1);
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1076 //fake address to force large displacement
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1077 call_dst = dst + 256;
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1078 }
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1079 dst = jmp(dst, call_dst);
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1080 } else {
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1081 dst = mov_ir(dst, dest_addr, SCRATCH1, SZ_W);
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1082 dst = call(dst, (uint8_t *)z80_native_addr);
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1083 dst = jmp_r(dst, SCRATCH1);
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1084 }
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1085 break;
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1086 }
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1087 case Z80_JRCC: {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1088 dst = zcycles(dst, 7);//T States: 4,3
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1089 uint8_t cond = CC_Z;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1090 switch (inst->reg)
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1091 {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1092 case Z80_CC_NZ:
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1093 cond = CC_NZ;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1094 case Z80_CC_Z:
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1095 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_Z), SZ_B);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1096 break;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1097 case Z80_CC_NC:
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1098 cond = CC_NZ;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1099 case Z80_CC_C:
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1100 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_C), SZ_B);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1101 break;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1102 }
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1103 uint8_t *no_jump_off = dst+1;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1104 dst = jcc(dst, cond, dst+2);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1105 dst = zcycles(dst, 5);//T States: 5
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1106 uint16_t dest_addr = address + inst->immed + 2;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1107 if (dest_addr < 0x4000) {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1108 uint8_t * call_dst = z80_get_native_address(context, dest_addr);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1109 if (!call_dst) {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1110 opts->deferred = defer_address(opts->deferred, dest_addr, dst + 1);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1111 //fake address to force large displacement
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1112 call_dst = dst + 256;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1113 }
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1114 dst = jmp(dst, call_dst);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1115 } else {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1116 dst = mov_ir(dst, dest_addr, SCRATCH1, SZ_W);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1117 dst = call(dst, (uint8_t *)z80_native_addr);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1118 dst = jmp_r(dst, SCRATCH1);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1119 }
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1120 *no_jump_off = dst - (no_jump_off+1);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1121 break;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1122 }
239 a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	1123 case Z80_DJNZ:
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	1124 dst = zcycles(dst, 8);//T States: 5,3
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	1125 dst = sub_ir(dst, 1, opts->regs[Z80_B], SZ_B);
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	1126 uint8_t *no_jump_off = dst+1;
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	1127 dst = jcc(dst, CC_Z, dst+2);
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	1128 dst = zcycles(dst, 5);//T States: 5
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	1129 uint16_t dest_addr = address + inst->immed + 2;
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	1130 if (dest_addr < 0x4000) {
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	1131 uint8_t * call_dst = z80_get_native_address(context, dest_addr);
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	1132 if (!call_dst) {
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	1133 opts->deferred = defer_address(opts->deferred, dest_addr, dst + 1);
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	1134 //fake address to force large displacement
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	1135 call_dst = dst + 256;
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	1136 }
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	1137 dst = jmp(dst, call_dst);
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	1138 } else {
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	1139 dst = mov_ir(dst, dest_addr, SCRATCH1, SZ_W);
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	1140 dst = call(dst, (uint8_t *)z80_native_addr);
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	1141 dst = jmp_r(dst, SCRATCH1);
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	1142 }
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	1143 *no_jump_off = dst - (no_jump_off+1);
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	1144 break;
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1145 case Z80_CALL: {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1146 dst = zcycles(dst, 11);//T States: 4,3,4
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1147 dst = sub_ir(dst, 2, opts->regs[Z80_SP], SZ_W);
253 3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around. Mike Pavone <pavone@retrodev.com> parents: 252 diff changeset	1148 dst = mov_ir(dst, address + 3, SCRATCH1, SZ_W);
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around. Mike Pavone <pavone@retrodev.com> parents: 252 diff changeset	1149 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH2, SZ_W);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1150 dst = call(dst, (uint8_t *)z80_write_word_highfirst);//T States: 3, 3
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1151 if (inst->immed < 0x4000) {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1152 uint8_t * call_dst = z80_get_native_address(context, inst->immed);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1153 if (!call_dst) {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1154 opts->deferred = defer_address(opts->deferred, inst->immed, dst + 1);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1155 //fake address to force large displacement
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1156 call_dst = dst + 256;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1157 }
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1158 dst = jmp(dst, call_dst);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1159 } else {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1160 dst = mov_ir(dst, inst->immed, SCRATCH1, SZ_W);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1161 dst = call(dst, (uint8_t *)z80_native_addr);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1162 dst = jmp_r(dst, SCRATCH1);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1163 }
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1164 break;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1165 }
238 827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1166 case Z80_CALLCC:
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1167 dst = zcycles(dst, 10);//T States: 4,3,3 (false case)
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1168 uint8_t cond = CC_Z;
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1169 switch (inst->reg)
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1170 {
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1171 case Z80_CC_NZ:
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1172 cond = CC_NZ;
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1173 case Z80_CC_Z:
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1174 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_Z), SZ_B);
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1175 break;
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1176 case Z80_CC_NC:
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1177 cond = CC_NZ;
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1178 case Z80_CC_C:
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1179 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_C), SZ_B);
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1180 break;
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1181 case Z80_CC_PO:
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1182 cond = CC_NZ;
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1183 case Z80_CC_PE:
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1184 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_PV), SZ_B);
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1185 break;
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1186 case Z80_CC_P:
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1187 case Z80_CC_M:
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1188 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_S), SZ_B);
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1189 break;
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1190 }
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1191 uint8_t *no_call_off = dst+1;
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1192 dst = jcc(dst, cond, dst+2);
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1193 dst = zcycles(dst, 1);//Last of the above T states takes an extra cycle in the true case
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1194 dst = sub_ir(dst, 2, opts->regs[Z80_SP], SZ_W);
253 3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around. Mike Pavone <pavone@retrodev.com> parents: 252 diff changeset	1195 dst = mov_ir(dst, address + 3, SCRATCH1, SZ_W);
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around. Mike Pavone <pavone@retrodev.com> parents: 252 diff changeset	1196 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH2, SZ_W);
238 827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1197 dst = call(dst, (uint8_t *)z80_write_word_highfirst);//T States: 3, 3
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1198 if (inst->immed < 0x4000) {
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1199 uint8_t * call_dst = z80_get_native_address(context, inst->immed);
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1200 if (!call_dst) {
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1201 opts->deferred = defer_address(opts->deferred, inst->immed, dst + 1);
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1202 //fake address to force large displacement
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1203 call_dst = dst + 256;
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1204 }
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1205 dst = jmp(dst, call_dst);
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1206 } else {
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1207 dst = mov_ir(dst, inst->immed, SCRATCH1, SZ_W);
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1208 dst = call(dst, (uint8_t *)z80_native_addr);
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1209 dst = jmp_r(dst, SCRATCH1);
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1210 }
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1211 *no_call_off = dst - (no_call_off+1);
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1212 break;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	1213 case Z80_RET:
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1214 dst = zcycles(dst, 4);//T States: 4
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1215 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH1, SZ_W);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1216 dst = call(dst, (uint8_t *)z80_read_word);//T STates: 3, 3
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1217 dst = add_ir(dst, 2, opts->regs[Z80_SP], SZ_W);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1218 dst = call(dst, (uint8_t *)z80_native_addr);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1219 dst = jmp_r(dst, SCRATCH1);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1220 break;
246 ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1221 case Z80_RETCC: {
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1222 dst = zcycles(dst, 5);//T States: 5
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1223 uint8_t cond = CC_Z;
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1224 switch (inst->reg)
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1225 {
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1226 case Z80_CC_NZ:
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1227 cond = CC_NZ;
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1228 case Z80_CC_Z:
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1229 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_Z), SZ_B);
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1230 break;
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1231 case Z80_CC_NC:
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1232 cond = CC_NZ;
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1233 case Z80_CC_C:
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1234 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_C), SZ_B);
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1235 break;
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1236 case Z80_CC_PO:
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1237 cond = CC_NZ;
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1238 case Z80_CC_PE:
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1239 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_PV), SZ_B);
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1240 break;
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1241 case Z80_CC_P:
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1242 case Z80_CC_M:
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1243 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_S), SZ_B);
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1244 break;
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1245 }
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1246 uint8_t *no_call_off = dst+1;
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1247 dst = jcc(dst, cond, dst+2);
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1248 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH1, SZ_W);
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1249 dst = call(dst, (uint8_t *)z80_read_word);//T STates: 3, 3
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1250 dst = add_ir(dst, 2, opts->regs[Z80_SP], SZ_W);
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1251 dst = call(dst, (uint8_t *)z80_native_addr);
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1252 dst = jmp_r(dst, SCRATCH1);
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1253 *no_call_off = dst - (no_call_off+1);
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1254 break;
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1255 }
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1256 /*case Z80_RETI:
241 2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	1257 case Z80_RETN:*/
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	1258 case Z80_RST: {
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	1259 //RST is basically CALL to an address in page 0
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	1260 dst = zcycles(dst, 5);//T States: 5
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	1261 dst = sub_ir(dst, 2, opts->regs[Z80_SP], SZ_W);
253 3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around. Mike Pavone <pavone@retrodev.com> parents: 252 diff changeset	1262 dst = mov_ir(dst, address + 3, SCRATCH1, SZ_W);
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around. Mike Pavone <pavone@retrodev.com> parents: 252 diff changeset	1263 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH2, SZ_W);
241 2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	1264 dst = call(dst, (uint8_t *)z80_write_word_highfirst);//T States: 3, 3
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	1265 uint8_t * call_dst = z80_get_native_address(context, inst->immed);
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	1266 if (!call_dst) {
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	1267 opts->deferred = defer_address(opts->deferred, inst->immed, dst + 1);
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	1268 //fake address to force large displacement
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	1269 call_dst = dst + 256;
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	1270 }
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	1271 dst = jmp(dst, call_dst);
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	1272 break;
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	1273 }
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	1274 /*case Z80_IN:
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	1275 case Z80_INI:
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	1276 case Z80_INIR:
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	1277 case Z80_IND:
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	1278 case Z80_INDR:
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	1279 case Z80_OUT:
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	1280 case Z80_OUTI:
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	1281 case Z80_OTIR:
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	1282 case Z80_OUTD:
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	1283 case Z80_OTDR:*/
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1284 default: {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1285 char disbuf[80];
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1286 z80_disasm(inst, disbuf);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1287 fprintf(stderr, "unimplemented instruction: %s\n", disbuf);
259 d9417261366f Fix a remaining z80_write reg swap bug. Properly initialize the native map slots. Reset appropriate regs when z80_reset is called. Mike Pavone <pavone@retrodev.com> parents: 257 diff changeset	1288 FILE * f = fopen("zram.bin", "wb");
d9417261366f Fix a remaining z80_write reg swap bug. Properly initialize the native map slots. Reset appropriate regs when z80_reset is called. Mike Pavone <pavone@retrodev.com> parents: 257 diff changeset	1289 fwrite(context->mem_pointers[0], 1, 8 * 1024, f);
d9417261366f Fix a remaining z80_write reg swap bug. Properly initialize the native map slots. Reset appropriate regs when z80_reset is called. Mike Pavone <pavone@retrodev.com> parents: 257 diff changeset	1290 fclose(f);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	1291 exit(1);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	1292 }
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1293 }
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1294 return dst;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1295 }
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1296
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1297 uint8_t * z80_get_native_address(z80_context * context, uint32_t address)
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1298 {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1299 native_map_slot *map;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1300 if (address < 0x4000) {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1301 address &= 0x1FFF;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1302 map = context->static_code_map;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1303 } else if (address >= 0x8000) {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1304 address &= 0x7FFF;
252 63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1305 map = context->banked_code_map + (context->bank_reg << 15);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1306 } else {
268 6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	1307 dprintf("z80_get_native_address: %X NULL\n", address);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1308 return NULL;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1309 }
268 6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	1310 if (!map->base \|\| !map->offsets \|\| map->offsets[address] == INVALID_OFFSET \|\| map->offsets[address] == EXTENSION_WORD) {
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	1311 dprintf("z80_get_native_address: %X NULL\n", address);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1312 return NULL;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1313 }
268 6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	1314 dprintf("z80_get_native_address: %X %p\n", address, map->base + map->offsets[address]);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1315 return map->base + map->offsets[address];
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1316 }
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1317
252 63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1318 uint8_t z80_get_native_inst_size(x86_z80_options * opts, uint32_t address)
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1319 {
252 63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1320 if (address >= 0x4000) {
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1321 return 0;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1322 }
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1323 return opts->ram_inst_sizes[address & 0x1FFF];
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1324 }
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1325
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1326 void z80_map_native_address(z80_context * context, uint32_t address, uint8_t * native_address, uint8_t size, uint8_t native_size)
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1327 {
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1328 uint32_t orig_address = address;
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1329 native_map_slot *map;
252 63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1330 x86_z80_options * opts = context->options;
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1331 if (address < 0x4000) {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1332 address &= 0x1FFF;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1333 map = context->static_code_map;
252 63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1334 opts->ram_inst_sizes[address] = native_size;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1335 context->ram_code_flags[(address & 0x1C00) >> 10] \|= 1 << ((address & 0x380) >> 7);
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1336 context->ram_code_flags[((address + size) & 0x1C00) >> 10] \|= 1 << (((address + size) & 0x380) >> 7);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1337 } else if (address >= 0x8000) {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1338 address &= 0x7FFF;
252 63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1339 map = context->banked_code_map + (context->bank_reg << 15);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1340 if (!map->offsets) {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1341 map->offsets = malloc(sizeof(int32_t) * 0x8000);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1342 memset(map->offsets, 0xFF, sizeof(int32_t) * 0x8000);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1343 }
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1344 } else {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1345 return;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1346 }
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1347 if (!map->base) {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1348 map->base = native_address;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1349 }
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1350 map->offsets[address] = native_address - map->base;
253 3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around. Mike Pavone <pavone@retrodev.com> parents: 252 diff changeset	1351 for(--size, orig_address++; size; --size, orig_address++) {
252 63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1352 address = orig_address;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1353 if (address < 0x4000) {
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1354 address &= 0x1FFF;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1355 map = context->static_code_map;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1356 } else if (address >= 0x8000) {
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1357 address &= 0x7FFF;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1358 map = context->banked_code_map + (context->bank_reg << 15);
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1359 } else {
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1360 return;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1361 }
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1362 if (!map->offsets) {
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1363 map->offsets = malloc(sizeof(int32_t) * 0x8000);
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1364 memset(map->offsets, 0xFF, sizeof(int32_t) * 0x8000);
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1365 }
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1366 map->offsets[address] = EXTENSION_WORD;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1367 }
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1368 }
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1369
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1370 #define INVALID_INSTRUCTION_START 0xFEEDFEED
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1371
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1372 uint32_t z80_get_instruction_start(native_map_slot * static_code_map, uint32_t address)
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1373 {
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1374 if (!static_code_map->base \|\| address >= 0x4000) {
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1375 return INVALID_INSTRUCTION_START;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1376 }
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1377 address &= 0x1FFF;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1378 if (static_code_map->offsets[address] == INVALID_OFFSET) {
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1379 return INVALID_INSTRUCTION_START;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1380 }
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1381 while (static_code_map->offsets[address] == EXTENSION_WORD) {
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1382 --address;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1383 address &= 0x1FFF;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1384 }
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1385 return address;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1386 }
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1387
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1388 z80_context * z80_handle_code_write(uint32_t address, z80_context * context)
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1389 {
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1390 uint32_t inst_start = z80_get_instruction_start(context->static_code_map, address);
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1391 if (inst_start != INVALID_INSTRUCTION_START) {
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1392 uint8_t * dst = z80_get_native_address(context, inst_start);
268 6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	1393 dprintf("patching code at %p for Z80 instruction at %X due to write to %X\n", dst, inst_start, address);
252 63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1394 dst = mov_ir(dst, inst_start, SCRATCH1, SZ_D);
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1395 dst = jmp(dst, (uint8_t *)z80_retrans_stub);
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1396 }
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1397 return context;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1398 }
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1399
264 8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	1400 uint8_t * z80_get_native_address_trans(z80_context * context, uint32_t address)
8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	1401 {
8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	1402 uint8_t * addr = z80_get_native_address(context, address);
8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	1403 if (!addr) {
8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	1404 translate_z80_stream(context, address);
8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	1405 addr = z80_get_native_address(context, address);
8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	1406 if (!addr) {
8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	1407 printf("Failed to translate %X to native code\n", address);
8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	1408 }
8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	1409 }
8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	1410 return addr;
8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	1411 }
8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	1412
266 376df762ddf5 Fix some more retranslation bugs in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 264 diff changeset	1413 void z80_handle_deferred(z80_context * context)
376df762ddf5 Fix some more retranslation bugs in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 264 diff changeset	1414 {
376df762ddf5 Fix some more retranslation bugs in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 264 diff changeset	1415 x86_z80_options * opts = context->options;
376df762ddf5 Fix some more retranslation bugs in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 264 diff changeset	1416 process_deferred(&opts->deferred, context, (native_addr_func)z80_get_native_address);
376df762ddf5 Fix some more retranslation bugs in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 264 diff changeset	1417 if (opts->deferred) {
376df762ddf5 Fix some more retranslation bugs in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 264 diff changeset	1418 translate_z80_stream(context, opts->deferred->address);
376df762ddf5 Fix some more retranslation bugs in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 264 diff changeset	1419 }
376df762ddf5 Fix some more retranslation bugs in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 264 diff changeset	1420 }
376df762ddf5 Fix some more retranslation bugs in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 264 diff changeset	1421
252 63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1422 void * z80_retranslate_inst(uint32_t address, z80_context * context)
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1423 {
266 376df762ddf5 Fix some more retranslation bugs in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 264 diff changeset	1424 char disbuf[80];
252 63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1425 x86_z80_options * opts = context->options;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1426 uint8_t orig_size = z80_get_native_inst_size(opts, address);
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1427 uint8_t * orig_start = z80_get_native_address(context, address);
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1428 uint32_t orig = address;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1429 address &= 0x1FFF;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1430 uint8_t * dst = opts->cur_code;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1431 uint8_t * dst_end = opts->code_end;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1432 uint8_t after, inst = context->mem_pointers[0] + address;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1433 z80inst instbuf;
268 6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	1434 dprintf("Retranslating code at Z80 address %X, native address %p\n", address, orig_start);
252 63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1435 after = z80_decode(inst, &instbuf);
268 6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	1436 #ifdef DO_DEBUG_PRINT
267 1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	1437 z80_disasm(&instbuf, disbuf);
266 376df762ddf5 Fix some more retranslation bugs in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 264 diff changeset	1438 if (instbuf.op == Z80_NOP) {
376df762ddf5 Fix some more retranslation bugs in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 264 diff changeset	1439 printf("%X\t%s(%d)\n", address, disbuf, instbuf.immed);
376df762ddf5 Fix some more retranslation bugs in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 264 diff changeset	1440 } else {
376df762ddf5 Fix some more retranslation bugs in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 264 diff changeset	1441 printf("%X\t%s\n", address, disbuf);
267 1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	1442 }
268 6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	1443 #endif
252 63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1444 if (orig_size != ZMAX_NATIVE_SIZE) {
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1445 if (dst_end - dst < ZMAX_NATIVE_SIZE) {
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1446 size_t size = 1024*1024;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1447 dst = alloc_code(&size);
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1448 opts->code_end = dst_end = dst + size;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1449 opts->cur_code = dst;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1450 }
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1451 uint8_t * native_end = translate_z80inst(&instbuf, dst, context, address);
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1452 if ((native_end - dst) <= orig_size) {
264 8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	1453 uint8_t * native_next = z80_get_native_address(context, address + after-inst);
8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	1454 if (native_next && ((native_next == orig_start + orig_size) \|\| (orig_size - (native_end - dst)) > 5)) {
8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	1455 native_end = translate_z80inst(&instbuf, orig_start, context, address);
266 376df762ddf5 Fix some more retranslation bugs in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 264 diff changeset	1456 if (native_next == orig_start + orig_size && (native_next-native_end) < 2) {
264 8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	1457 while (native_end < orig_start + orig_size) {
8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	1458 *(native_end++) = 0x90; //NOP
8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	1459 }
8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	1460 } else {
8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	1461 jmp(native_end, native_next);
8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	1462 }
266 376df762ddf5 Fix some more retranslation bugs in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 264 diff changeset	1463 z80_handle_deferred(context);
264 8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	1464 return orig_start;
252 63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1465 }
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1466 }
264 8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	1467 z80_map_native_address(context, address, dst, after-inst, ZMAX_NATIVE_SIZE);
266 376df762ddf5 Fix some more retranslation bugs in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 264 diff changeset	1468 opts->cur_code = dst+ZMAX_NATIVE_SIZE;
376df762ddf5 Fix some more retranslation bugs in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 264 diff changeset	1469 jmp(orig_start, dst);
264 8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	1470 if(!(instbuf.op == Z80_RET \|\| instbuf.op == Z80_RETI \|\| instbuf.op == Z80_RETN \|\| instbuf.op == Z80_JP \|\| (instbuf.op == Z80_NOP && instbuf.immed == 42))) {
8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	1471 jmp(native_end, z80_get_native_address_trans(context, address + after-inst));
8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	1472 }
266 376df762ddf5 Fix some more retranslation bugs in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 264 diff changeset	1473 z80_handle_deferred(context);
264 8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	1474 return dst;
252 63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1475 } else {
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1476 dst = translate_z80inst(&instbuf, orig_start, context, address);
254 64feb6b67244 Fix bug in end condition inside translate_z80_stream. Mike Pavone <pavone@retrodev.com> parents: 253 diff changeset	1477 if(!(instbuf.op == Z80_RET \|\| instbuf.op == Z80_RETI \|\| instbuf.op == Z80_RETN \|\| instbuf.op == Z80_JP \|\| (instbuf.op == Z80_NOP && instbuf.immed == 42))) {
264 8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	1478 dst = jmp(dst, z80_get_native_address_trans(context, address + after-inst));
252 63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1479 }
266 376df762ddf5 Fix some more retranslation bugs in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 264 diff changeset	1480 z80_handle_deferred(context);
252 63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1481 return orig_start;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1482 }
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1483 }
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1484
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1485 void translate_z80_stream(z80_context * context, uint32_t address)
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1486 {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1487 char disbuf[80];
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1488 if (z80_get_native_address(context, address)) {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1489 return;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1490 }
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1491 x86_z80_options * opts = context->options;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1492 uint8_t * encoded = NULL, *next;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1493 if (address < 0x4000) {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1494 encoded = context->mem_pointers[0] + (address & 0x1FFF);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1495 } else if(address >= 0x8000 && context->mem_pointers[1]) {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1496 encoded = context->mem_pointers[1] + (address & 0x7FFF);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1497 }
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1498 while (encoded != NULL)
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1499 {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1500 z80inst inst;
268 6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	1501 dprintf("translating Z80 code at address %X\n", address);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1502 do {
252 63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1503 if (opts->code_end-opts->cur_code < ZMAX_NATIVE_SIZE) {
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1504 if (opts->code_end-opts->cur_code < 5) {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1505 puts("out of code memory, not enough space for jmp to next chunk");
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1506 exit(1);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1507 }
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1508 size_t size = 1024*1024;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1509 opts->cur_code = alloc_code(&size);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1510 opts->code_end = opts->cur_code + size;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1511 jmp(opts->cur_code, opts->cur_code);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1512 }
255 572b935dd030 Properly handle wrapping around to 0 in translate_z80_stream Mike Pavone <pavone@retrodev.com> parents: 254 diff changeset	1513 if (address > 0x4000 && address < 0x8000) {
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1514 opts->cur_code = xor_rr(opts->cur_code, RDI, RDI, SZ_D);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1515 opts->cur_code = call(opts->cur_code, (uint8_t *)exit);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1516 break;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1517 }
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1518 uint8_t * existing = z80_get_native_address(context, address);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1519 if (existing) {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1520 opts->cur_code = jmp(opts->cur_code, existing);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1521 break;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1522 }
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1523 next = z80_decode(encoded, &inst);
268 6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	1524 #ifdef DO_DEBUG_PRINT
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1525 z80_disasm(&inst, disbuf);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1526 if (inst.op == Z80_NOP) {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1527 printf("%X\t%s(%d)\n", address, disbuf, inst.immed);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1528 } else {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1529 printf("%X\t%s\n", address, disbuf);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1530 }
268 6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	1531 #endif
248 9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	1532 uint8_t *after = translate_z80inst(&inst, opts->cur_code, context, address);
252 63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1533 z80_map_native_address(context, address, opts->cur_code, next-encoded, after - opts->cur_code);
248 9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	1534 opts->cur_code = after;
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1535 address += next-encoded;
255 572b935dd030 Properly handle wrapping around to 0 in translate_z80_stream Mike Pavone <pavone@retrodev.com> parents: 254 diff changeset	1536 if (address > 0xFFFF) {
572b935dd030 Properly handle wrapping around to 0 in translate_z80_stream Mike Pavone <pavone@retrodev.com> parents: 254 diff changeset	1537 address &= 0xFFFF;
572b935dd030 Properly handle wrapping around to 0 in translate_z80_stream Mike Pavone <pavone@retrodev.com> parents: 254 diff changeset	1538
572b935dd030 Properly handle wrapping around to 0 in translate_z80_stream Mike Pavone <pavone@retrodev.com> parents: 254 diff changeset	1539 } else {
572b935dd030 Properly handle wrapping around to 0 in translate_z80_stream Mike Pavone <pavone@retrodev.com> parents: 254 diff changeset	1540 encoded = next;
572b935dd030 Properly handle wrapping around to 0 in translate_z80_stream Mike Pavone <pavone@retrodev.com> parents: 254 diff changeset	1541 }
254 64feb6b67244 Fix bug in end condition inside translate_z80_stream. Mike Pavone <pavone@retrodev.com> parents: 253 diff changeset	1542 } while (!(inst.op == Z80_RET \|\| inst.op == Z80_RETI \|\| inst.op == Z80_RETN \|\| inst.op == Z80_JP \|\| (inst.op == Z80_NOP && inst.immed == 42)));
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1543 process_deferred(&opts->deferred, context, (native_addr_func)z80_get_native_address);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1544 if (opts->deferred) {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1545 address = opts->deferred->address;
268 6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	1546 dprintf("defferred address: %X\n", address);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1547 if (address < 0x4000) {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1548 encoded = context->mem_pointers[0] + (address & 0x1FFF);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1549 } else if (address > 0x8000 && context->mem_pointers[1]) {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1550 encoded = context->mem_pointers[1] + (address & 0x7FFF);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1551 } else {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1552 printf("attempt to translate non-memory address: %X\n", address);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1553 exit(1);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1554 }
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1555 } else {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1556 encoded = NULL;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1557 }
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1558 }
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	1559 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	1560
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1561 void init_x86_z80_opts(x86_z80_options * options)
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	1562 {
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1563 options->flags = 0;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1564 options->regs[Z80_B] = BH;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1565 options->regs[Z80_C] = RBX;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1566 options->regs[Z80_D] = CH;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1567 options->regs[Z80_E] = RCX;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1568 options->regs[Z80_H] = AH;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1569 options->regs[Z80_L] = RAX;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1570 options->regs[Z80_IXH] = DH;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1571 options->regs[Z80_IXL] = RDX;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1572 options->regs[Z80_IYH] = -1;
239 a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	1573 options->regs[Z80_IYL] = R8;
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1574 options->regs[Z80_I] = -1;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1575 options->regs[Z80_R] = -1;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1576 options->regs[Z80_A] = R10;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1577 options->regs[Z80_BC] = RBX;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1578 options->regs[Z80_DE] = RCX;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1579 options->regs[Z80_HL] = RAX;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1580 options->regs[Z80_SP] = R9;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1581 options->regs[Z80_AF] = -1;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1582 options->regs[Z80_IX] = RDX;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1583 options->regs[Z80_IY] = R8;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1584 size_t size = 1024 * 1024;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1585 options->cur_code = alloc_code(&size);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1586 options->code_end = options->cur_code + size;
252 63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1587 options->ram_inst_sizes = malloc(sizeof(uint8_t) * 0x2000);
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1588 memset(options->ram_inst_sizes, 0, sizeof(uint8_t) * 0x2000);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1589 options->deferred = NULL;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	1590 }
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1591
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1592 void init_z80_context(z80_context * context, x86_z80_options * options)
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1593 {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1594 memset(context, 0, sizeof(*context));
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1595 context->static_code_map = malloc(sizeof(context->static_code_map));
259 d9417261366f Fix a remaining z80_write reg swap bug. Properly initialize the native map slots. Reset appropriate regs when z80_reset is called. Mike Pavone <pavone@retrodev.com> parents: 257 diff changeset	1596 context->static_code_map->base = NULL;
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1597 context->static_code_map->offsets = malloc(sizeof(int32_t) * 0x2000);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1598 memset(context->static_code_map->offsets, 0xFF, sizeof(int32_t) * 0x2000);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1599 context->banked_code_map = malloc(sizeof(native_map_slot) * (1 << 9));
259 d9417261366f Fix a remaining z80_write reg swap bug. Properly initialize the native map slots. Reset appropriate regs when z80_reset is called. Mike Pavone <pavone@retrodev.com> parents: 257 diff changeset	1600 memset(context->banked_code_map, 0, sizeof(native_map_slot) * (1 << 9));
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1601 context->options = options;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1602 }
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1603
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1604 void z80_reset(z80_context * context)
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1605 {
259 d9417261366f Fix a remaining z80_write reg swap bug. Properly initialize the native map slots. Reset appropriate regs when z80_reset is called. Mike Pavone <pavone@retrodev.com> parents: 257 diff changeset	1606 context->im = 0;
d9417261366f Fix a remaining z80_write reg swap bug. Properly initialize the native map slots. Reset appropriate regs when z80_reset is called. Mike Pavone <pavone@retrodev.com> parents: 257 diff changeset	1607 context->iff1 = context->iff2 = 0;
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1608 context->native_pc = z80_get_native_address_trans(context, 0);
268 6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	1609 context->extra_pc = NULL;
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1610 }
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1611
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1612

Mercurial > repos > blastem

annotate z80_to_x86.c @ 272:9b04b57434b5