repos/blastem: z80_to_x86.c annotate

annotate z80_to_x86.c @ 590:ea80559c67cb

WIP effort to update z80 core for code gen changes

author	Michael Pavone <pavone@retrodev.com>
date	Sun, 14 Dec 2014 16:45:23 -0800
parents	a3b48a57e847
children	966b46c68942

rev	line source
467 140af5509ce7 Added copyright notice to source files and added GPL license text in COPYING Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	1 /*
140af5509ce7 Added copyright notice to source files and added GPL license text in COPYING Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	2 Copyright 2013 Michael Pavone
505 b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 467 diff changeset	3 This file is part of BlastEm.
467 140af5509ce7 Added copyright notice to source files and added GPL license text in COPYING Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	4 BlastEm is free software distributed under the terms of the GNU General Public License version 3 or greater. See COPYING for full license text.
140af5509ce7 Added copyright notice to source files and added GPL license text in COPYING Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	5 */
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	6 #include "z80inst.h"
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	7 #include "z80_to_x86.h"
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	8 #include "gen_x86.h"
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	9 #include "mem.h"
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	10 #include <stdio.h>
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	11 #include <stdlib.h>
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	12 #include <stddef.h>
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	13 #include <string.h>
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	14
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	15 #define MODE_UNUSED (MODE_IMMED-1)
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	16
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	17 #define ZCYCLES RBP
250 5f1b68cecfc7 Implemented basic interrupt support in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 248 diff changeset	18 #define ZLIMIT RDI
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	19 #define SCRATCH1 R13
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	20 #define SCRATCH2 R14
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	21 #define CONTEXT RSI
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	22
315 684e71e9f0d0 Fix return address for RST Mike Pavone <pavone@retrodev.com> parents: 314 diff changeset	23 //#define DO_DEBUG_PRINT
275 1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	24
268 6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	25 #ifdef DO_DEBUG_PRINT
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	26 #define dprintf printf
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	27 #else
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	28 #define dprintf
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	29 #endif
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	30
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	31 void z80_read_byte();
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	32 void z80_read_word();
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	33 void z80_write_byte();
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	34 void z80_write_word_highfirst();
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	35 void z80_write_word_lowfirst();
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	36 void z80_save_context();
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	37 void z80_native_addr();
250 5f1b68cecfc7 Implemented basic interrupt support in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 248 diff changeset	38 void z80_do_sync();
5f1b68cecfc7 Implemented basic interrupt support in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 248 diff changeset	39 void z80_handle_cycle_limit_int();
252 63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	40 void z80_retrans_stub();
284 ed7098f717d7 Implement IN and OUT (untested) Mike Pavone <pavone@retrodev.com> parents: 283 diff changeset	41 void z80_io_read();
ed7098f717d7 Implement IN and OUT (untested) Mike Pavone <pavone@retrodev.com> parents: 283 diff changeset	42 void z80_io_write();
285 021aeb6df19b Implement HALT (sort of tested) Mike Pavone <pavone@retrodev.com> parents: 284 diff changeset	43 void z80_halt();
366 836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	44 void z80_save_context();
836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	45 void z80_load_context();
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	46
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	47 uint8_t z80_size(z80inst * inst)
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	48 {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	49 uint8_t reg = (inst->reg & 0x1F);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	50 if (reg != Z80_UNUSED && reg != Z80_USE_IMMED) {
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	51 return reg < Z80_BC ? SZ_B : SZ_W;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	52 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	53 //TODO: Handle any necessary special cases
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	54 return SZ_B;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	55 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	56
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	57 void translate_z80_reg(z80inst * inst, x86_ea * ea, z80_options * opts)
250 5f1b68cecfc7 Implemented basic interrupt support in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 248 diff changeset	58 {
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	59 code_info *code = &opts->gen.code;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	60 if (inst->reg == Z80_USE_IMMED) {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	61 ea->mode = MODE_IMMED;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	62 ea->disp = inst->immed;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	63 } else if ((inst->reg & 0x1F) == Z80_UNUSED) {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	64 ea->mode = MODE_UNUSED;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	65 } else {
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	66 ea->mode = MODE_REG_DIRECT;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	67 if (inst->reg == Z80_IYH) {
312 cf7ecda060c7 Properly handle instructions that use boty IYH and IYL Mike Pavone <pavone@retrodev.com> parents: 311 diff changeset	68 if ((inst->addr_mode & 0x1F) == Z80_REG && inst->ea_reg == Z80_IYL) {
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	69 mov_rr(code, opts->regs[Z80_IY], opts->gen.scratch1, SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	70 ror_ir(code, 8, opts->gen.scratch1, SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	71 ea->base = opts->gen.scratch1;
312 cf7ecda060c7 Properly handle instructions that use boty IYH and IYL Mike Pavone <pavone@retrodev.com> parents: 311 diff changeset	72 } else {
cf7ecda060c7 Properly handle instructions that use boty IYH and IYL Mike Pavone <pavone@retrodev.com> parents: 311 diff changeset	73 ea->base = opts->regs[Z80_IYL];
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	74 ror_ir(code, 8, opts->regs[Z80_IY], SZ_W);
312 cf7ecda060c7 Properly handle instructions that use boty IYH and IYL Mike Pavone <pavone@retrodev.com> parents: 311 diff changeset	75 }
262 d97c9eca49f4 Implement ld to and from the I and R registers Mike Pavone <pavone@retrodev.com> parents: 261 diff changeset	76 } else if(opts->regs[inst->reg] >= 0) {
d97c9eca49f4 Implement ld to and from the I and R registers Mike Pavone <pavone@retrodev.com> parents: 261 diff changeset	77 ea->base = opts->regs[inst->reg];
268 6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	78 if (ea->base >= AH && ea->base <= BH) {
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	79 if ((inst->addr_mode & 0x1F) == Z80_REG) {
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	80 uint8_t other_reg = opts->regs[inst->ea_reg];
269 3c054d977175 Fix IX/IY displace modes. Fix check for registers requiring REX. Mike Pavone <pavone@retrodev.com> parents: 268 diff changeset	81 if (other_reg >= R8 \|\| (other_reg >= RSP && other_reg <= RDI)) {
268 6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	82 //we can't mix an *H reg with a register that requires the REX prefix
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	83 ea->base = opts->regs[z80_low_reg(inst->reg)];
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	84 ror_ir(code, 8, ea->base, SZ_W);
268 6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	85 }
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	86 } else if((inst->addr_mode & 0x1F) != Z80_UNUSED && (inst->addr_mode & 0x1F) != Z80_IMMED) {
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	87 //temp regs require REX prefix too
267 1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	88 ea->base = opts->regs[z80_low_reg(inst->reg)];
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	89 ror_ir(code, 8, ea->base, SZ_W);
267 1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	90 }
1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	91 }
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	92 } else {
262 d97c9eca49f4 Implement ld to and from the I and R registers Mike Pavone <pavone@retrodev.com> parents: 261 diff changeset	93 ea->mode = MODE_REG_DISPLACE8;
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	94 ea->base = opts->gen.context_reg;
262 d97c9eca49f4 Implement ld to and from the I and R registers Mike Pavone <pavone@retrodev.com> parents: 261 diff changeset	95 ea->disp = offsetof(z80_context, regs) + inst->reg;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	96 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	97 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	98 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	99
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	100 void z80_save_reg(z80inst * inst, z80_options * opts)
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	101 {
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	102 code_info *code = &opts->gen.code;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	103 if (inst->reg == Z80_IYH) {
312 cf7ecda060c7 Properly handle instructions that use boty IYH and IYL Mike Pavone <pavone@retrodev.com> parents: 311 diff changeset	104 if ((inst->addr_mode & 0x1F) == Z80_REG && inst->ea_reg == Z80_IYL) {
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	105 ror_ir(code, 8, opts->regs[Z80_IY], SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	106 mov_rr(code, opts->gen.scratch1, opts->regs[Z80_IYL], SZ_B);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	107 ror_ir(code, 8, opts->regs[Z80_IY], SZ_W);
312 cf7ecda060c7 Properly handle instructions that use boty IYH and IYL Mike Pavone <pavone@retrodev.com> parents: 311 diff changeset	108 } else {
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	109 ror_ir(code, 8, opts->regs[Z80_IY], SZ_W);
312 cf7ecda060c7 Properly handle instructions that use boty IYH and IYL Mike Pavone <pavone@retrodev.com> parents: 311 diff changeset	110 }
268 6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	111 } else if (opts->regs[inst->reg] >= AH && opts->regs[inst->reg] <= BH) {
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	112 if ((inst->addr_mode & 0x1F) == Z80_REG) {
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	113 uint8_t other_reg = opts->regs[inst->ea_reg];
269 3c054d977175 Fix IX/IY displace modes. Fix check for registers requiring REX. Mike Pavone <pavone@retrodev.com> parents: 268 diff changeset	114 if (other_reg >= R8 \|\| (other_reg >= RSP && other_reg <= RDI)) {
268 6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	115 //we can't mix an *H reg with a register that requires the REX prefix
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	116 ror_ir(code, 8, opts->regs[z80_low_reg(inst->reg)], SZ_W);
268 6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	117 }
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	118 } else if((inst->addr_mode & 0x1F) != Z80_UNUSED && (inst->addr_mode & 0x1F) != Z80_IMMED) {
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	119 //temp regs require REX prefix too
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	120 ror_ir(code, 8, opts->regs[z80_low_reg(inst->reg)], SZ_W);
267 1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	121 }
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	122 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	123 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	124
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	125 void translate_z80_ea(z80inst * inst, x86_ea * ea, z80_options * opts, uint8_t read, uint8_t modify)
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	126 {
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	127 code_info *code = &opts->gen.code;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	128 uint8_t size, reg, areg;
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	129 ea->mode = MODE_REG_DIRECT;
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	130 areg = read ? opts->gen.scratch1 : opts->gen.scratch2;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	131 switch(inst->addr_mode & 0x1F)
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	132 {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	133 case Z80_REG:
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	134 if (inst->ea_reg == Z80_IYH) {
312 cf7ecda060c7 Properly handle instructions that use boty IYH and IYL Mike Pavone <pavone@retrodev.com> parents: 311 diff changeset	135 if (inst->reg == Z80_IYL) {
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	136 mov_rr(code, opts->regs[Z80_IY], opts->gen.scratch1, SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	137 ror_ir(code, 8, opts->gen.scratch1, SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	138 ea->base = opts->gen.scratch1;
312 cf7ecda060c7 Properly handle instructions that use boty IYH and IYL Mike Pavone <pavone@retrodev.com> parents: 311 diff changeset	139 } else {
cf7ecda060c7 Properly handle instructions that use boty IYH and IYL Mike Pavone <pavone@retrodev.com> parents: 311 diff changeset	140 ea->base = opts->regs[Z80_IYL];
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	141 ror_ir(code, 8, opts->regs[Z80_IY], SZ_W);
312 cf7ecda060c7 Properly handle instructions that use boty IYH and IYL Mike Pavone <pavone@retrodev.com> parents: 311 diff changeset	142 }
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	143 } else {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	144 ea->base = opts->regs[inst->ea_reg];
267 1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	145 if (ea->base >= AH && ea->base <= BH && inst->reg != Z80_UNUSED && inst->reg != Z80_USE_IMMED) {
1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	146 uint8_t other_reg = opts->regs[inst->reg];
269 3c054d977175 Fix IX/IY displace modes. Fix check for registers requiring REX. Mike Pavone <pavone@retrodev.com> parents: 268 diff changeset	147 if (other_reg >= R8 \|\| (other_reg >= RSP && other_reg <= RDI)) {
267 1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	148 //we can't mix an *H reg with a register that requires the REX prefix
1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	149 ea->base = opts->regs[z80_low_reg(inst->ea_reg)];
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	150 ror_ir(code, 8, ea->base, SZ_W);
267 1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	151 }
1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	152 }
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	153 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	154 break;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	155 case Z80_REG_INDIRECT:
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	156 mov_rr(code, opts->regs[inst->ea_reg], areg, SZ_W);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	157 size = z80_size(inst);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	158 if (read) {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	159 if (modify) {
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	160 //push_r(code, opts->gen.scratch1);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	161 mov_rrdisp8(code, opts->gen.scratch1, opts->gen.context_reg, offsetof(z80_context, scratch1), SZ_W);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	162 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	163 if (size == SZ_B) {
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	164 call(code, opts->read_8);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	165 } else {
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	166 dst = call(dst, opts->read_16);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	167 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	168 if (modify) {
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	169 //pop_r(code, opts->gen.scratch2);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	170 mov_rdisp8r(code, opts->gen.context_reg, offsetof(z80_context, scratch1), opts->gen.scratch2, SZ_W);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	171 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	172 }
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	173 ea->base = opts->gen.scratch1;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	174 break;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	175 case Z80_IMMED:
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	176 ea->mode = MODE_IMMED;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	177 ea->disp = inst->immed;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	178 break;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	179 case Z80_IMMED_INDIRECT:
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	180 dst = mov_ir(dst, inst->immed, areg, SZ_W);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	181 size = z80_size(inst);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	182 if (read) {
277 765e132edd71 Using push/pop inside translated code is not compatible with the current way the Z80 core returns to the caller Mike Pavone <pavone@retrodev.com> parents: 275 diff changeset	183 /*if (modify) {
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	184 dst = push_r(dst, opts->gen.scratch1);
277 765e132edd71 Using push/pop inside translated code is not compatible with the current way the Z80 core returns to the caller Mike Pavone <pavone@retrodev.com> parents: 275 diff changeset	185 }*/
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	186 if (size == SZ_B) {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	187 dst = call(dst, (uint8_t *)z80_read_byte);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	188 } else {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	189 dst = call(dst, (uint8_t *)z80_read_word);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	190 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	191 if (modify) {
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	192 //dst = pop_r(dst, opts->gen.scratch2);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	193 dst = mov_ir(dst, inst->immed, opts->gen.scratch2, SZ_W);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	194 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	195 }
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	196 ea->base = opts->gen.scratch1;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	197 break;
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	198 case Z80_IX_DISPLACE:
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	199 case Z80_IY_DISPLACE:
300 9adc1dce39bf Fix IX/IY register selection when the direction bit is set Mike Pavone <pavone@retrodev.com> parents: 299 diff changeset	200 reg = opts->regs[(inst->addr_mode & 0x1F) == Z80_IX_DISPLACE ? Z80_IX : Z80_IY];
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	201 dst = mov_rr(dst, reg, areg, SZ_W);
306 3970006fae90 Properly handle negative displacements in Z80 core Mike Pavone <pavone@retrodev.com> parents: 305 diff changeset	202 dst = add_ir(dst, inst->ea_reg & 0x80 ? inst->ea_reg - 256 : inst->ea_reg, areg, SZ_W);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	203 size = z80_size(inst);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	204 if (read) {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	205 if (modify) {
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	206 //dst = push_r(dst, opts->gen.scratch1);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	207 dst = mov_rrdisp8(dst, opts->gen.scratch1, opts->gen.context_reg, offsetof(z80_context, scratch1), SZ_W);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	208 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	209 if (size == SZ_B) {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	210 dst = call(dst, (uint8_t *)z80_read_byte);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	211 } else {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	212 dst = call(dst, (uint8_t *)z80_read_word);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	213 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	214 if (modify) {
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	215 //dst = pop_r(dst, opts->gen.scratch2);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	216 dst = mov_rdisp8r(dst, opts->gen.context_reg, offsetof(z80_context, scratch1), opts->gen.scratch2, SZ_W);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	217 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	218 }
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	219 ea->base = opts->gen.scratch1;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	220 break;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	221 case Z80_UNUSED:
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	222 ea->mode = MODE_UNUSED;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	223 break;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	224 default:
300 9adc1dce39bf Fix IX/IY register selection when the direction bit is set Mike Pavone <pavone@retrodev.com> parents: 299 diff changeset	225 fprintf(stderr, "Unrecognized Z80 addressing mode %d\n", inst->addr_mode & 0x1F);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	226 exit(1);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	227 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	228 return dst;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	229 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	230
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	231 uint8_t * z80_save_ea(uint8_t * dst, z80inst * inst, z80_options * opts)
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	232 {
267 1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	233 if ((inst->addr_mode & 0x1F) == Z80_REG) {
1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	234 if (inst->ea_reg == Z80_IYH) {
312 cf7ecda060c7 Properly handle instructions that use boty IYH and IYL Mike Pavone <pavone@retrodev.com> parents: 311 diff changeset	235 if (inst->reg == Z80_IYL) {
cf7ecda060c7 Properly handle instructions that use boty IYH and IYL Mike Pavone <pavone@retrodev.com> parents: 311 diff changeset	236 dst = ror_ir(dst, 8, opts->regs[Z80_IY], SZ_W);
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	237 dst = mov_rr(dst, opts->gen.scratch1, opts->regs[Z80_IYL], SZ_B);
312 cf7ecda060c7 Properly handle instructions that use boty IYH and IYL Mike Pavone <pavone@retrodev.com> parents: 311 diff changeset	238 dst = ror_ir(dst, 8, opts->regs[Z80_IY], SZ_W);
cf7ecda060c7 Properly handle instructions that use boty IYH and IYL Mike Pavone <pavone@retrodev.com> parents: 311 diff changeset	239 } else {
cf7ecda060c7 Properly handle instructions that use boty IYH and IYL Mike Pavone <pavone@retrodev.com> parents: 311 diff changeset	240 dst = ror_ir(dst, 8, opts->regs[Z80_IY], SZ_W);
cf7ecda060c7 Properly handle instructions that use boty IYH and IYL Mike Pavone <pavone@retrodev.com> parents: 311 diff changeset	241 }
267 1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	242 } else if (inst->reg != Z80_UNUSED && inst->reg != Z80_USE_IMMED && opts->regs[inst->ea_reg] >= AH && opts->regs[inst->ea_reg] <= BH) {
1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	243 uint8_t other_reg = opts->regs[inst->reg];
269 3c054d977175 Fix IX/IY displace modes. Fix check for registers requiring REX. Mike Pavone <pavone@retrodev.com> parents: 268 diff changeset	244 if (other_reg >= R8 \|\| (other_reg >= RSP && other_reg <= RDI)) {
267 1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	245 //we can't mix an *H reg with a register that requires the REX prefix
1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	246 dst = ror_ir(dst, 8, opts->regs[z80_low_reg(inst->ea_reg)], SZ_W);
1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	247 }
1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	248 }
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	249 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	250 return dst;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	251 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	252
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	253 uint8_t * z80_save_result(uint8_t * dst, z80inst * inst)
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	254 {
253 3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around. Mike Pavone <pavone@retrodev.com> parents: 252 diff changeset	255 switch(inst->addr_mode & 0x1f)
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around. Mike Pavone <pavone@retrodev.com> parents: 252 diff changeset	256 {
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around. Mike Pavone <pavone@retrodev.com> parents: 252 diff changeset	257 case Z80_REG_INDIRECT:
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around. Mike Pavone <pavone@retrodev.com> parents: 252 diff changeset	258 case Z80_IMMED_INDIRECT:
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around. Mike Pavone <pavone@retrodev.com> parents: 252 diff changeset	259 case Z80_IX_DISPLACE:
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around. Mike Pavone <pavone@retrodev.com> parents: 252 diff changeset	260 case Z80_IY_DISPLACE:
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around. Mike Pavone <pavone@retrodev.com> parents: 252 diff changeset	261 if (z80_size(inst) == SZ_B) {
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around. Mike Pavone <pavone@retrodev.com> parents: 252 diff changeset	262 dst = call(dst, (uint8_t *)z80_write_byte);
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around. Mike Pavone <pavone@retrodev.com> parents: 252 diff changeset	263 } else {
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around. Mike Pavone <pavone@retrodev.com> parents: 252 diff changeset	264 dst = call(dst, (uint8_t *)z80_write_word_lowfirst);
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around. Mike Pavone <pavone@retrodev.com> parents: 252 diff changeset	265 }
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	266 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	267 return dst;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	268 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	269
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	270 enum {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	271 DONT_READ=0,
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	272 READ
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	273 };
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	274
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	275 enum {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	276 DONT_MODIFY=0,
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	277 MODIFY
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	278 };
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	279
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	280 uint8_t zf_off(uint8_t flag)
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	281 {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	282 return offsetof(z80_context, flags) + flag;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	283 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	284
241 2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	285 uint8_t zaf_off(uint8_t flag)
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	286 {
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	287 return offsetof(z80_context, alt_flags) + flag;
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	288 }
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	289
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	290 uint8_t zar_off(uint8_t reg)
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	291 {
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	292 return offsetof(z80_context, alt_regs) + reg;
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	293 }
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	294
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	295 void z80_print_regs_exit(z80_context * context)
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	296 {
505 b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 467 diff changeset	297 printf("A: %X\nB: %X\nC: %X\nD: %X\nE: %X\nHL: %X\nIX: %X\nIY: %X\nSP: %X\n\nIM: %d, IFF1: %d, IFF2: %d\n",
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	298 context->regs[Z80_A], context->regs[Z80_B], context->regs[Z80_C],
505 b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 467 diff changeset	299 context->regs[Z80_D], context->regs[Z80_E],
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 467 diff changeset	300 (context->regs[Z80_H] << 8) \| context->regs[Z80_L],
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 467 diff changeset	301 (context->regs[Z80_IXH] << 8) \| context->regs[Z80_IXL],
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 467 diff changeset	302 (context->regs[Z80_IYH] << 8) \| context->regs[Z80_IYL],
243 2f069a0b487e Implement EI, DI and IM in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 242 diff changeset	303 context->sp, context->im, context->iff1, context->iff2);
241 2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	304 puts("--Alternate Regs--");
505 b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 467 diff changeset	305 printf("A: %X\nB: %X\nC: %X\nD: %X\nE: %X\nHL: %X\nIX: %X\nIY: %X\n",
241 2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	306 context->alt_regs[Z80_A], context->alt_regs[Z80_B], context->alt_regs[Z80_C],
505 b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 467 diff changeset	307 context->alt_regs[Z80_D], context->alt_regs[Z80_E],
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 467 diff changeset	308 (context->alt_regs[Z80_H] << 8) \| context->alt_regs[Z80_L],
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 467 diff changeset	309 (context->alt_regs[Z80_IXH] << 8) \| context->alt_regs[Z80_IXL],
241 2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	310 (context->alt_regs[Z80_IYH] << 8) \| context->alt_regs[Z80_IYL]);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	311 exit(0);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	312 }
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	313
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	314 uint8_t * translate_z80inst(z80inst * inst, z80_context * context, uint16_t address)
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	315 {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	316 uint32_t cycles;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	317 x86_ea src_op, dst_op;
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	318 uint8_t size;
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	319 z80_options *opts = context->options;
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	320 uint8_t * start = opts->code.cur;
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	321 check_cycles_int(&opts->gen, address);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	322 switch(inst->op)
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	323 {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	324 case Z80_LD:
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	325 size = z80_size(inst);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	326 switch (inst->addr_mode & 0x1F)
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	327 {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	328 case Z80_REG:
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	329 case Z80_REG_INDIRECT:
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	330 cycles = size == SZ_B ? 4 : 6;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	331 if (inst->ea_reg == Z80_IX \|\| inst->ea_reg == Z80_IY) {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	332 cycles += 4;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	333 }
506 a3b48a57e847 Fix timing of certain ld and jp instructions in the Z80 core Michael Pavone <pavone@retrodev.com> parents: 505 diff changeset	334 if (inst->reg == Z80_I \|\| inst->ea_reg == Z80_I) {
a3b48a57e847 Fix timing of certain ld and jp instructions in the Z80 core Michael Pavone <pavone@retrodev.com> parents: 505 diff changeset	335 cycles += 5;
a3b48a57e847 Fix timing of certain ld and jp instructions in the Z80 core Michael Pavone <pavone@retrodev.com> parents: 505 diff changeset	336 }
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	337 break;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	338 case Z80_IMMED:
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	339 cycles = size == SZ_B ? 7 : 10;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	340 break;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	341 case Z80_IMMED_INDIRECT:
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	342 cycles = 10;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	343 break;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	344 case Z80_IX_DISPLACE:
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	345 case Z80_IY_DISPLACE:
506 a3b48a57e847 Fix timing of certain ld and jp instructions in the Z80 core Michael Pavone <pavone@retrodev.com> parents: 505 diff changeset	346 cycles = 16;
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	347 break;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	348 }
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	349 if ((inst->reg >= Z80_IXL && inst->reg <= Z80_IYH) \|\| inst->reg == Z80_IX \|\| inst->reg == Z80_IY) {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	350 cycles += 4;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	351 }
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	352 dst = cycles(&opts->gen, cycles);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	353 if (inst->addr_mode & Z80_DIR) {
505 b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 467 diff changeset	354 dst = translate_z80_ea(inst, &dst_op, dst, opts, DONT_READ, MODIFY);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	355 dst = translate_z80_reg(inst, &src_op, dst, opts);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	356 } else {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	357 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	358 dst = translate_z80_reg(inst, &dst_op, dst, opts);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	359 }
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	360 if (src_op.mode == MODE_REG_DIRECT) {
262 d97c9eca49f4 Implement ld to and from the I and R registers Mike Pavone <pavone@retrodev.com> parents: 261 diff changeset	361 if(dst_op.mode == MODE_REG_DISPLACE8) {
d97c9eca49f4 Implement ld to and from the I and R registers Mike Pavone <pavone@retrodev.com> parents: 261 diff changeset	362 dst = mov_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, size);
d97c9eca49f4 Implement ld to and from the I and R registers Mike Pavone <pavone@retrodev.com> parents: 261 diff changeset	363 } else {
d97c9eca49f4 Implement ld to and from the I and R registers Mike Pavone <pavone@retrodev.com> parents: 261 diff changeset	364 dst = mov_rr(dst, src_op.base, dst_op.base, size);
d97c9eca49f4 Implement ld to and from the I and R registers Mike Pavone <pavone@retrodev.com> parents: 261 diff changeset	365 }
d97c9eca49f4 Implement ld to and from the I and R registers Mike Pavone <pavone@retrodev.com> parents: 261 diff changeset	366 } else if(src_op.mode == MODE_IMMED) {
d97c9eca49f4 Implement ld to and from the I and R registers Mike Pavone <pavone@retrodev.com> parents: 261 diff changeset	367 dst = mov_ir(dst, src_op.disp, dst_op.base, size);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	368 } else {
262 d97c9eca49f4 Implement ld to and from the I and R registers Mike Pavone <pavone@retrodev.com> parents: 261 diff changeset	369 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, size);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	370 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	371 dst = z80_save_reg(dst, inst, opts);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	372 dst = z80_save_ea(dst, inst, opts);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	373 if (inst->addr_mode & Z80_DIR) {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	374 dst = z80_save_result(dst, inst);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	375 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	376 break;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	377 case Z80_PUSH:
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	378 dst = cycles(&opts->gen, (inst->reg == Z80_IX \|\| inst->reg == Z80_IY) ? 9 : 5);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	379 dst = sub_ir(dst, 2, opts->regs[Z80_SP], SZ_W);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	380 if (inst->reg == Z80_AF) {
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	381 dst = mov_rr(dst, opts->regs[Z80_A], opts->gen.scratch1, SZ_B);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	382 dst = shl_ir(dst, 8, opts->gen.scratch1, SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	383 dst = mov_rdisp8r(dst, opts->gen.context_reg, zf_off(ZF_S), opts->gen.scratch1, SZ_B);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	384 dst = shl_ir(dst, 1, opts->gen.scratch1, SZ_B);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	385 dst = or_rdisp8r(dst, opts->gen.context_reg, zf_off(ZF_Z), opts->gen.scratch1, SZ_B);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	386 dst = shl_ir(dst, 2, opts->gen.scratch1, SZ_B);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	387 dst = or_rdisp8r(dst, opts->gen.context_reg, zf_off(ZF_H), opts->gen.scratch1, SZ_B);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	388 dst = shl_ir(dst, 2, opts->gen.scratch1, SZ_B);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	389 dst = or_rdisp8r(dst, opts->gen.context_reg, zf_off(ZF_PV), opts->gen.scratch1, SZ_B);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	390 dst = shl_ir(dst, 1, opts->gen.scratch1, SZ_B);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	391 dst = or_rdisp8r(dst, opts->gen.context_reg, zf_off(ZF_N), opts->gen.scratch1, SZ_B);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	392 dst = shl_ir(dst, 1, opts->gen.scratch1, SZ_B);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	393 dst = or_rdisp8r(dst, opts->gen.context_reg, zf_off(ZF_C), opts->gen.scratch1, SZ_B);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	394 } else {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	395 dst = translate_z80_reg(inst, &src_op, dst, opts);
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	396 dst = mov_rr(dst, src_op.base, opts->gen.scratch1, SZ_W);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	397 }
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	398 dst = mov_rr(dst, opts->regs[Z80_SP], opts->gen.scratch2, SZ_W);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	399 dst = call(dst, (uint8_t *)z80_write_word_highfirst);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	400 //no call to save_z80_reg needed since there's no chance we'll use the only
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	401 //the upper half of a register pair
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	402 break;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	403 case Z80_POP:
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	404 dst = cycles(&opts->gen, (inst->reg == Z80_IX \|\| inst->reg == Z80_IY) ? 8 : 4);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	405 dst = mov_rr(dst, opts->regs[Z80_SP], opts->gen.scratch1, SZ_W);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	406 dst = call(dst, (uint8_t *)z80_read_word);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	407 dst = add_ir(dst, 2, opts->regs[Z80_SP], SZ_W);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	408 if (inst->reg == Z80_AF) {
505 b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 467 diff changeset	409
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	410 dst = bt_ir(dst, 0, opts->gen.scratch1, SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	411 dst = setcc_rdisp8(dst, CC_C, opts->gen.context_reg, zf_off(ZF_C));
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	412 dst = bt_ir(dst, 1, opts->gen.scratch1, SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	413 dst = setcc_rdisp8(dst, CC_C, opts->gen.context_reg, zf_off(ZF_N));
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	414 dst = bt_ir(dst, 2, opts->gen.scratch1, SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	415 dst = setcc_rdisp8(dst, CC_C, opts->gen.context_reg, zf_off(ZF_PV));
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	416 dst = bt_ir(dst, 4, opts->gen.scratch1, SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	417 dst = setcc_rdisp8(dst, CC_C, opts->gen.context_reg, zf_off(ZF_H));
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	418 dst = bt_ir(dst, 6, opts->gen.scratch1, SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	419 dst = setcc_rdisp8(dst, CC_C, opts->gen.context_reg, zf_off(ZF_Z));
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	420 dst = bt_ir(dst, 7, opts->gen.scratch1, SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	421 dst = setcc_rdisp8(dst, CC_C, opts->gen.context_reg, zf_off(ZF_S));
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	422 dst = shr_ir(dst, 8, opts->gen.scratch1, SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	423 dst = mov_rr(dst, opts->gen.scratch1, opts->regs[Z80_A], SZ_B);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	424 } else {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	425 dst = translate_z80_reg(inst, &src_op, dst, opts);
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	426 dst = mov_rr(dst, opts->gen.scratch1, src_op.base, SZ_W);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	427 }
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	428 //no call to save_z80_reg needed since there's no chance we'll use the only
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	429 //the upper half of a register pair
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	430 break;
241 2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	431 case Z80_EX:
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	432 if (inst->addr_mode == Z80_REG \|\| inst->reg == Z80_HL) {
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	433 cycles = 4;
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	434 } else {
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	435 cycles = 8;
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	436 }
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	437 dst = cycles(&opts->gen, cycles);
241 2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	438 if (inst->addr_mode == Z80_REG) {
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	439 if(inst->reg == Z80_AF) {
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	440 dst = mov_rr(dst, opts->regs[Z80_A], opts->gen.scratch1, SZ_B);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	441 dst = mov_rdisp8r(dst, opts->gen.context_reg, zar_off(Z80_A), opts->regs[Z80_A], SZ_B);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	442 dst = mov_rrdisp8(dst, opts->gen.scratch1, opts->gen.context_reg, zar_off(Z80_A), SZ_B);
505 b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 467 diff changeset	443
241 2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	444 //Flags are currently word aligned, so we can move
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	445 //them efficiently a word at a time
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	446 for (int f = ZF_C; f < ZF_NUM; f+=2) {
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	447 dst = mov_rdisp8r(dst, opts->gen.context_reg, zf_off(f), opts->gen.scratch1, SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	448 dst = mov_rdisp8r(dst, opts->gen.context_reg, zaf_off(f), opts->gen.scratch2, SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	449 dst = mov_rrdisp8(dst, opts->gen.scratch1, opts->gen.context_reg, zaf_off(f), SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	450 dst = mov_rrdisp8(dst, opts->gen.scratch2, opts->gen.context_reg, zf_off(f), SZ_W);
241 2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	451 }
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	452 } else {
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	453 dst = xchg_rr(dst, opts->regs[Z80_DE], opts->regs[Z80_HL], SZ_W);
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	454 }
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	455 } else {
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	456 dst = mov_rr(dst, opts->regs[Z80_SP], opts->gen.scratch1, SZ_W);
241 2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	457 dst = call(dst, (uint8_t *)z80_read_byte);
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	458 dst = xchg_rr(dst, opts->regs[inst->reg], opts->gen.scratch1, SZ_B);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	459 dst = mov_rr(dst, opts->regs[Z80_SP], opts->gen.scratch2, SZ_W);
241 2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	460 dst = call(dst, (uint8_t *)z80_write_byte);
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	461 dst = cycles(&opts->gen, 1);
241 2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	462 uint8_t high_reg = z80_high_reg(inst->reg);
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	463 uint8_t use_reg;
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	464 //even though some of the upper halves can be used directly
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	465 //the limitations on mixing *H regs with the REX prefix
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	466 //prevent us from taking advantage of it
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	467 use_reg = opts->regs[inst->reg];
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	468 dst = ror_ir(dst, 8, use_reg, SZ_W);
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	469 dst = mov_rr(dst, opts->regs[Z80_SP], opts->gen.scratch1, SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	470 dst = add_ir(dst, 1, opts->gen.scratch1, SZ_W);
241 2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	471 dst = call(dst, (uint8_t *)z80_read_byte);
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	472 dst = xchg_rr(dst, use_reg, opts->gen.scratch1, SZ_B);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	473 dst = mov_rr(dst, opts->regs[Z80_SP], opts->gen.scratch2, SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	474 dst = add_ir(dst, 1, opts->gen.scratch2, SZ_W);
241 2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	475 dst = call(dst, (uint8_t *)z80_write_byte);
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	476 //restore reg to normal rotation
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	477 dst = ror_ir(dst, 8, use_reg, SZ_W);
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	478 dst = cycles(&opts->gen, 2);
241 2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	479 }
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	480 break;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	481 case Z80_EXX:
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	482 dst = cycles(&opts->gen, 4);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	483 dst = mov_rr(dst, opts->regs[Z80_BC], opts->gen.scratch1, SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	484 dst = mov_rr(dst, opts->regs[Z80_HL], opts->gen.scratch2, SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	485 dst = mov_rdisp8r(dst, opts->gen.context_reg, zar_off(Z80_C), opts->regs[Z80_BC], SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	486 dst = mov_rdisp8r(dst, opts->gen.context_reg, zar_off(Z80_L), opts->regs[Z80_HL], SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	487 dst = mov_rrdisp8(dst, opts->gen.scratch1, opts->gen.context_reg, zar_off(Z80_C), SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	488 dst = mov_rrdisp8(dst, opts->gen.scratch2, opts->gen.context_reg, zar_off(Z80_L), SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	489 dst = mov_rr(dst, opts->regs[Z80_DE], opts->gen.scratch1, SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	490 dst = mov_rdisp8r(dst, opts->gen.context_reg, zar_off(Z80_E), opts->regs[Z80_DE], SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	491 dst = mov_rrdisp8(dst, opts->gen.scratch1, opts->gen.context_reg, zar_off(Z80_E), SZ_W);
241 2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	492 break;
272 9b04b57434b5 Implement LDI Mike Pavone <pavone@retrodev.com> parents: 269 diff changeset	493 case Z80_LDI: {
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	494 dst = cycles(&opts->gen, 8);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	495 dst = mov_rr(dst, opts->regs[Z80_HL], opts->gen.scratch1, SZ_W);
272 9b04b57434b5 Implement LDI Mike Pavone <pavone@retrodev.com> parents: 269 diff changeset	496 dst = call(dst, (uint8_t *)z80_read_byte);
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	497 dst = mov_rr(dst, opts->regs[Z80_DE], opts->gen.scratch2, SZ_W);
385 e45327305bb7 Fix LDI Mike Pavone <pavone@retrodev.com> parents: 384 diff changeset	498 dst = call(dst, (uint8_t *)z80_write_byte);
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	499 dst = cycles(&opts->gen, 2);
272 9b04b57434b5 Implement LDI Mike Pavone <pavone@retrodev.com> parents: 269 diff changeset	500 dst = add_ir(dst, 1, opts->regs[Z80_DE], SZ_W);
9b04b57434b5 Implement LDI Mike Pavone <pavone@retrodev.com> parents: 269 diff changeset	501 dst = add_ir(dst, 1, opts->regs[Z80_HL], SZ_W);
9b04b57434b5 Implement LDI Mike Pavone <pavone@retrodev.com> parents: 269 diff changeset	502 dst = sub_ir(dst, 1, opts->regs[Z80_BC], SZ_W);
9b04b57434b5 Implement LDI Mike Pavone <pavone@retrodev.com> parents: 269 diff changeset	503 //TODO: Implement half-carry
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	504 dst = mov_irdisp8(dst, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	505 dst = setcc_rdisp8(dst, CC_NZ, opts->gen.context_reg, zf_off(ZF_PV));
272 9b04b57434b5 Implement LDI Mike Pavone <pavone@retrodev.com> parents: 269 diff changeset	506 break;
9b04b57434b5 Implement LDI Mike Pavone <pavone@retrodev.com> parents: 269 diff changeset	507 }
261 f0c53a4bbfa3 Implement LDIR and fix a bug in which context was not restored after a call to z80_handle_code_write Mike Pavone <pavone@retrodev.com> parents: 259 diff changeset	508 case Z80_LDIR: {
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	509 dst = cycles(&opts->gen, 8);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	510 dst = mov_rr(dst, opts->regs[Z80_HL], opts->gen.scratch1, SZ_W);
261 f0c53a4bbfa3 Implement LDIR and fix a bug in which context was not restored after a call to z80_handle_code_write Mike Pavone <pavone@retrodev.com> parents: 259 diff changeset	511 dst = call(dst, (uint8_t *)z80_read_byte);
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	512 dst = mov_rr(dst, opts->regs[Z80_DE], opts->gen.scratch2, SZ_W);
397 c20607e5b272 Fix LDIR Mike Pavone <pavone@retrodev.com> parents: 394 diff changeset	513 dst = call(dst, (uint8_t *)z80_write_byte);
261 f0c53a4bbfa3 Implement LDIR and fix a bug in which context was not restored after a call to z80_handle_code_write Mike Pavone <pavone@retrodev.com> parents: 259 diff changeset	514 dst = add_ir(dst, 1, opts->regs[Z80_DE], SZ_W);
f0c53a4bbfa3 Implement LDIR and fix a bug in which context was not restored after a call to z80_handle_code_write Mike Pavone <pavone@retrodev.com> parents: 259 diff changeset	515 dst = add_ir(dst, 1, opts->regs[Z80_HL], SZ_W);
505 b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 467 diff changeset	516
261 f0c53a4bbfa3 Implement LDIR and fix a bug in which context was not restored after a call to z80_handle_code_write Mike Pavone <pavone@retrodev.com> parents: 259 diff changeset	517 dst = sub_ir(dst, 1, opts->regs[Z80_BC], SZ_W);
f0c53a4bbfa3 Implement LDIR and fix a bug in which context was not restored after a call to z80_handle_code_write Mike Pavone <pavone@retrodev.com> parents: 259 diff changeset	518 uint8_t * cont = dst+1;
f0c53a4bbfa3 Implement LDIR and fix a bug in which context was not restored after a call to z80_handle_code_write Mike Pavone <pavone@retrodev.com> parents: 259 diff changeset	519 dst = jcc(dst, CC_Z, dst+2);
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	520 dst = cycles(&opts->gen, 7);
261 f0c53a4bbfa3 Implement LDIR and fix a bug in which context was not restored after a call to z80_handle_code_write Mike Pavone <pavone@retrodev.com> parents: 259 diff changeset	521 //TODO: Figure out what the flag state should be here
f0c53a4bbfa3 Implement LDIR and fix a bug in which context was not restored after a call to z80_handle_code_write Mike Pavone <pavone@retrodev.com> parents: 259 diff changeset	522 //TODO: Figure out whether an interrupt can interrupt this
f0c53a4bbfa3 Implement LDIR and fix a bug in which context was not restored after a call to z80_handle_code_write Mike Pavone <pavone@retrodev.com> parents: 259 diff changeset	523 dst = jmp(dst, start);
f0c53a4bbfa3 Implement LDIR and fix a bug in which context was not restored after a call to z80_handle_code_write Mike Pavone <pavone@retrodev.com> parents: 259 diff changeset	524 *cont = dst - (cont + 1);
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	525 dst = cycles(&opts->gen, 2);
261 f0c53a4bbfa3 Implement LDIR and fix a bug in which context was not restored after a call to z80_handle_code_write Mike Pavone <pavone@retrodev.com> parents: 259 diff changeset	526 //TODO: Implement half-carry
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	527 dst = mov_irdisp8(dst, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	528 dst = mov_irdisp8(dst, 0, opts->gen.context_reg, zf_off(ZF_PV), SZ_B);
261 f0c53a4bbfa3 Implement LDIR and fix a bug in which context was not restored after a call to z80_handle_code_write Mike Pavone <pavone@retrodev.com> parents: 259 diff changeset	529 break;
f0c53a4bbfa3 Implement LDIR and fix a bug in which context was not restored after a call to z80_handle_code_write Mike Pavone <pavone@retrodev.com> parents: 259 diff changeset	530 }
273 719b9fea2fe9 Implement LDD and LDDR Mike Pavone <pavone@retrodev.com> parents: 272 diff changeset	531 case Z80_LDD: {
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	532 dst = cycles(&opts->gen, 8);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	533 dst = mov_rr(dst, opts->regs[Z80_HL], opts->gen.scratch1, SZ_W);
273 719b9fea2fe9 Implement LDD and LDDR Mike Pavone <pavone@retrodev.com> parents: 272 diff changeset	534 dst = call(dst, (uint8_t *)z80_read_byte);
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	535 dst = mov_rr(dst, opts->regs[Z80_DE], opts->gen.scratch2, SZ_W);
388 228e4c696317 Fix LDD and LDDR Mike Pavone <pavone@retrodev.com> parents: 387 diff changeset	536 dst = call(dst, (uint8_t *)z80_write_byte);
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	537 dst = cycles(&opts->gen, 2);
273 719b9fea2fe9 Implement LDD and LDDR Mike Pavone <pavone@retrodev.com> parents: 272 diff changeset	538 dst = sub_ir(dst, 1, opts->regs[Z80_DE], SZ_W);
719b9fea2fe9 Implement LDD and LDDR Mike Pavone <pavone@retrodev.com> parents: 272 diff changeset	539 dst = sub_ir(dst, 1, opts->regs[Z80_HL], SZ_W);
719b9fea2fe9 Implement LDD and LDDR Mike Pavone <pavone@retrodev.com> parents: 272 diff changeset	540 dst = sub_ir(dst, 1, opts->regs[Z80_BC], SZ_W);
719b9fea2fe9 Implement LDD and LDDR Mike Pavone <pavone@retrodev.com> parents: 272 diff changeset	541 //TODO: Implement half-carry
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	542 dst = mov_irdisp8(dst, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	543 dst = setcc_rdisp8(dst, CC_NZ, opts->gen.context_reg, zf_off(ZF_PV));
273 719b9fea2fe9 Implement LDD and LDDR Mike Pavone <pavone@retrodev.com> parents: 272 diff changeset	544 break;
719b9fea2fe9 Implement LDD and LDDR Mike Pavone <pavone@retrodev.com> parents: 272 diff changeset	545 }
719b9fea2fe9 Implement LDD and LDDR Mike Pavone <pavone@retrodev.com> parents: 272 diff changeset	546 case Z80_LDDR: {
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	547 dst = cycles(&opts->gen, 8);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	548 dst = mov_rr(dst, opts->regs[Z80_HL], opts->gen.scratch1, SZ_W);
273 719b9fea2fe9 Implement LDD and LDDR Mike Pavone <pavone@retrodev.com> parents: 272 diff changeset	549 dst = call(dst, (uint8_t *)z80_read_byte);
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	550 dst = mov_rr(dst, opts->regs[Z80_DE], opts->gen.scratch2, SZ_W);
388 228e4c696317 Fix LDD and LDDR Mike Pavone <pavone@retrodev.com> parents: 387 diff changeset	551 dst = call(dst, (uint8_t *)z80_write_byte);
273 719b9fea2fe9 Implement LDD and LDDR Mike Pavone <pavone@retrodev.com> parents: 272 diff changeset	552 dst = sub_ir(dst, 1, opts->regs[Z80_DE], SZ_W);
719b9fea2fe9 Implement LDD and LDDR Mike Pavone <pavone@retrodev.com> parents: 272 diff changeset	553 dst = sub_ir(dst, 1, opts->regs[Z80_HL], SZ_W);
505 b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 467 diff changeset	554
273 719b9fea2fe9 Implement LDD and LDDR Mike Pavone <pavone@retrodev.com> parents: 272 diff changeset	555 dst = sub_ir(dst, 1, opts->regs[Z80_BC], SZ_W);
719b9fea2fe9 Implement LDD and LDDR Mike Pavone <pavone@retrodev.com> parents: 272 diff changeset	556 uint8_t * cont = dst+1;
719b9fea2fe9 Implement LDD and LDDR Mike Pavone <pavone@retrodev.com> parents: 272 diff changeset	557 dst = jcc(dst, CC_Z, dst+2);
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	558 dst = cycles(&opts->gen, 7);
273 719b9fea2fe9 Implement LDD and LDDR Mike Pavone <pavone@retrodev.com> parents: 272 diff changeset	559 //TODO: Figure out what the flag state should be here
719b9fea2fe9 Implement LDD and LDDR Mike Pavone <pavone@retrodev.com> parents: 272 diff changeset	560 //TODO: Figure out whether an interrupt can interrupt this
719b9fea2fe9 Implement LDD and LDDR Mike Pavone <pavone@retrodev.com> parents: 272 diff changeset	561 dst = jmp(dst, start);
719b9fea2fe9 Implement LDD and LDDR Mike Pavone <pavone@retrodev.com> parents: 272 diff changeset	562 *cont = dst - (cont + 1);
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	563 dst = cycles(&opts->gen, 2);
273 719b9fea2fe9 Implement LDD and LDDR Mike Pavone <pavone@retrodev.com> parents: 272 diff changeset	564 //TODO: Implement half-carry
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	565 dst = mov_irdisp8(dst, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	566 dst = mov_irdisp8(dst, 0, opts->gen.context_reg, zf_off(ZF_PV), SZ_B);
273 719b9fea2fe9 Implement LDD and LDDR Mike Pavone <pavone@retrodev.com> parents: 272 diff changeset	567 break;
719b9fea2fe9 Implement LDD and LDDR Mike Pavone <pavone@retrodev.com> parents: 272 diff changeset	568 }
719b9fea2fe9 Implement LDD and LDDR Mike Pavone <pavone@retrodev.com> parents: 272 diff changeset	569 /*case Z80_CPI:
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	570 case Z80_CPIR:
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	571 case Z80_CPD:
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	572 case Z80_CPDR:
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	573 break;*/
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	574 case Z80_ADD:
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	575 cycles = 4;
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	576 if (inst->addr_mode == Z80_IX_DISPLACE \|\| inst->addr_mode == Z80_IY_DISPLACE) {
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	577 cycles += 12;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	578 } else if(inst->addr_mode == Z80_IMMED) {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	579 cycles += 3;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	580 } else if(z80_size(inst) == SZ_W) {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	581 cycles += 4;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	582 }
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	583 dst = cycles(&opts->gen, cycles);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	584 dst = translate_z80_reg(inst, &dst_op, dst, opts);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	585 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	586 if (src_op.mode == MODE_REG_DIRECT) {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	587 dst = add_rr(dst, src_op.base, dst_op.base, z80_size(inst));
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	588 } else {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	589 dst = add_ir(dst, src_op.disp, dst_op.base, z80_size(inst));
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	590 }
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	591 dst = setcc_rdisp8(dst, CC_C, opts->gen.context_reg, zf_off(ZF_C));
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	592 dst = mov_irdisp8(dst, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	593 //TODO: Implement half-carry flag
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	594 if (z80_size(inst) == SZ_B) {
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	595 dst = setcc_rdisp8(dst, CC_O, opts->gen.context_reg, zf_off(ZF_PV));
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	596 dst = setcc_rdisp8(dst, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	597 dst = setcc_rdisp8(dst, CC_S, opts->gen.context_reg, zf_off(ZF_S));
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	598 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	599 dst = z80_save_reg(dst, inst, opts);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	600 dst = z80_save_ea(dst, inst, opts);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	601 break;
248 9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	602 case Z80_ADC:
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	603 cycles = 4;
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	604 if (inst->addr_mode == Z80_IX_DISPLACE \|\| inst->addr_mode == Z80_IY_DISPLACE) {
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	605 cycles += 12;
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	606 } else if(inst->addr_mode == Z80_IMMED) {
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	607 cycles += 3;
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	608 } else if(z80_size(inst) == SZ_W) {
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	609 cycles += 4;
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	610 }
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	611 dst = cycles(&opts->gen, cycles);
248 9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	612 dst = translate_z80_reg(inst, &dst_op, dst, opts);
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	613 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY);
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	614 dst = bt_irdisp8(dst, 0, opts->gen.context_reg, zf_off(ZF_C), SZ_B);
248 9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	615 if (src_op.mode == MODE_REG_DIRECT) {
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	616 dst = adc_rr(dst, src_op.base, dst_op.base, z80_size(inst));
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	617 } else {
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	618 dst = adc_ir(dst, src_op.disp, dst_op.base, z80_size(inst));
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	619 }
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	620 dst = setcc_rdisp8(dst, CC_C, opts->gen.context_reg, zf_off(ZF_C));
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	621 dst = mov_irdisp8(dst, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
248 9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	622 //TODO: Implement half-carry flag
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	623 dst = setcc_rdisp8(dst, CC_O, opts->gen.context_reg, zf_off(ZF_PV));
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	624 dst = setcc_rdisp8(dst, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	625 dst = setcc_rdisp8(dst, CC_S, opts->gen.context_reg, zf_off(ZF_S));
248 9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	626 dst = z80_save_reg(dst, inst, opts);
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	627 dst = z80_save_ea(dst, inst, opts);
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	628 break;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	629 case Z80_SUB:
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	630 cycles = 4;
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	631 if (inst->addr_mode == Z80_IX_DISPLACE \|\| inst->addr_mode == Z80_IY_DISPLACE) {
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	632 cycles += 12;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	633 } else if(inst->addr_mode == Z80_IMMED) {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	634 cycles += 3;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	635 }
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	636 dst = cycles(&opts->gen, cycles);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	637 dst = translate_z80_reg(inst, &dst_op, dst, opts);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	638 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	639 if (src_op.mode == MODE_REG_DIRECT) {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	640 dst = sub_rr(dst, src_op.base, dst_op.base, z80_size(inst));
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	641 } else {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	642 dst = sub_ir(dst, src_op.disp, dst_op.base, z80_size(inst));
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	643 }
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	644 dst = setcc_rdisp8(dst, CC_C, opts->gen.context_reg, zf_off(ZF_C));
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	645 dst = mov_irdisp8(dst, 1, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	646 dst = setcc_rdisp8(dst, CC_O, opts->gen.context_reg, zf_off(ZF_PV));
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	647 //TODO: Implement half-carry flag
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	648 dst = setcc_rdisp8(dst, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	649 dst = setcc_rdisp8(dst, CC_S, opts->gen.context_reg, zf_off(ZF_S));
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	650 dst = z80_save_reg(dst, inst, opts);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	651 dst = z80_save_ea(dst, inst, opts);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	652 break;
248 9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	653 case Z80_SBC:
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	654 cycles = 4;
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	655 if (inst->addr_mode == Z80_IX_DISPLACE \|\| inst->addr_mode == Z80_IY_DISPLACE) {
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	656 cycles += 12;
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	657 } else if(inst->addr_mode == Z80_IMMED) {
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	658 cycles += 3;
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	659 } else if(z80_size(inst) == SZ_W) {
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	660 cycles += 4;
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	661 }
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	662 dst = cycles(&opts->gen, cycles);
248 9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	663 dst = translate_z80_reg(inst, &dst_op, dst, opts);
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	664 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY);
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	665 dst = bt_irdisp8(dst, 0, opts->gen.context_reg, zf_off(ZF_C), SZ_B);
248 9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	666 if (src_op.mode == MODE_REG_DIRECT) {
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	667 dst = sbb_rr(dst, src_op.base, dst_op.base, z80_size(inst));
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	668 } else {
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	669 dst = sbb_ir(dst, src_op.disp, dst_op.base, z80_size(inst));
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	670 }
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	671 dst = setcc_rdisp8(dst, CC_C, opts->gen.context_reg, zf_off(ZF_C));
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	672 dst = mov_irdisp8(dst, 1, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
248 9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	673 //TODO: Implement half-carry flag
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	674 dst = setcc_rdisp8(dst, CC_O, opts->gen.context_reg, zf_off(ZF_PV));
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	675 dst = setcc_rdisp8(dst, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	676 dst = setcc_rdisp8(dst, CC_S, opts->gen.context_reg, zf_off(ZF_S));
248 9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	677 dst = z80_save_reg(dst, inst, opts);
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	678 dst = z80_save_ea(dst, inst, opts);
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	679 break;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	680 case Z80_AND:
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	681 cycles = 4;
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	682 if (inst->addr_mode == Z80_IX_DISPLACE \|\| inst->addr_mode == Z80_IY_DISPLACE) {
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	683 cycles += 12;
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	684 } else if(inst->addr_mode == Z80_IMMED) {
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	685 cycles += 3;
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	686 } else if(z80_size(inst) == SZ_W) {
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	687 cycles += 4;
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	688 }
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	689 dst = cycles(&opts->gen, cycles);
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	690 dst = translate_z80_reg(inst, &dst_op, dst, opts);
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	691 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY);
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	692 if (src_op.mode == MODE_REG_DIRECT) {
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	693 dst = and_rr(dst, src_op.base, dst_op.base, z80_size(inst));
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	694 } else {
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	695 dst = and_ir(dst, src_op.disp, dst_op.base, z80_size(inst));
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	696 }
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	697 //TODO: Cleanup flags
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	698 dst = setcc_rdisp8(dst, CC_C, opts->gen.context_reg, zf_off(ZF_C));
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	699 dst = mov_irdisp8(dst, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	700 //TODO: Implement half-carry flag
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	701 if (z80_size(inst) == SZ_B) {
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	702 dst = setcc_rdisp8(dst, CC_P, opts->gen.context_reg, zf_off(ZF_PV));
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	703 dst = setcc_rdisp8(dst, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	704 dst = setcc_rdisp8(dst, CC_S, opts->gen.context_reg, zf_off(ZF_S));
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	705 }
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	706 dst = z80_save_reg(dst, inst, opts);
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	707 dst = z80_save_ea(dst, inst, opts);
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	708 break;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	709 case Z80_OR:
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	710 cycles = 4;
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	711 if (inst->addr_mode == Z80_IX_DISPLACE \|\| inst->addr_mode == Z80_IY_DISPLACE) {
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	712 cycles += 12;
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	713 } else if(inst->addr_mode == Z80_IMMED) {
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	714 cycles += 3;
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	715 } else if(z80_size(inst) == SZ_W) {
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	716 cycles += 4;
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	717 }
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	718 dst = cycles(&opts->gen, cycles);
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	719 dst = translate_z80_reg(inst, &dst_op, dst, opts);
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	720 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY);
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	721 if (src_op.mode == MODE_REG_DIRECT) {
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	722 dst = or_rr(dst, src_op.base, dst_op.base, z80_size(inst));
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	723 } else {
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	724 dst = or_ir(dst, src_op.disp, dst_op.base, z80_size(inst));
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	725 }
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	726 //TODO: Cleanup flags
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	727 dst = setcc_rdisp8(dst, CC_C, opts->gen.context_reg, zf_off(ZF_C));
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	728 dst = mov_irdisp8(dst, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	729 //TODO: Implement half-carry flag
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	730 if (z80_size(inst) == SZ_B) {
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	731 dst = setcc_rdisp8(dst, CC_P, opts->gen.context_reg, zf_off(ZF_PV));
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	732 dst = setcc_rdisp8(dst, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	733 dst = setcc_rdisp8(dst, CC_S, opts->gen.context_reg, zf_off(ZF_S));
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	734 }
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	735 dst = z80_save_reg(dst, inst, opts);
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	736 dst = z80_save_ea(dst, inst, opts);
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	737 break;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	738 case Z80_XOR:
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	739 cycles = 4;
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	740 if (inst->addr_mode == Z80_IX_DISPLACE \|\| inst->addr_mode == Z80_IY_DISPLACE) {
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	741 cycles += 12;
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	742 } else if(inst->addr_mode == Z80_IMMED) {
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	743 cycles += 3;
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	744 } else if(z80_size(inst) == SZ_W) {
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	745 cycles += 4;
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	746 }
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	747 dst = cycles(&opts->gen, cycles);
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	748 dst = translate_z80_reg(inst, &dst_op, dst, opts);
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	749 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY);
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	750 if (src_op.mode == MODE_REG_DIRECT) {
295 dba661846579 Fix stupid copy-pasta bug in XOR Mike Pavone <pavone@retrodev.com> parents: 294 diff changeset	751 dst = xor_rr(dst, src_op.base, dst_op.base, z80_size(inst));
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	752 } else {
295 dba661846579 Fix stupid copy-pasta bug in XOR Mike Pavone <pavone@retrodev.com> parents: 294 diff changeset	753 dst = xor_ir(dst, src_op.disp, dst_op.base, z80_size(inst));
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	754 }
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	755 //TODO: Cleanup flags
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	756 dst = setcc_rdisp8(dst, CC_C, opts->gen.context_reg, zf_off(ZF_C));
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	757 dst = mov_irdisp8(dst, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	758 //TODO: Implement half-carry flag
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	759 if (z80_size(inst) == SZ_B) {
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	760 dst = setcc_rdisp8(dst, CC_P, opts->gen.context_reg, zf_off(ZF_PV));
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	761 dst = setcc_rdisp8(dst, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	762 dst = setcc_rdisp8(dst, CC_S, opts->gen.context_reg, zf_off(ZF_S));
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	763 }
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	764 dst = z80_save_reg(dst, inst, opts);
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	765 dst = z80_save_ea(dst, inst, opts);
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	766 break;
242 d3b84b2a4397 Implemente CP (untested) Mike Pavone <pavone@retrodev.com> parents: 241 diff changeset	767 case Z80_CP:
d3b84b2a4397 Implemente CP (untested) Mike Pavone <pavone@retrodev.com> parents: 241 diff changeset	768 cycles = 4;
d3b84b2a4397 Implemente CP (untested) Mike Pavone <pavone@retrodev.com> parents: 241 diff changeset	769 if (inst->addr_mode == Z80_IX_DISPLACE \|\| inst->addr_mode == Z80_IY_DISPLACE) {
d3b84b2a4397 Implemente CP (untested) Mike Pavone <pavone@retrodev.com> parents: 241 diff changeset	770 cycles += 12;
d3b84b2a4397 Implemente CP (untested) Mike Pavone <pavone@retrodev.com> parents: 241 diff changeset	771 } else if(inst->addr_mode == Z80_IMMED) {
d3b84b2a4397 Implemente CP (untested) Mike Pavone <pavone@retrodev.com> parents: 241 diff changeset	772 cycles += 3;
d3b84b2a4397 Implemente CP (untested) Mike Pavone <pavone@retrodev.com> parents: 241 diff changeset	773 }
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	774 dst = cycles(&opts->gen, cycles);
242 d3b84b2a4397 Implemente CP (untested) Mike Pavone <pavone@retrodev.com> parents: 241 diff changeset	775 dst = translate_z80_reg(inst, &dst_op, dst, opts);
d3b84b2a4397 Implemente CP (untested) Mike Pavone <pavone@retrodev.com> parents: 241 diff changeset	776 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY);
d3b84b2a4397 Implemente CP (untested) Mike Pavone <pavone@retrodev.com> parents: 241 diff changeset	777 if (src_op.mode == MODE_REG_DIRECT) {
d3b84b2a4397 Implemente CP (untested) Mike Pavone <pavone@retrodev.com> parents: 241 diff changeset	778 dst = cmp_rr(dst, src_op.base, dst_op.base, z80_size(inst));
d3b84b2a4397 Implemente CP (untested) Mike Pavone <pavone@retrodev.com> parents: 241 diff changeset	779 } else {
d3b84b2a4397 Implemente CP (untested) Mike Pavone <pavone@retrodev.com> parents: 241 diff changeset	780 dst = cmp_ir(dst, src_op.disp, dst_op.base, z80_size(inst));
d3b84b2a4397 Implemente CP (untested) Mike Pavone <pavone@retrodev.com> parents: 241 diff changeset	781 }
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	782 dst = setcc_rdisp8(dst, CC_C, opts->gen.context_reg, zf_off(ZF_C));
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	783 dst = mov_irdisp8(dst, 1, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	784 dst = setcc_rdisp8(dst, CC_O, opts->gen.context_reg, zf_off(ZF_PV));
242 d3b84b2a4397 Implemente CP (untested) Mike Pavone <pavone@retrodev.com> parents: 241 diff changeset	785 //TODO: Implement half-carry flag
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	786 dst = setcc_rdisp8(dst, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	787 dst = setcc_rdisp8(dst, CC_S, opts->gen.context_reg, zf_off(ZF_S));
242 d3b84b2a4397 Implemente CP (untested) Mike Pavone <pavone@retrodev.com> parents: 241 diff changeset	788 dst = z80_save_reg(dst, inst, opts);
d3b84b2a4397 Implemente CP (untested) Mike Pavone <pavone@retrodev.com> parents: 241 diff changeset	789 dst = z80_save_ea(dst, inst, opts);
d3b84b2a4397 Implemente CP (untested) Mike Pavone <pavone@retrodev.com> parents: 241 diff changeset	790 break;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	791 case Z80_INC:
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	792 cycles = 4;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	793 if (inst->reg == Z80_IX \|\| inst->reg == Z80_IY) {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	794 cycles += 6;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	795 } else if(z80_size(inst) == SZ_W) {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	796 cycles += 2;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	797 } else if(inst->reg == Z80_IXH \|\| inst->reg == Z80_IXL \|\| inst->reg == Z80_IYH \|\| inst->reg == Z80_IYL \|\| inst->addr_mode == Z80_IX_DISPLACE \|\| inst->addr_mode == Z80_IY_DISPLACE) {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	798 cycles += 4;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	799 }
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	800 dst = cycles(&opts->gen, cycles);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	801 dst = translate_z80_reg(inst, &dst_op, dst, opts);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	802 if (dst_op.mode == MODE_UNUSED) {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	803 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	804 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	805 dst = add_ir(dst, 1, dst_op.base, z80_size(inst));
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	806 if (z80_size(inst) == SZ_B) {
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	807 dst = mov_irdisp8(dst, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	808 //TODO: Implement half-carry flag
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	809 dst = setcc_rdisp8(dst, CC_O, opts->gen.context_reg, zf_off(ZF_PV));
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	810 dst = setcc_rdisp8(dst, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	811 dst = setcc_rdisp8(dst, CC_S, opts->gen.context_reg, zf_off(ZF_S));
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	812 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	813 dst = z80_save_reg(dst, inst, opts);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	814 dst = z80_save_ea(dst, inst, opts);
387 582a68a90708 Fix dec and inc when the operand is in memory Mike Pavone <pavone@retrodev.com> parents: 385 diff changeset	815 dst = z80_save_result(dst, inst);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	816 break;
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	817 case Z80_DEC:
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	818 cycles = 4;
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	819 if (inst->reg == Z80_IX \|\| inst->reg == Z80_IY) {
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	820 cycles += 6;
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	821 } else if(z80_size(inst) == SZ_W) {
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	822 cycles += 2;
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	823 } else if(inst->reg == Z80_IXH \|\| inst->reg == Z80_IXL \|\| inst->reg == Z80_IYH \|\| inst->reg == Z80_IYL \|\| inst->addr_mode == Z80_IX_DISPLACE \|\| inst->addr_mode == Z80_IY_DISPLACE) {
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	824 cycles += 4;
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	825 }
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	826 dst = cycles(&opts->gen, cycles);
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	827 dst = translate_z80_reg(inst, &dst_op, dst, opts);
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	828 if (dst_op.mode == MODE_UNUSED) {
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	829 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY);
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	830 }
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	831 dst = sub_ir(dst, 1, dst_op.base, z80_size(inst));
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	832 if (z80_size(inst) == SZ_B) {
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	833 dst = mov_irdisp8(dst, 1, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	834 //TODO: Implement half-carry flag
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	835 dst = setcc_rdisp8(dst, CC_O, opts->gen.context_reg, zf_off(ZF_PV));
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	836 dst = setcc_rdisp8(dst, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	837 dst = setcc_rdisp8(dst, CC_S, opts->gen.context_reg, zf_off(ZF_S));
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	838 }
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	839 dst = z80_save_reg(dst, inst, opts);
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	840 dst = z80_save_ea(dst, inst, opts);
387 582a68a90708 Fix dec and inc when the operand is in memory Mike Pavone <pavone@retrodev.com> parents: 385 diff changeset	841 dst = z80_save_result(dst, inst);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	842 break;
274 be2b845d3e94 Implement CPL and NEG (untested) Mike Pavone <pavone@retrodev.com> parents: 273 diff changeset	843 //case Z80_DAA:
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	844 case Z80_CPL:
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	845 dst = cycles(&opts->gen, 4);
274 be2b845d3e94 Implement CPL and NEG (untested) Mike Pavone <pavone@retrodev.com> parents: 273 diff changeset	846 dst = not_r(dst, opts->regs[Z80_A], SZ_B);
be2b845d3e94 Implement CPL and NEG (untested) Mike Pavone <pavone@retrodev.com> parents: 273 diff changeset	847 //TODO: Implement half-carry flag
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	848 dst = mov_irdisp8(dst, 1, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
274 be2b845d3e94 Implement CPL and NEG (untested) Mike Pavone <pavone@retrodev.com> parents: 273 diff changeset	849 break;
be2b845d3e94 Implement CPL and NEG (untested) Mike Pavone <pavone@retrodev.com> parents: 273 diff changeset	850 case Z80_NEG:
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	851 dst = cycles(&opts->gen, 8);
274 be2b845d3e94 Implement CPL and NEG (untested) Mike Pavone <pavone@retrodev.com> parents: 273 diff changeset	852 dst = neg_r(dst, opts->regs[Z80_A], SZ_B);
be2b845d3e94 Implement CPL and NEG (untested) Mike Pavone <pavone@retrodev.com> parents: 273 diff changeset	853 //TODO: Implement half-carry flag
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	854 dst = setcc_rdisp8(dst, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	855 dst = setcc_rdisp8(dst, CC_S, opts->gen.context_reg, zf_off(ZF_S));
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	856 dst = setcc_rdisp8(dst, CC_C, opts->gen.context_reg, zf_off(ZF_C));
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	857 dst = setcc_rdisp8(dst, CC_O, opts->gen.context_reg, zf_off(ZF_PV));
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	858 dst = mov_irdisp8(dst, 1, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
274 be2b845d3e94 Implement CPL and NEG (untested) Mike Pavone <pavone@retrodev.com> parents: 273 diff changeset	859 break;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	860 case Z80_CCF:
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	861 dst = cycles(&opts->gen, 4);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	862 dst = xor_irdisp8(dst, 1, opts->gen.context_reg, zf_off(ZF_C), SZ_B);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	863 dst = mov_irdisp8(dst, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
257 4c7933444df4 Implement CCF and SCF Mike Pavone <pavone@retrodev.com> parents: 255 diff changeset	864 //TODO: Implement half-carry flag
4c7933444df4 Implement CCF and SCF Mike Pavone <pavone@retrodev.com> parents: 255 diff changeset	865 break;
4c7933444df4 Implement CCF and SCF Mike Pavone <pavone@retrodev.com> parents: 255 diff changeset	866 case Z80_SCF:
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	867 dst = cycles(&opts->gen, 4);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	868 dst = mov_irdisp8(dst, 1, opts->gen.context_reg, zf_off(ZF_C), SZ_B);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	869 dst = mov_irdisp8(dst, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
257 4c7933444df4 Implement CCF and SCF Mike Pavone <pavone@retrodev.com> parents: 255 diff changeset	870 //TODO: Implement half-carry flag
4c7933444df4 Implement CCF and SCF Mike Pavone <pavone@retrodev.com> parents: 255 diff changeset	871 break;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	872 case Z80_NOP:
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	873 if (inst->immed == 42) {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	874 dst = call(dst, (uint8_t *)z80_save_context);
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	875 dst = mov_rr(dst, opts->gen.context_reg, RDI, SZ_Q);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	876 dst = jmp(dst, (uint8_t *)z80_print_regs_exit);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	877 } else {
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	878 dst = cycles(&opts->gen, 4 * inst->immed);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	879 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	880 break;
285 021aeb6df19b Implement HALT (sort of tested) Mike Pavone <pavone@retrodev.com> parents: 284 diff changeset	881 case Z80_HALT:
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	882 dst = cycles(&opts->gen, 4);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	883 dst = mov_ir(dst, address, opts->gen.scratch1, SZ_W);
285 021aeb6df19b Implement HALT (sort of tested) Mike Pavone <pavone@retrodev.com> parents: 284 diff changeset	884 uint8_t * call_inst = dst;
021aeb6df19b Implement HALT (sort of tested) Mike Pavone <pavone@retrodev.com> parents: 284 diff changeset	885 dst = call(dst, (uint8_t *)z80_halt);
021aeb6df19b Implement HALT (sort of tested) Mike Pavone <pavone@retrodev.com> parents: 284 diff changeset	886 dst = jmp(dst, call_inst);
021aeb6df19b Implement HALT (sort of tested) Mike Pavone <pavone@retrodev.com> parents: 284 diff changeset	887 break;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	888 case Z80_DI:
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	889 dst = cycles(&opts->gen, 4);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	890 dst = mov_irdisp8(dst, 0, opts->gen.context_reg, offsetof(z80_context, iff1), SZ_B);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	891 dst = mov_irdisp8(dst, 0, opts->gen.context_reg, offsetof(z80_context, iff2), SZ_B);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	892 dst = mov_rdisp8r(dst, opts->gen.context_reg, offsetof(z80_context, sync_cycle), opts->gen.limit, SZ_D);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	893 dst = mov_irdisp8(dst, 0xFFFFFFFF, opts->gen.context_reg, offsetof(z80_context, int_cycle), SZ_D);
243 2f069a0b487e Implement EI, DI and IM in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 242 diff changeset	894 break;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	895 case Z80_EI:
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	896 dst = cycles(&opts->gen, 4);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	897 dst = mov_rrdisp32(dst, opts->gen.cycles, opts->gen.context_reg, offsetof(z80_context, int_enable_cycle), SZ_D);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	898 dst = mov_irdisp8(dst, 1, opts->gen.context_reg, offsetof(z80_context, iff1), SZ_B);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	899 dst = mov_irdisp8(dst, 1, opts->gen.context_reg, offsetof(z80_context, iff2), SZ_B);
335 14a937097c2b Some Z80 interrupt fixes Mike Pavone <pavone@retrodev.com> parents: 315 diff changeset	900 //interrupt enable has a one-instruction latency, minimum instruction duration is 4 cycles
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	901 dst = add_irdisp32(dst, 4, opts->gen.context_reg, offsetof(z80_context, int_enable_cycle), SZ_D);
250 5f1b68cecfc7 Implemented basic interrupt support in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 248 diff changeset	902 dst = call(dst, (uint8_t *)z80_do_sync);
243 2f069a0b487e Implement EI, DI and IM in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 242 diff changeset	903 break;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	904 case Z80_IM:
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	905 dst = cycles(&opts->gen, 4);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	906 dst = mov_irdisp8(dst, inst->immed, opts->gen.context_reg, offsetof(z80_context, im), SZ_B);
243 2f069a0b487e Implement EI, DI and IM in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 242 diff changeset	907 break;
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	908 case Z80_RLC:
275 1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	909 cycles = inst->immed == 0 ? 4 : (inst->addr_mode == Z80_IX_DISPLACE \|\| inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8);
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	910 dst = cycles(&opts->gen, cycles);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	911 if (inst->addr_mode != Z80_UNUSED) {
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	912 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	913 dst = translate_z80_reg(inst, &src_op, dst, opts); //For IX/IY variants that also write to a register
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	914 dst = cycles(&opts->gen, 1);
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	915 } else {
302 3b831fe32c15 More fixes for confusion between Z80_UNUSED and MODE_UNUSED Mike Pavone <pavone@retrodev.com> parents: 301 diff changeset	916 src_op.mode = MODE_UNUSED;
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	917 dst = translate_z80_reg(inst, &dst_op, dst, opts);
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	918 }
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	919 dst = rol_ir(dst, 1, dst_op.base, SZ_B);
301 6e15509a1257 Compare src_op.mode with the correct constant in shift/rotate instructions Mike Pavone <pavone@retrodev.com> parents: 300 diff changeset	920 if (src_op.mode != MODE_UNUSED) {
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	921 dst = mov_rr(dst, dst_op.base, src_op.base, SZ_B);
42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	922 }
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	923 dst = setcc_rdisp8(dst, CC_C, opts->gen.context_reg, zf_off(ZF_C));
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	924 dst = mov_irdisp8(dst, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	925 //TODO: Implement half-carry flag
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	926 dst = cmp_ir(dst, 0, dst_op.base, SZ_B);
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	927 dst = setcc_rdisp8(dst, CC_P, opts->gen.context_reg, zf_off(ZF_PV));
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	928 dst = setcc_rdisp8(dst, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	929 dst = setcc_rdisp8(dst, CC_S, opts->gen.context_reg, zf_off(ZF_S));
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	930 if (inst->addr_mode != Z80_UNUSED) {
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	931 dst = z80_save_result(dst, inst);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	932 if (src_op.mode != MODE_UNUSED) {
42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	933 dst = z80_save_reg(dst, inst, opts);
42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	934 }
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	935 } else {
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	936 dst = z80_save_reg(dst, inst, opts);
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	937 }
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	938 break;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	939 case Z80_RL:
275 1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	940 cycles = inst->immed == 0 ? 4 : (inst->addr_mode == Z80_IX_DISPLACE \|\| inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8);
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	941 dst = cycles(&opts->gen, cycles);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	942 if (inst->addr_mode != Z80_UNUSED) {
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	943 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	944 dst = translate_z80_reg(inst, &src_op, dst, opts); //For IX/IY variants that also write to a register
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	945 dst = cycles(&opts->gen, 1);
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	946 } else {
302 3b831fe32c15 More fixes for confusion between Z80_UNUSED and MODE_UNUSED Mike Pavone <pavone@retrodev.com> parents: 301 diff changeset	947 src_op.mode = MODE_UNUSED;
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	948 dst = translate_z80_reg(inst, &dst_op, dst, opts);
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	949 }
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	950 dst = bt_irdisp8(dst, 0, opts->gen.context_reg, zf_off(ZF_C), SZ_B);
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	951 dst = rcl_ir(dst, 1, dst_op.base, SZ_B);
301 6e15509a1257 Compare src_op.mode with the correct constant in shift/rotate instructions Mike Pavone <pavone@retrodev.com> parents: 300 diff changeset	952 if (src_op.mode != MODE_UNUSED) {
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	953 dst = mov_rr(dst, dst_op.base, src_op.base, SZ_B);
42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	954 }
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	955 dst = setcc_rdisp8(dst, CC_C, opts->gen.context_reg, zf_off(ZF_C));
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	956 dst = mov_irdisp8(dst, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	957 //TODO: Implement half-carry flag
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	958 dst = cmp_ir(dst, 0, dst_op.base, SZ_B);
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	959 dst = setcc_rdisp8(dst, CC_P, opts->gen.context_reg, zf_off(ZF_PV));
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	960 dst = setcc_rdisp8(dst, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	961 dst = setcc_rdisp8(dst, CC_S, opts->gen.context_reg, zf_off(ZF_S));
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	962 if (inst->addr_mode != Z80_UNUSED) {
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	963 dst = z80_save_result(dst, inst);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	964 if (src_op.mode != MODE_UNUSED) {
42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	965 dst = z80_save_reg(dst, inst, opts);
42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	966 }
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	967 } else {
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	968 dst = z80_save_reg(dst, inst, opts);
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	969 }
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	970 break;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	971 case Z80_RRC:
275 1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	972 cycles = inst->immed == 0 ? 4 : (inst->addr_mode == Z80_IX_DISPLACE \|\| inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8);
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	973 dst = cycles(&opts->gen, cycles);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	974 if (inst->addr_mode != Z80_UNUSED) {
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	975 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	976 dst = translate_z80_reg(inst, &src_op, dst, opts); //For IX/IY variants that also write to a register
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	977 dst = cycles(&opts->gen, 1);
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	978 } else {
302 3b831fe32c15 More fixes for confusion between Z80_UNUSED and MODE_UNUSED Mike Pavone <pavone@retrodev.com> parents: 301 diff changeset	979 src_op.mode = MODE_UNUSED;
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	980 dst = translate_z80_reg(inst, &dst_op, dst, opts);
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	981 }
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	982 dst = ror_ir(dst, 1, dst_op.base, SZ_B);
301 6e15509a1257 Compare src_op.mode with the correct constant in shift/rotate instructions Mike Pavone <pavone@retrodev.com> parents: 300 diff changeset	983 if (src_op.mode != MODE_UNUSED) {
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	984 dst = mov_rr(dst, dst_op.base, src_op.base, SZ_B);
42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	985 }
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	986 dst = setcc_rdisp8(dst, CC_C, opts->gen.context_reg, zf_off(ZF_C));
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	987 dst = mov_irdisp8(dst, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	988 //TODO: Implement half-carry flag
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	989 dst = cmp_ir(dst, 0, dst_op.base, SZ_B);
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	990 dst = setcc_rdisp8(dst, CC_P, opts->gen.context_reg, zf_off(ZF_PV));
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	991 dst = setcc_rdisp8(dst, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	992 dst = setcc_rdisp8(dst, CC_S, opts->gen.context_reg, zf_off(ZF_S));
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	993 if (inst->addr_mode != Z80_UNUSED) {
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	994 dst = z80_save_result(dst, inst);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	995 if (src_op.mode != MODE_UNUSED) {
42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	996 dst = z80_save_reg(dst, inst, opts);
42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	997 }
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	998 } else {
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	999 dst = z80_save_reg(dst, inst, opts);
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1000 }
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1001 break;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	1002 case Z80_RR:
275 1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1003 cycles = inst->immed == 0 ? 4 : (inst->addr_mode == Z80_IX_DISPLACE \|\| inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8);
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1004 dst = cycles(&opts->gen, cycles);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1005 if (inst->addr_mode != Z80_UNUSED) {
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1006 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1007 dst = translate_z80_reg(inst, &src_op, dst, opts); //For IX/IY variants that also write to a register
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1008 dst = cycles(&opts->gen, 1);
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1009 } else {
302 3b831fe32c15 More fixes for confusion between Z80_UNUSED and MODE_UNUSED Mike Pavone <pavone@retrodev.com> parents: 301 diff changeset	1010 src_op.mode = MODE_UNUSED;
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1011 dst = translate_z80_reg(inst, &dst_op, dst, opts);
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1012 }
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1013 dst = bt_irdisp8(dst, 0, opts->gen.context_reg, zf_off(ZF_C), SZ_B);
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1014 dst = rcr_ir(dst, 1, dst_op.base, SZ_B);
301 6e15509a1257 Compare src_op.mode with the correct constant in shift/rotate instructions Mike Pavone <pavone@retrodev.com> parents: 300 diff changeset	1015 if (src_op.mode != MODE_UNUSED) {
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1016 dst = mov_rr(dst, dst_op.base, src_op.base, SZ_B);
42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1017 }
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1018 dst = setcc_rdisp8(dst, CC_C, opts->gen.context_reg, zf_off(ZF_C));
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1019 dst = mov_irdisp8(dst, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1020 //TODO: Implement half-carry flag
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1021 dst = cmp_ir(dst, 0, dst_op.base, SZ_B);
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1022 dst = setcc_rdisp8(dst, CC_P, opts->gen.context_reg, zf_off(ZF_PV));
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1023 dst = setcc_rdisp8(dst, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1024 dst = setcc_rdisp8(dst, CC_S, opts->gen.context_reg, zf_off(ZF_S));
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1025 if (inst->addr_mode != Z80_UNUSED) {
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1026 dst = z80_save_result(dst, inst);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1027 if (src_op.mode != MODE_UNUSED) {
42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1028 dst = z80_save_reg(dst, inst, opts);
42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1029 }
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1030 } else {
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1031 dst = z80_save_reg(dst, inst, opts);
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1032 }
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1033 break;
275 1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1034 case Z80_SLA:
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	1035 case Z80_SLL:
275 1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1036 cycles = inst->addr_mode == Z80_IX_DISPLACE \|\| inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8;
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1037 dst = cycles(&opts->gen, cycles);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1038 if (inst->addr_mode != Z80_UNUSED) {
275 1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1039 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1040 dst = translate_z80_reg(inst, &src_op, dst, opts); //For IX/IY variants that also write to a register
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1041 dst = cycles(&opts->gen, 1);
275 1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1042 } else {
302 3b831fe32c15 More fixes for confusion between Z80_UNUSED and MODE_UNUSED Mike Pavone <pavone@retrodev.com> parents: 301 diff changeset	1043 src_op.mode = MODE_UNUSED;
275 1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1044 dst = translate_z80_reg(inst, &dst_op, dst, opts);
1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1045 }
1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1046 dst = shl_ir(dst, 1, dst_op.base, SZ_B);
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1047 dst = setcc_rdisp8(dst, CC_C, opts->gen.context_reg, zf_off(ZF_C));
310 bf440db64086 Implement carry flag for shift instructions. Implement weird behavior for bit 0 of SLL. Fix missing break statement in SRL. Mike Pavone <pavone@retrodev.com> parents: 309 diff changeset	1048 if (inst->op == Z80_SLL) {
bf440db64086 Implement carry flag for shift instructions. Implement weird behavior for bit 0 of SLL. Fix missing break statement in SRL. Mike Pavone <pavone@retrodev.com> parents: 309 diff changeset	1049 dst = or_ir(dst, 1, dst_op.base, SZ_B);
bf440db64086 Implement carry flag for shift instructions. Implement weird behavior for bit 0 of SLL. Fix missing break statement in SRL. Mike Pavone <pavone@retrodev.com> parents: 309 diff changeset	1050 }
301 6e15509a1257 Compare src_op.mode with the correct constant in shift/rotate instructions Mike Pavone <pavone@retrodev.com> parents: 300 diff changeset	1051 if (src_op.mode != MODE_UNUSED) {
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1052 dst = mov_rr(dst, dst_op.base, src_op.base, SZ_B);
42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1053 }
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1054 dst = mov_irdisp8(dst, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
275 1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1055 //TODO: Implement half-carry flag
1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1056 dst = cmp_ir(dst, 0, dst_op.base, SZ_B);
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1057 dst = setcc_rdisp8(dst, CC_P, opts->gen.context_reg, zf_off(ZF_PV));
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1058 dst = setcc_rdisp8(dst, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1059 dst = setcc_rdisp8(dst, CC_S, opts->gen.context_reg, zf_off(ZF_S));
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1060 if (inst->addr_mode != Z80_UNUSED) {
275 1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1061 dst = z80_save_result(dst, inst);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1062 if (src_op.mode != MODE_UNUSED) {
42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1063 dst = z80_save_reg(dst, inst, opts);
42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1064 }
275 1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1065 } else {
1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1066 dst = z80_save_reg(dst, inst, opts);
1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1067 }
1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1068 break;
1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1069 case Z80_SRA:
1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1070 cycles = inst->addr_mode == Z80_IX_DISPLACE \|\| inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8;
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1071 dst = cycles(&opts->gen, cycles);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1072 if (inst->addr_mode != Z80_UNUSED) {
275 1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1073 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1074 dst = translate_z80_reg(inst, &src_op, dst, opts); //For IX/IY variants that also write to a register
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1075 dst = cycles(&opts->gen, 1);
275 1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1076 } else {
302 3b831fe32c15 More fixes for confusion between Z80_UNUSED and MODE_UNUSED Mike Pavone <pavone@retrodev.com> parents: 301 diff changeset	1077 src_op.mode = MODE_UNUSED;
275 1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1078 dst = translate_z80_reg(inst, &dst_op, dst, opts);
1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1079 }
1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1080 dst = sar_ir(dst, 1, dst_op.base, SZ_B);
301 6e15509a1257 Compare src_op.mode with the correct constant in shift/rotate instructions Mike Pavone <pavone@retrodev.com> parents: 300 diff changeset	1081 if (src_op.mode != MODE_UNUSED) {
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1082 dst = mov_rr(dst, dst_op.base, src_op.base, SZ_B);
42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1083 }
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1084 dst = setcc_rdisp8(dst, CC_C, opts->gen.context_reg, zf_off(ZF_C));
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1085 dst = mov_irdisp8(dst, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
275 1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1086 //TODO: Implement half-carry flag
1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1087 dst = cmp_ir(dst, 0, dst_op.base, SZ_B);
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1088 dst = setcc_rdisp8(dst, CC_P, opts->gen.context_reg, zf_off(ZF_PV));
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1089 dst = setcc_rdisp8(dst, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1090 dst = setcc_rdisp8(dst, CC_S, opts->gen.context_reg, zf_off(ZF_S));
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1091 if (inst->addr_mode != Z80_UNUSED) {
275 1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1092 dst = z80_save_result(dst, inst);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1093 if (src_op.mode != MODE_UNUSED) {
42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1094 dst = z80_save_reg(dst, inst, opts);
42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1095 }
275 1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1096 } else {
1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1097 dst = z80_save_reg(dst, inst, opts);
1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1098 }
1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1099 break;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	1100 case Z80_SRL:
275 1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1101 cycles = inst->addr_mode == Z80_IX_DISPLACE \|\| inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8;
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1102 dst = cycles(&opts->gen, cycles);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1103 if (inst->addr_mode != Z80_UNUSED) {
275 1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1104 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1105 dst = translate_z80_reg(inst, &src_op, dst, opts); //For IX/IY variants that also write to a register
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1106 dst = cycles(&opts->gen, 1);
275 1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1107 } else {
302 3b831fe32c15 More fixes for confusion between Z80_UNUSED and MODE_UNUSED Mike Pavone <pavone@retrodev.com> parents: 301 diff changeset	1108 src_op.mode = MODE_UNUSED;
275 1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1109 dst = translate_z80_reg(inst, &dst_op, dst, opts);
1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1110 }
1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1111 dst = shr_ir(dst, 1, dst_op.base, SZ_B);
301 6e15509a1257 Compare src_op.mode with the correct constant in shift/rotate instructions Mike Pavone <pavone@retrodev.com> parents: 300 diff changeset	1112 if (src_op.mode != MODE_UNUSED) {
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1113 dst = mov_rr(dst, dst_op.base, src_op.base, SZ_B);
42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1114 }
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1115 dst = setcc_rdisp8(dst, CC_C, opts->gen.context_reg, zf_off(ZF_C));
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1116 dst = mov_irdisp8(dst, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
275 1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1117 //TODO: Implement half-carry flag
1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1118 dst = cmp_ir(dst, 0, dst_op.base, SZ_B);
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1119 dst = setcc_rdisp8(dst, CC_P, opts->gen.context_reg, zf_off(ZF_PV));
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1120 dst = setcc_rdisp8(dst, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1121 dst = setcc_rdisp8(dst, CC_S, opts->gen.context_reg, zf_off(ZF_S));
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1122 if (inst->addr_mode != Z80_UNUSED) {
275 1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1123 dst = z80_save_result(dst, inst);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1124 if (src_op.mode != MODE_UNUSED) {
42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1125 dst = z80_save_reg(dst, inst, opts);
42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1126 }
275 1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1127 } else {
1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1128 dst = z80_save_reg(dst, inst, opts);
1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1129 }
310 bf440db64086 Implement carry flag for shift instructions. Implement weird behavior for bit 0 of SLL. Fix missing break statement in SRL. Mike Pavone <pavone@retrodev.com> parents: 309 diff changeset	1130 break;
286 872a8911e0f4 Implemente RLD Mike Pavone <pavone@retrodev.com> parents: 285 diff changeset	1131 case Z80_RLD:
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1132 dst = cycles(&opts->gen, 8);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1133 dst = mov_rr(dst, opts->regs[Z80_HL], opts->gen.scratch1, SZ_W);
286 872a8911e0f4 Implemente RLD Mike Pavone <pavone@retrodev.com> parents: 285 diff changeset	1134 dst = call(dst, (uint8_t *)z80_read_byte);
872a8911e0f4 Implemente RLD Mike Pavone <pavone@retrodev.com> parents: 285 diff changeset	1135 //Before: (HL) = 0x12, A = 0x34
872a8911e0f4 Implemente RLD Mike Pavone <pavone@retrodev.com> parents: 285 diff changeset	1136 //After: (HL) = 0x24, A = 0x31
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1137 dst = mov_rr(dst, opts->regs[Z80_A], opts->gen.scratch2, SZ_B);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1138 dst = shl_ir(dst, 4, opts->gen.scratch1, SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1139 dst = and_ir(dst, 0xF, opts->gen.scratch2, SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1140 dst = and_ir(dst, 0xFFF, opts->gen.scratch1, SZ_W);
286 872a8911e0f4 Implemente RLD Mike Pavone <pavone@retrodev.com> parents: 285 diff changeset	1141 dst = and_ir(dst, 0xF0, opts->regs[Z80_A], SZ_B);
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1142 dst = or_rr(dst, opts->gen.scratch2, opts->gen.scratch1, SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1143 //opts->gen.scratch1 = 0x0124
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1144 dst = ror_ir(dst, 8, opts->gen.scratch1, SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1145 dst = cycles(&opts->gen, 4);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1146 dst = or_rr(dst, opts->gen.scratch1, opts->regs[Z80_A], SZ_B);
287 fb840e0a48cd Implement RRD and implement flags on RLD Mike Pavone <pavone@retrodev.com> parents: 286 diff changeset	1147 //set flags
fb840e0a48cd Implement RRD and implement flags on RLD Mike Pavone <pavone@retrodev.com> parents: 286 diff changeset	1148 //TODO: Implement half-carry flag
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1149 dst = mov_irdisp8(dst, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1150 dst = setcc_rdisp8(dst, CC_P, opts->gen.context_reg, zf_off(ZF_PV));
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1151 dst = setcc_rdisp8(dst, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1152 dst = setcc_rdisp8(dst, CC_S, opts->gen.context_reg, zf_off(ZF_S));
505 b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 467 diff changeset	1153
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1154 dst = mov_rr(dst, opts->regs[Z80_HL], opts->gen.scratch2, SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1155 dst = ror_ir(dst, 8, opts->gen.scratch1, SZ_W);
286 872a8911e0f4 Implemente RLD Mike Pavone <pavone@retrodev.com> parents: 285 diff changeset	1156 dst = call(dst, (uint8_t *)z80_write_byte);
872a8911e0f4 Implemente RLD Mike Pavone <pavone@retrodev.com> parents: 285 diff changeset	1157 break;
287 fb840e0a48cd Implement RRD and implement flags on RLD Mike Pavone <pavone@retrodev.com> parents: 286 diff changeset	1158 case Z80_RRD:
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1159 dst = cycles(&opts->gen, 8);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1160 dst = mov_rr(dst, opts->regs[Z80_HL], opts->gen.scratch1, SZ_W);
287 fb840e0a48cd Implement RRD and implement flags on RLD Mike Pavone <pavone@retrodev.com> parents: 286 diff changeset	1161 dst = call(dst, (uint8_t *)z80_read_byte);
fb840e0a48cd Implement RRD and implement flags on RLD Mike Pavone <pavone@retrodev.com> parents: 286 diff changeset	1162 //Before: (HL) = 0x12, A = 0x34
fb840e0a48cd Implement RRD and implement flags on RLD Mike Pavone <pavone@retrodev.com> parents: 286 diff changeset	1163 //After: (HL) = 0x41, A = 0x32
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1164 dst = movzx_rr(dst, opts->regs[Z80_A], opts->gen.scratch2, SZ_B, SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1165 dst = ror_ir(dst, 4, opts->gen.scratch1, SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1166 dst = shl_ir(dst, 4, opts->gen.scratch2, SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1167 dst = and_ir(dst, 0xF00F, opts->gen.scratch1, SZ_W);
287 fb840e0a48cd Implement RRD and implement flags on RLD Mike Pavone <pavone@retrodev.com> parents: 286 diff changeset	1168 dst = and_ir(dst, 0xF0, opts->regs[Z80_A], SZ_B);
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1169 //opts->gen.scratch1 = 0x2001
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1170 //opts->gen.scratch2 = 0x0040
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1171 dst = or_rr(dst, opts->gen.scratch2, opts->gen.scratch1, SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1172 //opts->gen.scratch1 = 0x2041
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1173 dst = ror_ir(dst, 8, opts->gen.scratch1, SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1174 dst = cycles(&opts->gen, 4);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1175 dst = shr_ir(dst, 4, opts->gen.scratch1, SZ_B);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1176 dst = or_rr(dst, opts->gen.scratch1, opts->regs[Z80_A], SZ_B);
287 fb840e0a48cd Implement RRD and implement flags on RLD Mike Pavone <pavone@retrodev.com> parents: 286 diff changeset	1177 //set flags
fb840e0a48cd Implement RRD and implement flags on RLD Mike Pavone <pavone@retrodev.com> parents: 286 diff changeset	1178 //TODO: Implement half-carry flag
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1179 dst = mov_irdisp8(dst, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1180 dst = setcc_rdisp8(dst, CC_P, opts->gen.context_reg, zf_off(ZF_PV));
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1181 dst = setcc_rdisp8(dst, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1182 dst = setcc_rdisp8(dst, CC_S, opts->gen.context_reg, zf_off(ZF_S));
505 b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 467 diff changeset	1183
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1184 dst = mov_rr(dst, opts->regs[Z80_HL], opts->gen.scratch2, SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1185 dst = ror_ir(dst, 8, opts->gen.scratch1, SZ_W);
287 fb840e0a48cd Implement RRD and implement flags on RLD Mike Pavone <pavone@retrodev.com> parents: 286 diff changeset	1186 dst = call(dst, (uint8_t *)z80_write_byte);
fb840e0a48cd Implement RRD and implement flags on RLD Mike Pavone <pavone@retrodev.com> parents: 286 diff changeset	1187 break;
308 e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1188 case Z80_BIT: {
239 a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	1189 cycles = (inst->addr_mode == Z80_IX_DISPLACE \|\| inst->addr_mode == Z80_IY_DISPLACE) ? 8 : 16;
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1190 dst = cycles(&opts->gen, cycles);
308 e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1191 uint8_t bit;
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1192 if ((inst->addr_mode & 0x1F) == Z80_REG && opts->regs[inst->ea_reg] >= AH && opts->regs[inst->ea_reg] <= BH) {
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1193 src_op.base = opts->regs[z80_word_reg(inst->ea_reg)];
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1194 size = SZ_W;
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1195 bit = inst->immed + 8;
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1196 } else {
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1197 size = SZ_B;
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1198 bit = inst->immed;
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1199 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY);
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1200 }
239 a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	1201 if (inst->addr_mode != Z80_REG) {
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	1202 //Reads normally take 3 cycles, but the read at the end of a bit instruction takes 4
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1203 dst = cycles(&opts->gen, 1);
239 a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	1204 }
308 e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1205 dst = bt_ir(dst, bit, src_op.base, size);
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1206 dst = setcc_rdisp8(dst, CC_NC, opts->gen.context_reg, zf_off(ZF_Z));
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1207 dst = setcc_rdisp8(dst, CC_NC, opts->gen.context_reg, zf_off(ZF_PV));
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1208 dst = mov_irdisp8(dst, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
307 b6393b89a7e4 Complete flag behavior for Z80 BIT instruction Mike Pavone <pavone@retrodev.com> parents: 306 diff changeset	1209 if (inst->immed == 7) {
308 e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1210 dst = cmp_ir(dst, 0, src_op.base, size);
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1211 dst = setcc_rdisp8(dst, CC_S, opts->gen.context_reg, zf_off(ZF_S));
307 b6393b89a7e4 Complete flag behavior for Z80 BIT instruction Mike Pavone <pavone@retrodev.com> parents: 306 diff changeset	1212 } else {
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1213 dst = mov_irdisp8(dst, 0, opts->gen.context_reg, zf_off(ZF_S), SZ_B);
307 b6393b89a7e4 Complete flag behavior for Z80 BIT instruction Mike Pavone <pavone@retrodev.com> parents: 306 diff changeset	1214 }
239 a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	1215 break;
308 e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1216 }
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1217 case Z80_SET: {
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1218 cycles = (inst->addr_mode == Z80_IX_DISPLACE \|\| inst->addr_mode == Z80_IY_DISPLACE) ? 8 : 16;
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1219 dst = cycles(&opts->gen, cycles);
308 e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1220 uint8_t bit;
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1221 if ((inst->addr_mode & 0x1F) == Z80_REG && opts->regs[inst->ea_reg] >= AH && opts->regs[inst->ea_reg] <= BH) {
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1222 src_op.base = opts->regs[z80_word_reg(inst->ea_reg)];
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1223 size = SZ_W;
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1224 bit = inst->immed + 8;
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1225 } else {
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1226 size = SZ_B;
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1227 bit = inst->immed;
384 5500d1d1269e Fix set/res when the operand is in memory Mike Pavone <pavone@retrodev.com> parents: 373 diff changeset	1228 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, MODIFY);
308 e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1229 }
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1230 if (inst->reg != Z80_USE_IMMED) {
42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1231 dst = translate_z80_reg(inst, &dst_op, dst, opts);
42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1232 }
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1233 if (inst->addr_mode != Z80_REG) {
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1234 //Reads normally take 3 cycles, but the read in the middle of a set instruction takes 4
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1235 dst = cycles(&opts->gen, 1);
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1236 }
308 e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1237 dst = bts_ir(dst, bit, src_op.base, size);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1238 if (inst->reg != Z80_USE_IMMED) {
308 e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1239 if (size == SZ_W) {
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1240 if (dst_op.base >= R8) {
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1241 dst = ror_ir(dst, 8, src_op.base, SZ_W);
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1242 dst = mov_rr(dst, opts->regs[z80_low_reg(inst->ea_reg)], dst_op.base, SZ_B);
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1243 dst = ror_ir(dst, 8, src_op.base, SZ_W);
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1244 } else {
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1245 dst = mov_rr(dst, opts->regs[inst->ea_reg], dst_op.base, SZ_B);
505 b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 467 diff changeset	1246 }
308 e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1247 } else {
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1248 dst = mov_rr(dst, src_op.base, dst_op.base, SZ_B);
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1249 }
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1250 }
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1251 if ((inst->addr_mode & 0x1F) != Z80_REG) {
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1252 dst = z80_save_result(dst, inst);
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1253 if (inst->reg != Z80_USE_IMMED) {
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1254 dst = z80_save_reg(dst, inst, opts);
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1255 }
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1256 }
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1257 break;
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1258 }
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1259 case Z80_RES: {
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1260 cycles = (inst->addr_mode == Z80_IX_DISPLACE \|\| inst->addr_mode == Z80_IY_DISPLACE) ? 8 : 16;
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1261 dst = cycles(&opts->gen, cycles);
308 e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1262 uint8_t bit;
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1263 if ((inst->addr_mode & 0x1F) == Z80_REG && opts->regs[inst->ea_reg] >= AH && opts->regs[inst->ea_reg] <= BH) {
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1264 src_op.base = opts->regs[z80_word_reg(inst->ea_reg)];
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1265 size = SZ_W;
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1266 bit = inst->immed + 8;
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1267 } else {
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1268 size = SZ_B;
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1269 bit = inst->immed;
384 5500d1d1269e Fix set/res when the operand is in memory Mike Pavone <pavone@retrodev.com> parents: 373 diff changeset	1270 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, MODIFY);
308 e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1271 }
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1272 if (inst->reg != Z80_USE_IMMED) {
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1273 dst = translate_z80_reg(inst, &dst_op, dst, opts);
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1274 }
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1275 if (inst->addr_mode != Z80_REG) {
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1276 //Reads normally take 3 cycles, but the read in the middle of a set instruction takes 4
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1277 dst = cycles(&opts->gen, 1);
308 e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1278 }
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1279 dst = btr_ir(dst, bit, src_op.base, size);
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1280 if (inst->reg != Z80_USE_IMMED) {
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1281 if (size == SZ_W) {
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1282 if (dst_op.base >= R8) {
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1283 dst = ror_ir(dst, 8, src_op.base, SZ_W);
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1284 dst = mov_rr(dst, opts->regs[z80_low_reg(inst->ea_reg)], dst_op.base, SZ_B);
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1285 dst = ror_ir(dst, 8, src_op.base, SZ_W);
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1286 } else {
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1287 dst = mov_rr(dst, opts->regs[inst->ea_reg], dst_op.base, SZ_B);
505 b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 467 diff changeset	1288 }
308 e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1289 } else {
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1290 dst = mov_rr(dst, src_op.base, dst_op.base, SZ_B);
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1291 }
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1292 }
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1293 if (inst->addr_mode != Z80_REG) {
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1294 dst = z80_save_result(dst, inst);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1295 if (inst->reg != Z80_USE_IMMED) {
42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1296 dst = z80_save_reg(dst, inst, opts);
42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1297 }
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1298 }
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1299 break;
308 e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1300 }
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1301 case Z80_JP: {
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1302 cycles = 4;
506 a3b48a57e847 Fix timing of certain ld and jp instructions in the Z80 core Michael Pavone <pavone@retrodev.com> parents: 505 diff changeset	1303 if (inst->addr_mode != Z80_REG_INDIRECT) {
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1304 cycles += 6;
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1305 } else if(inst->ea_reg == Z80_IX \|\| inst->ea_reg == Z80_IY) {
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1306 cycles += 4;
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1307 }
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1308 dst = cycles(&opts->gen, cycles);
239 a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	1309 if (inst->addr_mode != Z80_REG_INDIRECT && inst->immed < 0x4000) {
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1310 uint8_t * call_dst = z80_get_native_address(context, inst->immed);
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1311 if (!call_dst) {
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1312 opts->deferred = defer_address(opts->deferred, inst->immed, dst + 1);
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1313 //fake address to force large displacement
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1314 call_dst = dst + 256;
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1315 }
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1316 dst = jmp(dst, call_dst);
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1317 } else {
239 a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	1318 if (inst->addr_mode == Z80_REG_INDIRECT) {
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1319 dst = mov_rr(dst, opts->regs[inst->ea_reg], opts->gen.scratch1, SZ_W);
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1320 } else {
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1321 dst = mov_ir(dst, inst->immed, opts->gen.scratch1, SZ_W);
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1322 }
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1323 dst = call(dst, (uint8_t *)z80_native_addr);
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1324 dst = jmp_r(dst, opts->gen.scratch1);
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1325 }
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1326 break;
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1327 }
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1328 case Z80_JPCC: {
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1329 dst = cycles(&opts->gen, 7);//T States: 4,3
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1330 uint8_t cond = CC_Z;
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1331 switch (inst->reg)
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1332 {
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1333 case Z80_CC_NZ:
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1334 cond = CC_NZ;
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1335 case Z80_CC_Z:
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1336 dst = cmp_irdisp8(dst, 0, opts->gen.context_reg, zf_off(ZF_Z), SZ_B);
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1337 break;
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1338 case Z80_CC_NC:
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1339 cond = CC_NZ;
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1340 case Z80_CC_C:
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1341 dst = cmp_irdisp8(dst, 0, opts->gen.context_reg, zf_off(ZF_C), SZ_B);
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1342 break;
238 827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1343 case Z80_CC_PO:
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1344 cond = CC_NZ;
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1345 case Z80_CC_PE:
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1346 dst = cmp_irdisp8(dst, 0, opts->gen.context_reg, zf_off(ZF_PV), SZ_B);
238 827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1347 break;
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1348 case Z80_CC_P:
367 f20562f2a570 Fix P condition in Z80 core Mike Pavone <pavone@retrodev.com> parents: 366 diff changeset	1349 cond = CC_NZ;
238 827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1350 case Z80_CC_M:
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1351 dst = cmp_irdisp8(dst, 0, opts->gen.context_reg, zf_off(ZF_S), SZ_B);
238 827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1352 break;
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1353 }
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1354 uint8_t *no_jump_off = dst+1;
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1355 dst = jcc(dst, cond, dst+2);
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1356 dst = cycles(&opts->gen, 5);//T States: 5
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1357 uint16_t dest_addr = inst->immed;
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1358 if (dest_addr < 0x4000) {
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1359 uint8_t * call_dst = z80_get_native_address(context, dest_addr);
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1360 if (!call_dst) {
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1361 opts->deferred = defer_address(opts->deferred, dest_addr, dst + 1);
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1362 //fake address to force large displacement
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1363 call_dst = dst + 256;
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1364 }
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1365 dst = jmp(dst, call_dst);
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1366 } else {
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1367 dst = mov_ir(dst, dest_addr, opts->gen.scratch1, SZ_W);
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1368 dst = call(dst, (uint8_t *)z80_native_addr);
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1369 dst = jmp_r(dst, opts->gen.scratch1);
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1370 }
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1371 *no_jump_off = dst - (no_jump_off+1);
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1372 break;
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1373 }
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1374 case Z80_JR: {
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1375 dst = cycles(&opts->gen, 12);//T States: 4,3,5
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1376 uint16_t dest_addr = address + inst->immed + 2;
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1377 if (dest_addr < 0x4000) {
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1378 uint8_t * call_dst = z80_get_native_address(context, dest_addr);
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1379 if (!call_dst) {
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1380 opts->deferred = defer_address(opts->deferred, dest_addr, dst + 1);
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1381 //fake address to force large displacement
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1382 call_dst = dst + 256;
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1383 }
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1384 dst = jmp(dst, call_dst);
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1385 } else {
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1386 dst = mov_ir(dst, dest_addr, opts->gen.scratch1, SZ_W);
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1387 dst = call(dst, (uint8_t *)z80_native_addr);
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1388 dst = jmp_r(dst, opts->gen.scratch1);
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1389 }
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1390 break;
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1391 }
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1392 case Z80_JRCC: {
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1393 dst = cycles(&opts->gen, 7);//T States: 4,3
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1394 uint8_t cond = CC_Z;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1395 switch (inst->reg)
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1396 {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1397 case Z80_CC_NZ:
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1398 cond = CC_NZ;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1399 case Z80_CC_Z:
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1400 dst = cmp_irdisp8(dst, 0, opts->gen.context_reg, zf_off(ZF_Z), SZ_B);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1401 break;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1402 case Z80_CC_NC:
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1403 cond = CC_NZ;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1404 case Z80_CC_C:
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1405 dst = cmp_irdisp8(dst, 0, opts->gen.context_reg, zf_off(ZF_C), SZ_B);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1406 break;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1407 }
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1408 uint8_t *no_jump_off = dst+1;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1409 dst = jcc(dst, cond, dst+2);
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1410 dst = cycles(&opts->gen, 5);//T States: 5
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1411 uint16_t dest_addr = address + inst->immed + 2;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1412 if (dest_addr < 0x4000) {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1413 uint8_t * call_dst = z80_get_native_address(context, dest_addr);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1414 if (!call_dst) {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1415 opts->deferred = defer_address(opts->deferred, dest_addr, dst + 1);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1416 //fake address to force large displacement
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1417 call_dst = dst + 256;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1418 }
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1419 dst = jmp(dst, call_dst);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1420 } else {
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1421 dst = mov_ir(dst, dest_addr, opts->gen.scratch1, SZ_W);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1422 dst = call(dst, (uint8_t *)z80_native_addr);
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1423 dst = jmp_r(dst, opts->gen.scratch1);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1424 }
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1425 *no_jump_off = dst - (no_jump_off+1);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1426 break;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1427 }
239 a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	1428 case Z80_DJNZ:
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1429 dst = cycles(&opts->gen, 8);//T States: 5,3
239 a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	1430 dst = sub_ir(dst, 1, opts->regs[Z80_B], SZ_B);
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	1431 uint8_t *no_jump_off = dst+1;
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	1432 dst = jcc(dst, CC_Z, dst+2);
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1433 dst = cycles(&opts->gen, 5);//T States: 5
239 a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	1434 uint16_t dest_addr = address + inst->immed + 2;
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	1435 if (dest_addr < 0x4000) {
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	1436 uint8_t * call_dst = z80_get_native_address(context, dest_addr);
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	1437 if (!call_dst) {
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	1438 opts->deferred = defer_address(opts->deferred, dest_addr, dst + 1);
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	1439 //fake address to force large displacement
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	1440 call_dst = dst + 256;
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	1441 }
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	1442 dst = jmp(dst, call_dst);
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	1443 } else {
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1444 dst = mov_ir(dst, dest_addr, opts->gen.scratch1, SZ_W);
239 a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	1445 dst = call(dst, (uint8_t *)z80_native_addr);
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1446 dst = jmp_r(dst, opts->gen.scratch1);
239 a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	1447 }
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	1448 *no_jump_off = dst - (no_jump_off+1);
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	1449 break;
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1450 case Z80_CALL: {
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1451 dst = cycles(&opts->gen, 11);//T States: 4,3,4
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1452 dst = sub_ir(dst, 2, opts->regs[Z80_SP], SZ_W);
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1453 dst = mov_ir(dst, address + 3, opts->gen.scratch1, SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1454 dst = mov_rr(dst, opts->regs[Z80_SP], opts->gen.scratch2, SZ_W);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1455 dst = call(dst, (uint8_t *)z80_write_word_highfirst);//T States: 3, 3
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1456 if (inst->immed < 0x4000) {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1457 uint8_t * call_dst = z80_get_native_address(context, inst->immed);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1458 if (!call_dst) {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1459 opts->deferred = defer_address(opts->deferred, inst->immed, dst + 1);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1460 //fake address to force large displacement
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1461 call_dst = dst + 256;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1462 }
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1463 dst = jmp(dst, call_dst);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1464 } else {
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1465 dst = mov_ir(dst, inst->immed, opts->gen.scratch1, SZ_W);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1466 dst = call(dst, (uint8_t *)z80_native_addr);
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1467 dst = jmp_r(dst, opts->gen.scratch1);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1468 }
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1469 break;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1470 }
238 827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1471 case Z80_CALLCC:
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1472 dst = cycles(&opts->gen, 10);//T States: 4,3,3 (false case)
238 827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1473 uint8_t cond = CC_Z;
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1474 switch (inst->reg)
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1475 {
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1476 case Z80_CC_NZ:
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1477 cond = CC_NZ;
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1478 case Z80_CC_Z:
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1479 dst = cmp_irdisp8(dst, 0, opts->gen.context_reg, zf_off(ZF_Z), SZ_B);
238 827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1480 break;
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1481 case Z80_CC_NC:
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1482 cond = CC_NZ;
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1483 case Z80_CC_C:
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1484 dst = cmp_irdisp8(dst, 0, opts->gen.context_reg, zf_off(ZF_C), SZ_B);
238 827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1485 break;
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1486 case Z80_CC_PO:
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1487 cond = CC_NZ;
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1488 case Z80_CC_PE:
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1489 dst = cmp_irdisp8(dst, 0, opts->gen.context_reg, zf_off(ZF_PV), SZ_B);
238 827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1490 break;
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1491 case Z80_CC_P:
367 f20562f2a570 Fix P condition in Z80 core Mike Pavone <pavone@retrodev.com> parents: 366 diff changeset	1492 cond = CC_NZ;
238 827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1493 case Z80_CC_M:
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1494 dst = cmp_irdisp8(dst, 0, opts->gen.context_reg, zf_off(ZF_S), SZ_B);
238 827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1495 break;
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1496 }
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1497 uint8_t *no_call_off = dst+1;
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1498 dst = jcc(dst, cond, dst+2);
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1499 dst = cycles(&opts->gen, 1);//Last of the above T states takes an extra cycle in the true case
238 827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1500 dst = sub_ir(dst, 2, opts->regs[Z80_SP], SZ_W);
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1501 dst = mov_ir(dst, address + 3, opts->gen.scratch1, SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1502 dst = mov_rr(dst, opts->regs[Z80_SP], opts->gen.scratch2, SZ_W);
238 827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1503 dst = call(dst, (uint8_t *)z80_write_word_highfirst);//T States: 3, 3
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1504 if (inst->immed < 0x4000) {
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1505 uint8_t * call_dst = z80_get_native_address(context, inst->immed);
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1506 if (!call_dst) {
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1507 opts->deferred = defer_address(opts->deferred, inst->immed, dst + 1);
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1508 //fake address to force large displacement
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1509 call_dst = dst + 256;
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1510 }
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1511 dst = jmp(dst, call_dst);
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1512 } else {
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1513 dst = mov_ir(dst, inst->immed, opts->gen.scratch1, SZ_W);
238 827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1514 dst = call(dst, (uint8_t *)z80_native_addr);
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1515 dst = jmp_r(dst, opts->gen.scratch1);
238 827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1516 }
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1517 *no_call_off = dst - (no_call_off+1);
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1518 break;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	1519 case Z80_RET:
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1520 dst = cycles(&opts->gen, 4);//T States: 4
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1521 dst = mov_rr(dst, opts->regs[Z80_SP], opts->gen.scratch1, SZ_W);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1522 dst = call(dst, (uint8_t *)z80_read_word);//T STates: 3, 3
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1523 dst = add_ir(dst, 2, opts->regs[Z80_SP], SZ_W);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1524 dst = call(dst, (uint8_t *)z80_native_addr);
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1525 dst = jmp_r(dst, opts->gen.scratch1);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1526 break;
246 ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1527 case Z80_RETCC: {
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1528 dst = cycles(&opts->gen, 5);//T States: 5
246 ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1529 uint8_t cond = CC_Z;
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1530 switch (inst->reg)
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1531 {
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1532 case Z80_CC_NZ:
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1533 cond = CC_NZ;
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1534 case Z80_CC_Z:
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1535 dst = cmp_irdisp8(dst, 0, opts->gen.context_reg, zf_off(ZF_Z), SZ_B);
246 ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1536 break;
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1537 case Z80_CC_NC:
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1538 cond = CC_NZ;
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1539 case Z80_CC_C:
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1540 dst = cmp_irdisp8(dst, 0, opts->gen.context_reg, zf_off(ZF_C), SZ_B);
246 ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1541 break;
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1542 case Z80_CC_PO:
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1543 cond = CC_NZ;
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1544 case Z80_CC_PE:
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1545 dst = cmp_irdisp8(dst, 0, opts->gen.context_reg, zf_off(ZF_PV), SZ_B);
246 ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1546 break;
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1547 case Z80_CC_P:
367 f20562f2a570 Fix P condition in Z80 core Mike Pavone <pavone@retrodev.com> parents: 366 diff changeset	1548 cond = CC_NZ;
246 ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1549 case Z80_CC_M:
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1550 dst = cmp_irdisp8(dst, 0, opts->gen.context_reg, zf_off(ZF_S), SZ_B);
246 ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1551 break;
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1552 }
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1553 uint8_t *no_call_off = dst+1;
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1554 dst = jcc(dst, cond, dst+2);
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1555 dst = mov_rr(dst, opts->regs[Z80_SP], opts->gen.scratch1, SZ_W);
246 ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1556 dst = call(dst, (uint8_t *)z80_read_word);//T STates: 3, 3
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1557 dst = add_ir(dst, 2, opts->regs[Z80_SP], SZ_W);
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1558 dst = call(dst, (uint8_t *)z80_native_addr);
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1559 dst = jmp_r(dst, opts->gen.scratch1);
246 ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1560 *no_call_off = dst - (no_call_off+1);
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1561 break;
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1562 }
283 61f5d88ea01a Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions. Mike Pavone <pavone@retrodev.com> parents: 282 diff changeset	1563 case Z80_RETI:
61f5d88ea01a Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions. Mike Pavone <pavone@retrodev.com> parents: 282 diff changeset	1564 //For some systems, this may need a callback for signalling interrupt routine completion
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1565 dst = cycles(&opts->gen, 8);//T States: 4, 4
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1566 dst = mov_rr(dst, opts->regs[Z80_SP], opts->gen.scratch1, SZ_W);
283 61f5d88ea01a Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions. Mike Pavone <pavone@retrodev.com> parents: 282 diff changeset	1567 dst = call(dst, (uint8_t *)z80_read_word);//T STates: 3, 3
61f5d88ea01a Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions. Mike Pavone <pavone@retrodev.com> parents: 282 diff changeset	1568 dst = add_ir(dst, 2, opts->regs[Z80_SP], SZ_W);
61f5d88ea01a Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions. Mike Pavone <pavone@retrodev.com> parents: 282 diff changeset	1569 dst = call(dst, (uint8_t *)z80_native_addr);
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1570 dst = jmp_r(dst, opts->gen.scratch1);
283 61f5d88ea01a Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions. Mike Pavone <pavone@retrodev.com> parents: 282 diff changeset	1571 break;
61f5d88ea01a Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions. Mike Pavone <pavone@retrodev.com> parents: 282 diff changeset	1572 case Z80_RETN:
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1573 dst = cycles(&opts->gen, 8);//T States: 4, 4
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1574 dst = mov_rdisp8r(dst, opts->gen.context_reg, offsetof(z80_context, iff2), opts->gen.scratch2, SZ_B);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1575 dst = mov_rr(dst, opts->regs[Z80_SP], opts->gen.scratch1, SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1576 dst = mov_rrdisp8(dst, opts->gen.scratch2, opts->gen.context_reg, offsetof(z80_context, iff1), SZ_B);
283 61f5d88ea01a Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions. Mike Pavone <pavone@retrodev.com> parents: 282 diff changeset	1577 dst = call(dst, (uint8_t *)z80_read_word);//T STates: 3, 3
61f5d88ea01a Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions. Mike Pavone <pavone@retrodev.com> parents: 282 diff changeset	1578 dst = add_ir(dst, 2, opts->regs[Z80_SP], SZ_W);
61f5d88ea01a Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions. Mike Pavone <pavone@retrodev.com> parents: 282 diff changeset	1579 dst = call(dst, (uint8_t *)z80_native_addr);
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1580 dst = jmp_r(dst, opts->gen.scratch1);
283 61f5d88ea01a Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions. Mike Pavone <pavone@retrodev.com> parents: 282 diff changeset	1581 break;
241 2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	1582 case Z80_RST: {
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	1583 //RST is basically CALL to an address in page 0
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1584 dst = cycles(&opts->gen, 5);//T States: 5
241 2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	1585 dst = sub_ir(dst, 2, opts->regs[Z80_SP], SZ_W);
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1586 dst = mov_ir(dst, address + 1, opts->gen.scratch1, SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1587 dst = mov_rr(dst, opts->regs[Z80_SP], opts->gen.scratch2, SZ_W);
241 2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	1588 dst = call(dst, (uint8_t *)z80_write_word_highfirst);//T States: 3, 3
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	1589 uint8_t * call_dst = z80_get_native_address(context, inst->immed);
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	1590 if (!call_dst) {
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	1591 opts->deferred = defer_address(opts->deferred, inst->immed, dst + 1);
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	1592 //fake address to force large displacement
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	1593 call_dst = dst + 256;
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	1594 }
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	1595 dst = jmp(dst, call_dst);
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	1596 break;
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	1597 }
284 ed7098f717d7 Implement IN and OUT (untested) Mike Pavone <pavone@retrodev.com> parents: 283 diff changeset	1598 case Z80_IN:
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1599 dst = cycles(&opts->gen, inst->reg == Z80_A ? 7 : 8);//T States: 4 3/4
284 ed7098f717d7 Implement IN and OUT (untested) Mike Pavone <pavone@retrodev.com> parents: 283 diff changeset	1600 if (inst->addr_mode == Z80_IMMED_INDIRECT) {
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1601 dst = mov_ir(dst, inst->immed, opts->gen.scratch1, SZ_B);
284 ed7098f717d7 Implement IN and OUT (untested) Mike Pavone <pavone@retrodev.com> parents: 283 diff changeset	1602 } else {
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1603 dst = mov_rr(dst, opts->regs[Z80_C], opts->gen.scratch1, SZ_B);
284 ed7098f717d7 Implement IN and OUT (untested) Mike Pavone <pavone@retrodev.com> parents: 283 diff changeset	1604 }
ed7098f717d7 Implement IN and OUT (untested) Mike Pavone <pavone@retrodev.com> parents: 283 diff changeset	1605 dst = call(dst, (uint8_t *)z80_io_read);
ed7098f717d7 Implement IN and OUT (untested) Mike Pavone <pavone@retrodev.com> parents: 283 diff changeset	1606 translate_z80_reg(inst, &dst_op, dst, opts);
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1607 dst = mov_rr(dst, opts->gen.scratch1, dst_op.base, SZ_B);
284 ed7098f717d7 Implement IN and OUT (untested) Mike Pavone <pavone@retrodev.com> parents: 283 diff changeset	1608 dst = z80_save_reg(dst, inst, opts);
ed7098f717d7 Implement IN and OUT (untested) Mike Pavone <pavone@retrodev.com> parents: 283 diff changeset	1609 break;
ed7098f717d7 Implement IN and OUT (untested) Mike Pavone <pavone@retrodev.com> parents: 283 diff changeset	1610 /*case Z80_INI:
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	1611 case Z80_INIR:
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	1612 case Z80_IND:
284 ed7098f717d7 Implement IN and OUT (untested) Mike Pavone <pavone@retrodev.com> parents: 283 diff changeset	1613 case Z80_INDR:*/
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	1614 case Z80_OUT:
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1615 dst = cycles(&opts->gen, inst->reg == Z80_A ? 7 : 8);//T States: 4 3/4
284 ed7098f717d7 Implement IN and OUT (untested) Mike Pavone <pavone@retrodev.com> parents: 283 diff changeset	1616 if ((inst->addr_mode & 0x1F) == Z80_IMMED_INDIRECT) {
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1617 dst = mov_ir(dst, inst->immed, opts->gen.scratch2, SZ_B);
284 ed7098f717d7 Implement IN and OUT (untested) Mike Pavone <pavone@retrodev.com> parents: 283 diff changeset	1618 } else {
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1619 dst = mov_rr(dst, opts->regs[Z80_C], opts->gen.scratch2, SZ_B);
284 ed7098f717d7 Implement IN and OUT (untested) Mike Pavone <pavone@retrodev.com> parents: 283 diff changeset	1620 }
ed7098f717d7 Implement IN and OUT (untested) Mike Pavone <pavone@retrodev.com> parents: 283 diff changeset	1621 translate_z80_reg(inst, &src_op, dst, opts);
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1622 dst = mov_rr(dst, dst_op.base, opts->gen.scratch1, SZ_B);
284 ed7098f717d7 Implement IN and OUT (untested) Mike Pavone <pavone@retrodev.com> parents: 283 diff changeset	1623 dst = call(dst, (uint8_t *)z80_io_write);
ed7098f717d7 Implement IN and OUT (untested) Mike Pavone <pavone@retrodev.com> parents: 283 diff changeset	1624 dst = z80_save_reg(dst, inst, opts);
ed7098f717d7 Implement IN and OUT (untested) Mike Pavone <pavone@retrodev.com> parents: 283 diff changeset	1625 break;
ed7098f717d7 Implement IN and OUT (untested) Mike Pavone <pavone@retrodev.com> parents: 283 diff changeset	1626 /*case Z80_OUTI:
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	1627 case Z80_OTIR:
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	1628 case Z80_OUTD:
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	1629 case Z80_OTDR:*/
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1630 default: {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1631 char disbuf[80];
314 54c0e5f22198 Show absolute addresses for JR, JRCC and DJNZ in Z80 disassembler Mike Pavone <pavone@retrodev.com> parents: 313 diff changeset	1632 z80_disasm(inst, disbuf, address);
424 7e8e179116af Add support for loading GST format savestates Mike Pavone <pavone@retrodev.com> parents: 420 diff changeset	1633 fprintf(stderr, "unimplemented instruction: %s at %X\n", disbuf, address);
259 d9417261366f Fix a remaining z80_write reg swap bug. Properly initialize the native map slots. Reset appropriate regs when z80_reset is called. Mike Pavone <pavone@retrodev.com> parents: 257 diff changeset	1634 FILE * f = fopen("zram.bin", "wb");
d9417261366f Fix a remaining z80_write reg swap bug. Properly initialize the native map slots. Reset appropriate regs when z80_reset is called. Mike Pavone <pavone@retrodev.com> parents: 257 diff changeset	1635 fwrite(context->mem_pointers[0], 1, 8 * 1024, f);
d9417261366f Fix a remaining z80_write reg swap bug. Properly initialize the native map slots. Reset appropriate regs when z80_reset is called. Mike Pavone <pavone@retrodev.com> parents: 257 diff changeset	1636 fclose(f);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	1637 exit(1);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	1638 }
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1639 }
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1640 return dst;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1641 }
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1642
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1643 uint8_t * z80_get_native_address(z80_context * context, uint32_t address)
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1644 {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1645 native_map_slot *map;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1646 if (address < 0x4000) {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1647 address &= 0x1FFF;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1648 map = context->static_code_map;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1649 } else if (address >= 0x8000) {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1650 address &= 0x7FFF;
279 6be6056735a9 Fix native address lookup in bannked memory area Mike Pavone <pavone@retrodev.com> parents: 277 diff changeset	1651 map = context->banked_code_map + context->bank_reg;
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1652 } else {
313 a13329645ea3 Fix terminal instruction detection in disassembler Mike Pavone <pavone@retrodev.com> parents: 312 diff changeset	1653 //dprintf("z80_get_native_address: %X NULL\n", address);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1654 return NULL;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1655 }
268 6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	1656 if (!map->base \|\| !map->offsets \|\| map->offsets[address] == INVALID_OFFSET \|\| map->offsets[address] == EXTENSION_WORD) {
313 a13329645ea3 Fix terminal instruction detection in disassembler Mike Pavone <pavone@retrodev.com> parents: 312 diff changeset	1657 //dprintf("z80_get_native_address: %X NULL\n", address);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1658 return NULL;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1659 }
313 a13329645ea3 Fix terminal instruction detection in disassembler Mike Pavone <pavone@retrodev.com> parents: 312 diff changeset	1660 //dprintf("z80_get_native_address: %X %p\n", address, map->base + map->offsets[address]);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1661 return map->base + map->offsets[address];
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1662 }
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1663
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1664 uint8_t z80_get_native_inst_size(z80_options * opts, uint32_t address)
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1665 {
252 63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1666 if (address >= 0x4000) {
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1667 return 0;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1668 }
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1669 return opts->ram_inst_sizes[address & 0x1FFF];
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1670 }
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1671
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1672 void z80_map_native_address(z80_context * context, uint32_t address, uint8_t * native_address, uint8_t size, uint8_t native_size)
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1673 {
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1674 uint32_t orig_address = address;
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1675 native_map_slot *map;
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1676 z80_options * opts = context->options;
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1677 if (address < 0x4000) {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1678 address &= 0x1FFF;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1679 map = context->static_code_map;
252 63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1680 opts->ram_inst_sizes[address] = native_size;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1681 context->ram_code_flags[(address & 0x1C00) >> 10] \|= 1 << ((address & 0x380) >> 7);
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1682 context->ram_code_flags[((address + size) & 0x1C00) >> 10] \|= 1 << (((address + size) & 0x380) >> 7);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1683 } else if (address >= 0x8000) {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1684 address &= 0x7FFF;
279 6be6056735a9 Fix native address lookup in bannked memory area Mike Pavone <pavone@retrodev.com> parents: 277 diff changeset	1685 map = context->banked_code_map + context->bank_reg;
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1686 if (!map->offsets) {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1687 map->offsets = malloc(sizeof(int32_t) * 0x8000);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1688 memset(map->offsets, 0xFF, sizeof(int32_t) * 0x8000);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1689 }
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1690 } else {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1691 return;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1692 }
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1693 if (!map->base) {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1694 map->base = native_address;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1695 }
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1696 map->offsets[address] = native_address - map->base;
253 3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around. Mike Pavone <pavone@retrodev.com> parents: 252 diff changeset	1697 for(--size, orig_address++; size; --size, orig_address++) {
252 63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1698 address = orig_address;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1699 if (address < 0x4000) {
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1700 address &= 0x1FFF;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1701 map = context->static_code_map;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1702 } else if (address >= 0x8000) {
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1703 address &= 0x7FFF;
279 6be6056735a9 Fix native address lookup in bannked memory area Mike Pavone <pavone@retrodev.com> parents: 277 diff changeset	1704 map = context->banked_code_map + context->bank_reg;
252 63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1705 } else {
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1706 return;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1707 }
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1708 if (!map->offsets) {
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1709 map->offsets = malloc(sizeof(int32_t) * 0x8000);
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1710 memset(map->offsets, 0xFF, sizeof(int32_t) * 0x8000);
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1711 }
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1712 map->offsets[address] = EXTENSION_WORD;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1713 }
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1714 }
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1715
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1716 #define INVALID_INSTRUCTION_START 0xFEEDFEED
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1717
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1718 uint32_t z80_get_instruction_start(native_map_slot * static_code_map, uint32_t address)
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1719 {
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1720 if (!static_code_map->base \|\| address >= 0x4000) {
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1721 return INVALID_INSTRUCTION_START;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1722 }
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1723 address &= 0x1FFF;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1724 if (static_code_map->offsets[address] == INVALID_OFFSET) {
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1725 return INVALID_INSTRUCTION_START;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1726 }
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1727 while (static_code_map->offsets[address] == EXTENSION_WORD) {
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1728 --address;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1729 address &= 0x1FFF;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1730 }
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1731 return address;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1732 }
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1733
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1734 z80_context * z80_handle_code_write(uint32_t address, z80_context * context)
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1735 {
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1736 uint32_t inst_start = z80_get_instruction_start(context->static_code_map, address);
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1737 if (inst_start != INVALID_INSTRUCTION_START) {
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1738 uint8_t * dst = z80_get_native_address(context, inst_start);
268 6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	1739 dprintf("patching code at %p for Z80 instruction at %X due to write to %X\n", dst, inst_start, address);
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1740 dst = mov_ir(dst, inst_start, opts->gen.scratch1, SZ_D);
390 561fe3ea3fc8 Use a call instruction to figure out the original native address when retranslating so that it does not get lost when the byte transforms from a instruction word to extension word Mike Pavone <pavone@retrodev.com> parents: 389 diff changeset	1741 dst = call(dst, (uint8_t *)z80_retrans_stub);
252 63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1742 }
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1743 return context;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1744 }
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1745
264 8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	1746 uint8_t * z80_get_native_address_trans(z80_context * context, uint32_t address)
8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	1747 {
8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	1748 uint8_t * addr = z80_get_native_address(context, address);
8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	1749 if (!addr) {
8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	1750 translate_z80_stream(context, address);
8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	1751 addr = z80_get_native_address(context, address);
8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	1752 if (!addr) {
8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	1753 printf("Failed to translate %X to native code\n", address);
8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	1754 }
8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	1755 }
8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	1756 return addr;
8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	1757 }
8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	1758
266 376df762ddf5 Fix some more retranslation bugs in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 264 diff changeset	1759 void z80_handle_deferred(z80_context * context)
376df762ddf5 Fix some more retranslation bugs in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 264 diff changeset	1760 {
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1761 z80_options * opts = context->options;
266 376df762ddf5 Fix some more retranslation bugs in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 264 diff changeset	1762 process_deferred(&opts->deferred, context, (native_addr_func)z80_get_native_address);
376df762ddf5 Fix some more retranslation bugs in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 264 diff changeset	1763 if (opts->deferred) {
376df762ddf5 Fix some more retranslation bugs in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 264 diff changeset	1764 translate_z80_stream(context, opts->deferred->address);
376df762ddf5 Fix some more retranslation bugs in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 264 diff changeset	1765 }
376df762ddf5 Fix some more retranslation bugs in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 264 diff changeset	1766 }
376df762ddf5 Fix some more retranslation bugs in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 264 diff changeset	1767
390 561fe3ea3fc8 Use a call instruction to figure out the original native address when retranslating so that it does not get lost when the byte transforms from a instruction word to extension word Mike Pavone <pavone@retrodev.com> parents: 389 diff changeset	1768 void * z80_retranslate_inst(uint32_t address, z80_context * context, uint8_t * orig_start)
252 63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1769 {
266 376df762ddf5 Fix some more retranslation bugs in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 264 diff changeset	1770 char disbuf[80];
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1771 z80_options * opts = context->options;
252 63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1772 uint8_t orig_size = z80_get_native_inst_size(opts, address);
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1773 uint32_t orig = address;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1774 address &= 0x1FFF;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1775 uint8_t * dst = opts->cur_code;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1776 uint8_t * dst_end = opts->code_end;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1777 uint8_t after, inst = context->mem_pointers[0] + address;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1778 z80inst instbuf;
268 6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	1779 dprintf("Retranslating code at Z80 address %X, native address %p\n", address, orig_start);
252 63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1780 after = z80_decode(inst, &instbuf);
268 6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	1781 #ifdef DO_DEBUG_PRINT
314 54c0e5f22198 Show absolute addresses for JR, JRCC and DJNZ in Z80 disassembler Mike Pavone <pavone@retrodev.com> parents: 313 diff changeset	1782 z80_disasm(&instbuf, disbuf, address);
266 376df762ddf5 Fix some more retranslation bugs in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 264 diff changeset	1783 if (instbuf.op == Z80_NOP) {
376df762ddf5 Fix some more retranslation bugs in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 264 diff changeset	1784 printf("%X\t%s(%d)\n", address, disbuf, instbuf.immed);
376df762ddf5 Fix some more retranslation bugs in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 264 diff changeset	1785 } else {
376df762ddf5 Fix some more retranslation bugs in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 264 diff changeset	1786 printf("%X\t%s\n", address, disbuf);
267 1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	1787 }
268 6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	1788 #endif
252 63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1789 if (orig_size != ZMAX_NATIVE_SIZE) {
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1790 if (dst_end - dst < ZMAX_NATIVE_SIZE) {
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1791 size_t size = 1024*1024;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1792 dst = alloc_code(&size);
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1793 opts->code_end = dst_end = dst + size;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1794 opts->cur_code = dst;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1795 }
282 7b8a49220e3b Remove deferred address entries from abandoned translations inside z80_retrans_inst Mike Pavone <pavone@retrodev.com> parents: 279 diff changeset	1796 deferred_addr * orig_deferred = opts->deferred;
252 63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1797 uint8_t * native_end = translate_z80inst(&instbuf, dst, context, address);
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1798 if ((native_end - dst) <= orig_size) {
264 8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	1799 uint8_t * native_next = z80_get_native_address(context, address + after-inst);
8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	1800 if (native_next && ((native_next == orig_start + orig_size) \|\| (orig_size - (native_end - dst)) > 5)) {
282 7b8a49220e3b Remove deferred address entries from abandoned translations inside z80_retrans_inst Mike Pavone <pavone@retrodev.com> parents: 279 diff changeset	1801 remove_deferred_until(&opts->deferred, orig_deferred);
264 8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	1802 native_end = translate_z80inst(&instbuf, orig_start, context, address);
266 376df762ddf5 Fix some more retranslation bugs in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 264 diff changeset	1803 if (native_next == orig_start + orig_size && (native_next-native_end) < 2) {
264 8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	1804 while (native_end < orig_start + orig_size) {
8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	1805 *(native_end++) = 0x90; //NOP
8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	1806 }
8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	1807 } else {
8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	1808 jmp(native_end, native_next);
8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	1809 }
266 376df762ddf5 Fix some more retranslation bugs in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 264 diff changeset	1810 z80_handle_deferred(context);
264 8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	1811 return orig_start;
252 63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1812 }
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1813 }
264 8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	1814 z80_map_native_address(context, address, dst, after-inst, ZMAX_NATIVE_SIZE);
266 376df762ddf5 Fix some more retranslation bugs in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 264 diff changeset	1815 opts->cur_code = dst+ZMAX_NATIVE_SIZE;
376df762ddf5 Fix some more retranslation bugs in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 264 diff changeset	1816 jmp(orig_start, dst);
283 61f5d88ea01a Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions. Mike Pavone <pavone@retrodev.com> parents: 282 diff changeset	1817 if (!z80_is_terminal(&instbuf)) {
264 8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	1818 jmp(native_end, z80_get_native_address_trans(context, address + after-inst));
8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	1819 }
266 376df762ddf5 Fix some more retranslation bugs in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 264 diff changeset	1820 z80_handle_deferred(context);
264 8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	1821 return dst;
252 63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1822 } else {
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1823 dst = translate_z80inst(&instbuf, orig_start, context, address);
283 61f5d88ea01a Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions. Mike Pavone <pavone@retrodev.com> parents: 282 diff changeset	1824 if (!z80_is_terminal(&instbuf)) {
264 8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	1825 dst = jmp(dst, z80_get_native_address_trans(context, address + after-inst));
252 63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1826 }
266 376df762ddf5 Fix some more retranslation bugs in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 264 diff changeset	1827 z80_handle_deferred(context);
252 63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1828 return orig_start;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1829 }
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1830 }
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1831
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1832 void translate_z80_stream(z80_context * context, uint32_t address)
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1833 {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1834 char disbuf[80];
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1835 if (z80_get_native_address(context, address)) {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1836 return;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1837 }
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1838 z80_options * opts = context->options;
505 b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 467 diff changeset	1839 uint32_t start_address = address;
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1840 uint8_t * encoded = NULL, *next;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1841 if (address < 0x4000) {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1842 encoded = context->mem_pointers[0] + (address & 0x1FFF);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1843 } else if(address >= 0x8000 && context->mem_pointers[1]) {
394 d5f1840273b5 Bail out on attempt to run code from bank area until it is properly supported Mike Pavone <pavone@retrodev.com> parents: 390 diff changeset	1844 printf("attempt to translate Z80 code from banked area at address %X\n", address);
d5f1840273b5 Bail out on attempt to run code from bank area until it is properly supported Mike Pavone <pavone@retrodev.com> parents: 390 diff changeset	1845 exit(1);
d5f1840273b5 Bail out on attempt to run code from bank area until it is properly supported Mike Pavone <pavone@retrodev.com> parents: 390 diff changeset	1846 //encoded = context->mem_pointers[1] + (address & 0x7FFF);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1847 }
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1848 while (encoded != NULL)
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1849 {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1850 z80inst inst;
268 6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	1851 dprintf("translating Z80 code at address %X\n", address);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1852 do {
252 63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1853 if (opts->code_end-opts->cur_code < ZMAX_NATIVE_SIZE) {
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1854 if (opts->code_end-opts->cur_code < 5) {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1855 puts("out of code memory, not enough space for jmp to next chunk");
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1856 exit(1);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1857 }
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1858 size_t size = 1024*1024;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1859 opts->cur_code = alloc_code(&size);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1860 opts->code_end = opts->cur_code + size;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1861 jmp(opts->cur_code, opts->cur_code);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1862 }
255 572b935dd030 Properly handle wrapping around to 0 in translate_z80_stream Mike Pavone <pavone@retrodev.com> parents: 254 diff changeset	1863 if (address > 0x4000 && address < 0x8000) {
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1864 opts->cur_code = xor_rr(opts->cur_code, RDI, RDI, SZ_D);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1865 opts->cur_code = call(opts->cur_code, (uint8_t *)exit);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1866 break;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1867 }
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1868 uint8_t * existing = z80_get_native_address(context, address);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1869 if (existing) {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1870 opts->cur_code = jmp(opts->cur_code, existing);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1871 break;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1872 }
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1873 next = z80_decode(encoded, &inst);
268 6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	1874 #ifdef DO_DEBUG_PRINT
314 54c0e5f22198 Show absolute addresses for JR, JRCC and DJNZ in Z80 disassembler Mike Pavone <pavone@retrodev.com> parents: 313 diff changeset	1875 z80_disasm(&inst, disbuf, address);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1876 if (inst.op == Z80_NOP) {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1877 printf("%X\t%s(%d)\n", address, disbuf, inst.immed);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1878 } else {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1879 printf("%X\t%s\n", address, disbuf);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1880 }
268 6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	1881 #endif
248 9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	1882 uint8_t *after = translate_z80inst(&inst, opts->cur_code, context, address);
252 63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1883 z80_map_native_address(context, address, opts->cur_code, next-encoded, after - opts->cur_code);
248 9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	1884 opts->cur_code = after;
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1885 address += next-encoded;
255 572b935dd030 Properly handle wrapping around to 0 in translate_z80_stream Mike Pavone <pavone@retrodev.com> parents: 254 diff changeset	1886 if (address > 0xFFFF) {
572b935dd030 Properly handle wrapping around to 0 in translate_z80_stream Mike Pavone <pavone@retrodev.com> parents: 254 diff changeset	1887 address &= 0xFFFF;
505 b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 467 diff changeset	1888
255 572b935dd030 Properly handle wrapping around to 0 in translate_z80_stream Mike Pavone <pavone@retrodev.com> parents: 254 diff changeset	1889 } else {
572b935dd030 Properly handle wrapping around to 0 in translate_z80_stream Mike Pavone <pavone@retrodev.com> parents: 254 diff changeset	1890 encoded = next;
572b935dd030 Properly handle wrapping around to 0 in translate_z80_stream Mike Pavone <pavone@retrodev.com> parents: 254 diff changeset	1891 }
283 61f5d88ea01a Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions. Mike Pavone <pavone@retrodev.com> parents: 282 diff changeset	1892 } while (!z80_is_terminal(&inst));
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1893 process_deferred(&opts->deferred, context, (native_addr_func)z80_get_native_address);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1894 if (opts->deferred) {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1895 address = opts->deferred->address;
268 6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	1896 dprintf("defferred address: %X\n", address);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1897 if (address < 0x4000) {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1898 encoded = context->mem_pointers[0] + (address & 0x1FFF);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1899 } else if (address > 0x8000 && context->mem_pointers[1]) {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1900 encoded = context->mem_pointers[1] + (address & 0x7FFF);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1901 } else {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1902 printf("attempt to translate non-memory address: %X\n", address);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1903 exit(1);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1904 }
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1905 } else {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1906 encoded = NULL;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1907 }
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1908 }
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	1909 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	1910
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1911 void init_x86_z80_opts(z80_options * options, memmap_chunk * chunks, uint32_t num_chunks)
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	1912 {
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1913 memset(options, 0, sizeof(*options));
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1914
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1915 options->gen.address_size = SZ_W;
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1916 options->gen.address_mask = 0xFFFF;
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1917 options->gen.max_address = 0x10000;
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1918 options->gen.bus_cycles = 3;
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1919 options->gen.mem_ptr_off = offsetof(z80_context, mem_pointers);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1920 options->gen.ram_flags_off = offsetof(z80_context, ram_code_flags);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1921
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1922 options->flags = 0;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1923 options->regs[Z80_B] = BH;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1924 options->regs[Z80_C] = RBX;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1925 options->regs[Z80_D] = CH;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1926 options->regs[Z80_E] = RCX;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1927 options->regs[Z80_H] = AH;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1928 options->regs[Z80_L] = RAX;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1929 options->regs[Z80_IXH] = DH;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1930 options->regs[Z80_IXL] = RDX;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1931 options->regs[Z80_IYH] = -1;
239 a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	1932 options->regs[Z80_IYL] = R8;
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1933 options->regs[Z80_I] = -1;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1934 options->regs[Z80_R] = -1;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1935 options->regs[Z80_A] = R10;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1936 options->regs[Z80_BC] = RBX;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1937 options->regs[Z80_DE] = RCX;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1938 options->regs[Z80_HL] = RAX;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1939 options->regs[Z80_SP] = R9;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1940 options->regs[Z80_AF] = -1;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1941 options->regs[Z80_IX] = RDX;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1942 options->regs[Z80_IY] = R8;
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1943
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1944 options->bank_reg = R15;
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1945 options->bank_pointer = R12;
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1946
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1947 options->gen.context_reg = RSI;
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1948 options->gen.cycles = RBP;
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1949 options->gen.limit = RDI;
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1950 options->gen.scratch1 = R13;
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1951 options->gen.scratch2 = R14;
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1952
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1953 options->gen.native_code_map = malloc(sizeof(native_map_slot));
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1954 memset(options->gen.native_code_map, 0, sizeof(native_map_slot));
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1955 options->gen.deferred = NULL;
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1956 options->gen.ram_inst_sizes = malloc(sizeof(uint8_t) * 0x2000);
252 63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1957 memset(options->ram_inst_sizes, 0, sizeof(uint8_t) * 0x2000);
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1958
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1959 code_info *code = &options->gen.code;
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1960 init_code_info(code);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1961
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1962 options->save_context_scratch = code->cur;
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1963 mov_rrdisp(code, options->gen.scratch1, options->gen.context_reg, offsetof(z80_context, scratch1), SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1964 mov_rrdisp(code, options->gen.scratch2, options->gen.context_reg, offsetof(z80_context, scratch2), SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1965
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1966 options->gen.save_context = code->cur;
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1967 for (int i = 0; i <= Z80_A; i++)
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1968 {
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1969 int reg;
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1970 uint8_t size;
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1971 if (i < Z80_I) {
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1972 int reg = i /2 + Z80_BC;
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1973 size = SZ_W;
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1974
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1975 } else {
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1976 reg = i;
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1977 size = SZ_B;
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1978 }
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1979 if (options->regs[reg] >= 0) {
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1980 mov_rrdisp(code, options->regs[reg], options->gen.context_reg, offsetof(z80_context, regs) + i, size);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1981 }
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1982 }
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1983 if (options->regs[Z80_SP] >= 0) {
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1984 mov_rrdisp(code, options->regs[Z80_SP], options->gen.context_reg, offsetof(z80_context, sp), SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1985 }
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1986 mov_rrdisp(code, options->gen.limit, options->gen.context_reg, offsetof(z80_context, target_cycle), SZ_D);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1987 mov_rrdisp(code, options->gen.cycles, options->gen.context_reg, offsetof(z80_context, current_cycle), SZ_D);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1988 mov_rrdisp(code, options->bank_reg, options->gen.context_reg, offsetof(z80_context, bank_reg), SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1989 mov_rrdisp(code, options->bank_pointer, options->gen.context_reg, offsetof(z80_context, mem_pointers) + sizeof(uint8_t ) 1, SZ_PTR);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1990
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1991 options->load_context_scratch = code->cur;
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1992 mov_rdispr(code, options->gen.context_reg, offsetof(z80_context, scratch1), options->gen.scratch1, SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1993 mov_rdispr(code, options->gen.context_reg, offsetof(z80_context, scratch2), options->gen.scratch2, SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1994 options->gen.load_context = code->cur;
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1995 for (int i = 0; i <= Z80_A; i++)
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1996 {
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1997 int reg;
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1998 uint8_t size;
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1999 if (i < Z80_I) {
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2000 int reg = i /2 + Z80_BC;
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2001 size = SZ_W;
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2002
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2003 } else {
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2004 reg = i;
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2005 size = SZ_B;
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2006 }
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2007 if (options->regs[reg] >= 0) {
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2008 mov_rdispr(code, options->gen.context_reg, offsetof(z80_context, regs) + i, options->regs[reg], size);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2009 }
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2010 }
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2011 if (options->regs[Z80_SP] >= 0) {
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2012 mov_rdispr(code, options->gen.context_reg, offsetof(z80_context, sp), options->regs[Z80_SP], SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2013 }
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2014 mov_rdispr(code, options->gen.context_reg, offsetof(z80_context, target_cycle), options->gen.limit, SZ_D);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2015 mov_rdispr(code, options->gen.context_reg, offsetof(z80_context, current_cycle), options->gen.cycles, SZ_D);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2016 mov_rdispr(code, options->gen.context_reg, offsetof(z80_context, bank_reg), options->bank_reg, SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2017 mov_rdispr(code, options->gen.context_reg, offsetof(z80_context, mem_pointers) + sizeof(uint8_t ) 1, options->bank_pointer, SZ_PTR);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2018
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2019 options->gen.handle_cycle_limit = code->cur;
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2020 cmp_rdispr(code, options->gen.context_reg, offsetof(z80_context, sync_cycle), options->gen.cycles, SZ_D);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2021 code_ptr no_sync = code->cur+1;
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2022 jcc(code, CC_B, no_sync);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2023 mov_irdisp(code, 0, options->gen.context_reg, offsetof(z80_context, pc), SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2024 call(code, options->save_context_scratch);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2025 pop_r(code, RAX); //return address in read/write func
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2026 pop_r(code, RBX); //return address in translated code
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2027 sub_ir(code, 5, RAX, SZ_PTR); //adjust return address to point to the call that got us here
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2028 mov_rrdisp(code, RBX, options->gen.context_reg, offsetof(z80_context, extra_pc), SZ_PTR);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2029 mov_rrind(code, RAX, options->gen.context_reg, SZ_PTR);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2030 //restore callee saved registers
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2031 pop_r(code, R15)
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2032 pop_r(code, R14)
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2033 pop_r(code, R13)
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2034 pop_r(code, R12)
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2035 pop_r(code, RBP)
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2036 pop_r(code, RBX)
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2037 *no_sync = code->cur - no_sync;
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2038 //return to caller of z80_run
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2039 retn(code);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2040
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2041 options->gen.read_8 = gen_mem_fun(&options->gen, chunks, num_chunks, READ_8, NULL);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2042 options->gen.write_8 = gen_mem_fun(&options->gen, chunks, num_chunks, WRITE_8, &options->write_8_noinc);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2043
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2044 options->gen.handle_cycle_limit_int = code->cur;
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2045 cmp_rdispr(code, options->gen.context_reg, offsetof(z80_context, int_cycle), options->gen.cycles, SZ_D);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2046 code_ptr skip_int = code->cur+1;
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2047 jcc(code, CC_B, skip_int);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2048 //set limit to the cycle limit
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2049 mov_rdispr(code, options->gen.context_reg, offsetof(z80_context, sync_cycle), options->gen.limit, SZ_D);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2050 //disable interrupts
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2051 move_irdisp(code, 0, options->gen.context_reg, offsetof(z80_context, iff1), SZ_B);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2052 move_irdisp(code, 0, options->gen.context_reg, offsetof(z80_context, iff2), SZ_B);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2053 cycles(&options->gen, 7);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2054 //save return address (in scratch1) to Z80 stack
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2055 sub_ir(code, 2, options->regs[Z80_SP], SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2056 mov_rr(code, options->regs[Z80_SP], options->gen.scratch2, SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2057 //we need to do check_cycles and cycles outside of the write_8 call
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2058 //so that the stack has the correct depth if we need to return to C
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2059 //for a synchronization
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2060 check_cycles(&options->gen);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2061 cycles(&options->gen, 3);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2062 //save word to write before call to write_8_noinc
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2063 push_r(code, options->gen.scratch1);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2064 call(code, options->write_8_noinc);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2065 //restore word to write
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2066 pop_r(code, options->gen.scratch1);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2067 //write high byte to SP+1
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2068 mov_rr(code, options->regs[Z80_SP], options->gen.scratch2, SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2069 add_ir(code, 1, options->gen.scratch2, SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2070 shr_ir(code, 8, options->gen.scratch1, SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2071 check_cycles(&options->gen);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2072 cycles(&options->gen, 3);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2073 call(code, options->write_8_noinc);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2074 //dispose of return address as we'll be jumping somewhere else
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2075 pop_r(options->gen.scratch2);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2076 //TODO: Support interrupt mode 0 and 2
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2077 mov_ir(code, 0x38, options->gen.scratch1, SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2078 call(code, (code_ptr)z80_native_addr);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2079 jmp_r(code, options->gen.scratch1);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	2080 }
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2081
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2082 void init_z80_context(z80_context * context, z80_options * options)
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2083 {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2084 memset(context, 0, sizeof(*context));
360 c42fae88d346 Fix sizeof expression passed to malloc in z80_init to avoid a minor memory error Mike Pavone <pavone@retrodev.com> parents: 335 diff changeset	2085 context->static_code_map = malloc(sizeof(*context->static_code_map));
259 d9417261366f Fix a remaining z80_write reg swap bug. Properly initialize the native map slots. Reset appropriate regs when z80_reset is called. Mike Pavone <pavone@retrodev.com> parents: 257 diff changeset	2086 context->static_code_map->base = NULL;
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2087 context->static_code_map->offsets = malloc(sizeof(int32_t) * 0x2000);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2088 memset(context->static_code_map->offsets, 0xFF, sizeof(int32_t) * 0x2000);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2089 context->banked_code_map = malloc(sizeof(native_map_slot) * (1 << 9));
259 d9417261366f Fix a remaining z80_write reg swap bug. Properly initialize the native map slots. Reset appropriate regs when z80_reset is called. Mike Pavone <pavone@retrodev.com> parents: 257 diff changeset	2090 memset(context->banked_code_map, 0, sizeof(native_map_slot) * (1 << 9));
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2091 context->options = options;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2092 }
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2093
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2094 void z80_reset(z80_context * context)
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2095 {
259 d9417261366f Fix a remaining z80_write reg swap bug. Properly initialize the native map slots. Reset appropriate regs when z80_reset is called. Mike Pavone <pavone@retrodev.com> parents: 257 diff changeset	2096 context->im = 0;
d9417261366f Fix a remaining z80_write reg swap bug. Properly initialize the native map slots. Reset appropriate regs when z80_reset is called. Mike Pavone <pavone@retrodev.com> parents: 257 diff changeset	2097 context->iff1 = context->iff2 = 0;
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2098 context->native_pc = z80_get_native_address_trans(context, 0);
268 6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	2099 context->extra_pc = NULL;
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2100 }
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2101
366 836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	2102 void zinsert_breakpoint(z80_context * context, uint16_t address, uint8_t * bp_handler)
836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	2103 {
836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	2104 static uint8_t * bp_stub = NULL;
836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	2105 uint8_t * native = z80_get_native_address_trans(context, address);
836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	2106 uint8_t * start_native = native;
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2107 native = mov_ir(native, address, opts->gen.scratch1, SZ_W);
366 836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	2108 if (!bp_stub) {
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2109 z80_options * opts = context->options;
366 836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	2110 uint8_t * dst = opts->cur_code;
836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	2111 uint8_t * dst_end = opts->code_end;
836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	2112 if (dst_end - dst < 128) {
836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	2113 size_t size = 1024*1024;
836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	2114 dst = alloc_code(&size);
836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	2115 opts->code_end = dst_end = dst + size;
836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	2116 }
836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	2117 bp_stub = dst;
836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	2118 native = call(native, bp_stub);
505 b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 467 diff changeset	2119
366 836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	2120 //Calculate length of prologue
836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	2121 dst = z80_check_cycles_int(dst, address);
836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	2122 int check_int_size = dst-bp_stub;
836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	2123 dst = bp_stub;
505 b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 467 diff changeset	2124
366 836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	2125 //Save context and call breakpoint handler
836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	2126 dst = call(dst, (uint8_t *)z80_save_context);
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2127 dst = push_r(dst, opts->gen.scratch1);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2128 dst = mov_rr(dst, opts->gen.context_reg, RDI, SZ_Q);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2129 dst = mov_rr(dst, opts->gen.scratch1, RSI, SZ_W);
366 836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	2130 dst = call(dst, bp_handler);
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2131 dst = mov_rr(dst, RAX, opts->gen.context_reg, SZ_Q);
366 836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	2132 //Restore context
836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	2133 dst = call(dst, (uint8_t *)z80_load_context);
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2134 dst = pop_r(dst, opts->gen.scratch1);
366 836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	2135 //do prologue stuff
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2136 dst = cmp_rr(dst, opts->gen.cycles, opts->gen.limit, SZ_D);
366 836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	2137 uint8_t * jmp_off = dst+1;
836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	2138 dst = jcc(dst, CC_NC, dst + 7);
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2139 dst = pop_r(dst, opts->gen.scratch1);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2140 dst = add_ir(dst, check_int_size - (native-start_native), opts->gen.scratch1, SZ_Q);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2141 dst = push_r(dst, opts->gen.scratch1);
372 5dcf7551bb36 Bunch of Z80 debugger improvements Mike Pavone <pavone@retrodev.com> parents: 367 diff changeset	2142 dst = jmp(dst, (uint8_t *)z80_handle_cycle_limit_int);
366 836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	2143 *jmp_off = dst - (jmp_off+1);
836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	2144 //jump back to body of translated instruction
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2145 dst = pop_r(dst, opts->gen.scratch1);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2146 dst = add_ir(dst, check_int_size - (native-start_native), opts->gen.scratch1, SZ_Q);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2147 dst = jmp_r(dst, opts->gen.scratch1);
366 836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	2148 opts->cur_code = dst;
836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	2149 } else {
836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	2150 native = call(native, bp_stub);
836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	2151 }
836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	2152 }
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2153
366 836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	2154 void zremove_breakpoint(z80_context * context, uint16_t address)
836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	2155 {
836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	2156 uint8_t * native = z80_get_native_address(context, address);
836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	2157 z80_check_cycles_int(native, address);
836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	2158 }
836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	2159
836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	2160

Mercurial > repos > blastem

annotate z80_to_x86.c @ 590:ea80559c67cb