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annotate gentests.py @ 224:f7ff02eeec2f

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Added testcases for move and roxl/roxr. Made some small improvements to test tools.
author Mike Pavone <pavone@retrodev.com>
date Sun, 21 Apr 2013 11:40:18 -0700
parents cb72780e17b1
children 42123feab62d
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1 #!/usr/bin/env python
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2
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3 def split_fields(line):
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4 parts = []
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5 while line:
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6 field,_,line = line.partition('\t')
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7 parts.append(field.strip())
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8 while line.startswith('\t'):
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9 line = line[1:]
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10 return parts
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11
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12 class Program(object):
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13 def __init__(self, instruction):
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14 self.avail_dregs = {0,1,2,3,4,5,6,7}
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15 self.avail_aregs = {0,1,2,3,4,5,6,7}
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16 instruction.consume_regs(self)
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17 self.inst = instruction
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18
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19 def dirname(self):
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20 return self.inst.name + '_' + self.inst.size
214
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21 def name(self):
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22 return str(self.inst).replace('.', '_').replace('#', '_').replace(',', '_').replace(' ', '_').replace('(', '[').replace(')', ']')
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23
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24 def write_rom_test(self, outfile):
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25 outfile.write('\tdc.l $0, start\n')
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26 for i in xrange(0x8, 0x100, 0x4):
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27 outfile.write('\tdc.l empty_handler\n')
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28 outfile.write('\tdc.b "SEGA"\nempty_handler:\n\trte\nstart:\n')
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29 outfile.write('\tmove #0, CCR\n')
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30 already = {}
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31 self.inst.write_init(outfile, already)
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32 if 'label' in already:
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33 outfile.write('lbl_' + str(already['label']) + ':\n')
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34 outfile.write('\t'+str(self.inst)+'\n')
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35 outfile.write('\t'+self.inst.save_result(self.get_dreg(), True) + '\n')
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36 save_ccr = self.get_dreg()
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37 outfile.write('\tmove SR, ' + str(save_ccr) + '\n')
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38 outfile.write('\tmove #$1F, CCR\n')
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39 self.inst.invalidate_dest(already)
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40 self.inst.write_init(outfile, already)
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41 if 'label' in already:
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42 outfile.write('lbl_' + str(already['label']) + ':\n')
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43 outfile.write('\t'+str(self.inst)+'\n')
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44 outfile.write('\t'+self.inst.save_result(self.get_dreg(), False) + '\n')
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45 outfile.write('\treset\n')
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46
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47 def consume_dreg(self, num):
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48 self.avail_dregs.discard(num)
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49
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50 def consume_areg(self, num):
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51 self.avail_aregs.discard(num)
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52
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53 def get_dreg(self):
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54 return Register('d', self.avail_dregs.pop())
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55
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56 class Register(object):
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57 def __init__(self, kind, num):
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58 self.kind = kind
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59 self.num = num
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60
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61 def __str__(self):
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62 if self.kind == 'd' or self.kind == 'a':
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63 return self.kind + str(self.num)
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64 return self.kind
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65
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66 def write_init(self, outfile, size, already):
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67 if not str(self) in already:
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68 minv,maxv = get_size_range(size)
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69 val = randint(minv,maxv)
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70 already[str(self)] = val
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71 outfile.write('\tmove.'+size+' #'+str(val)+', ' + str(self) + '\n')
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72
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73 def consume_regs(self, program):
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74 if self.kind == 'd':
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75 program.consume_dreg(self.num)
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76 elif self.kind == 'a':
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77 program.consume_areg(self.num)
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78
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79 def valid_ram_address(address, size='b'):
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80 return address >= 0xE00000 and address <= 0xFFFFFFFC and (address & 0xE00000) == 0xE00000 and (size == 'b' or not address & 1)
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81
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82 def random_ram_address(mina=0xE00000, maxa=0xFFFFFFFC):
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83 return randint(mina, maxa) | 0xE00000
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84
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85 class Indexed(object):
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86 def __init__(self, base, index, index_size, disp):
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87 self.base = base
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88 self.index = index
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89 self.index_size = index_size
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90 self.disp = disp
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91
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92 def write_init(self, outfile, size, already):
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93 if self.base.kind == 'pc':
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94 if str(self.index) in already:
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95 index = already[str(self.index)]
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96 if self.index_size == 'w':
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97 index = index & 0xFFFF
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98 #sign extend index
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99 if index & 0x8000:
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100 index -= 65536
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101 if index > -1024:
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102 index = already[str(self.index)] = randint(-32768, -1024)
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103 outfile.write('\tmove.l #' + str(index) + ', ' + str(self.index) + '\n')
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104 else:
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105 index = already[str(self.index)] = randint(-32768, -1024)
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106 outfile.write('\tmove.l #' + str(index) + ', ' + str(self.index) + '\n')
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107 num = already.get('label', 0)+1
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108 already['label'] = num
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109 address = 'lbl_' + str(num) + ' + 2 + ' + str(self.disp) + ' + ' + str(index)
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110 else:
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111 if self.base == self.index:
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112 if str(self.base) in already:
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113 if not valid_ram_address(already[str(self.base)]*2):
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114 del already[str(self.base)]
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115 self.write_init(outfile, size, already)
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116 return
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117 else:
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118 base = index = already[str(self.base)]
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119 else:
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120 base = index = already[str(self.base)] = random_ram_address()/2
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121 outfile.write('\tmove.l #' + str(base) + ', ' + str(self.base) + '\n')
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122 else:
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123 if str(self.base) in already:
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124 if not valid_ram_address(already[str(self.base)]):
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125 del already[str(self.base)]
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126 self.write_init(outfile, size, already)
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127 return
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128 else:
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129 base = already[str(self.base)]
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130 else:
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131 base = already[str(self.base)] = random_ram_address()
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132 outfile.write('\tmove.l #' + str(base) + ', ' + str(self.base) + '\n')
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133 if str(self.index) in already:
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134 index = already[str(self.index)]
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diff changeset
135 if self.index_size == 'w':
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diff changeset
136 index = index & 0xFFFF
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diff changeset
137 #sign extend index
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parents: 214
diff changeset
138 if index & 0x8000:
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diff changeset
139 index -= 65536
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parents: 214
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140 if not valid_ram_address(base + index):
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
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parents: 214
diff changeset
141 index = already[str(self.index)] = randint(-64, 63)
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parents: 214
diff changeset
142 outfile.write('\tmove.l #' + str(index) + ', ' + str(self.index) + '\n')
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Mike Pavone <pavone@retrodev.com>
parents: 214
diff changeset
143 else:
214
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144 index = already[str(self.index)] = randint(-64, 63)
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145 outfile.write('\tmove.l #' + str(index) + ', ' + str(self.index) + '\n')
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146 address = base + index + self.disp
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147 if (address & 0xFFFFFF) < 0xE00000:
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148 if (address & 0xFFFFFF) < 128:
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149 self.disp -= (address & 0xFFFFFF)
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150 else:
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151 self.disp += 0xE00000-(address & 0xFFFFFF)
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152 address = base + index + self.disp
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153 elif (address & 0xFFFFFF) > 0xFFFFFC:
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154 self.disp -= (address & 0xFFFFFF) - 0xFFFFFC
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155 address = base + index + self.disp
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156 if size != 'b' and address & 1:
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157 self.disp = self.disp ^ 1
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158 address = base + index + self.disp
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159 minv,maxv = get_size_range(size)
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160 outfile.write('\tmove.' + size + ' #' + str(randint(minv, maxv)) + ', (' + str(address) + ').l\n')
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161
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162 def __str__(self):
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163 return '(' + str(self.disp) + ', ' + str(self.base) + ', ' + str(self.index) + '.' + self.index_size + ')'
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164
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165 def consume_regs(self, program):
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166 self.base.consume_regs(program)
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167 self.index.consume_regs(program)
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168
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169 class Displacement(object):
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170 def __init__(self, base, disp):
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171 self.base = base
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172 self.disp = disp
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173
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174 def write_init(self, outfile, size, already):
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175 if self.base.kind == 'pc':
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176 num = already.get('label', 0)+1
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177 already['label'] = num
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178 address = 'lbl_' + str(num) + ' + 2 + ' + str(self.disp)
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179 else:
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180 if str(self.base) in already:
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181 if not valid_ram_address(already[str(self.base)]):
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182 del already[str(self.base)]
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183 self.write_init(outfile, size, already)
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parents:
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184 return
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parents:
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185 else:
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186 base = already[str(self.base)]
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187 else:
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188 base = already[str(self.base)] = random_ram_address()
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189 outfile.write('\tmove.l #' + str(base) + ', ' + str(self.base) + '\n')
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190 address = base + self.disp
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parents:
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191 if (address & 0xFFFFFF) < 0xE00000:
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parents:
diff changeset
192 if (address & 0xFFFFFF) < 0x10000:
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193 self.disp -= (address & 0xFFFFFF)
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194 else:
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195 self.disp += 0xE00000-(address & 0xFFFFFF)
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196 address = base + self.disp
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parents:
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197 elif (address & 0xFFFFFF) > 0xFFFFFC:
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198 self.disp -= (address & 0xFFFFFF) - 0xFFFFFC
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199 address = base + self.disp
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parents:
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200 if size != 'b' and address & 1:
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diff changeset
201 self.disp = self.disp ^ 1
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202 address = base + self.disp
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parents:
diff changeset
203 minv,maxv = get_size_range(size)
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diff changeset
204 outfile.write('\tmove.' + size + ' #' + str(randint(minv, maxv)) + ', (' + str(address) + ').l\n')
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205
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206 def __str__(self):
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207 return '(' + str(self.disp) + ', ' + str(self.base) + ')'
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parents:
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208
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209 def consume_regs(self, program):
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parents:
diff changeset
210 self.base.consume_regs(program)
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parents:
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211
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diff changeset
212 class Indirect(object):
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213 def __init__(self, reg):
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diff changeset
214 self.reg = reg
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parents:
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215
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parents:
diff changeset
216 def __str__(self):
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parents:
diff changeset
217 return '(' + str(self.reg) + ')'
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parents:
diff changeset
218
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diff changeset
219 def write_init(self, outfile, size, already):
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220 if str(self.reg) in already:
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parents:
diff changeset
221 if not valid_ram_address(already[str(self.reg)], size):
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parents:
diff changeset
222 del already[str(self.reg)]
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diff changeset
223 self.write_init(outfile, size, already)
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parents:
diff changeset
224 return
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
225 else:
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parents:
diff changeset
226 address = already[str(self.reg)]
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parents:
diff changeset
227 else:
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diff changeset
228 address = random_ram_address()
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diff changeset
229 if size != 'b':
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230 address = address & 0xFFFFFFFE
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diff changeset
231 outfile.write('\tmove.l #' + str(address) + ', ' + str(self.reg) + '\n')
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parents:
diff changeset
232 already[str(self.reg)] = address
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parents:
diff changeset
233 minv,maxv = get_size_range(size)
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parents:
diff changeset
234 outfile.write('\tmove.' + size + ' #' + str(randint(minv, maxv)) + ', (' + str(address) + ').l\n')
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parents:
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235
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diff changeset
236 def consume_regs(self, program):
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parents:
diff changeset
237 self.reg.consume_regs(program)
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238
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diff changeset
239 class Increment(object):
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
240 def __init__(self, reg):
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parents:
diff changeset
241 self.reg = reg
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parents:
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242
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parents:
diff changeset
243 def __str__(self):
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
244 return '(' + str(self.reg) + ')+'
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parents:
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245
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diff changeset
246 def write_init(self, outfile, size, already):
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
247 if str(self.reg) in already:
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parents:
diff changeset
248 if not valid_ram_address(already[str(self.reg)], size):
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parents:
diff changeset
249 del already[str(self.reg)]
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parents:
diff changeset
250 self.write_init(outfile, size, already)
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parents:
diff changeset
251 return
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parents:
diff changeset
252 else:
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diff changeset
253 address = already[str(self.reg)]
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parents:
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254 else:
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parents:
diff changeset
255 address = random_ram_address()
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parents:
diff changeset
256 if size != 'b':
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parents:
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257 address = address & 0xFFFFFFFE
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diff changeset
258 outfile.write('\tmove.l #' + str(address) + ', ' + str(self.reg) + '\n')
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parents:
diff changeset
259 already[str(self.reg)] = address
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parents:
diff changeset
260 minv,maxv = get_size_range(size)
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parents:
diff changeset
261 outfile.write('\tmove.' + size + ' #' + str(randint(minv, maxv)) + ', (' + str(address) + ').l\n')
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parents:
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262
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parents:
diff changeset
263 def consume_regs(self, program):
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
264 self.reg.consume_regs(program)
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parents:
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265
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parents:
diff changeset
266 class Decrement(object):
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
267 def __init__(self, reg):
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parents:
diff changeset
268 self.reg = reg
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parents:
diff changeset
269
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parents:
diff changeset
270 def __str__(self):
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parents:
diff changeset
271 return '-(' + str(self.reg) + ')'
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parents:
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272
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diff changeset
273 def write_init(self, outfile, size, already):
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
274 if str(self.reg) in already:
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parents:
diff changeset
275 if not valid_ram_address(already[str(self.reg)]- 4 if size == 'l' else 2 if size == 'w' else 1, size):
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parents:
diff changeset
276 del already[str(self.reg)]
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parents:
diff changeset
277 self.write_init(outfile, size, already)
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278 return
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parents:
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279 else:
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280 address = already[str(self.reg)]
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281 else:
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282 address = random_ram_address(mina=0xE00004)
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283 if size != 'b':
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284 address = address & 0xFFFFFFFE
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285 outfile.write('\tmove.l #' + str(address) + ', ' + str(self.reg) + '\n')
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286 already[str(self.reg)] = address
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diff changeset
287 minv,maxv = get_size_range(size)
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diff changeset
288 outfile.write('\tmove.' + size + ' #' + str(randint(minv, maxv)) + ', (' + str(address) + ').l\n')
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289
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290 def consume_regs(self, program):
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parents:
diff changeset
291 self.reg.consume_regs(program)
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292
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293 class Absolute(object):
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294 def __init__(self, address, size):
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295 self.address = address
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296 self.size = size
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297
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diff changeset
298 def __str__(self):
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299 return '(' + str(self.address) + ').' + self.size
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parents:
diff changeset
300
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301 def write_init(self, outfile, size, already):
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302 minv,maxv = get_size_range(size)
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303 outfile.write('\tmove.' + size + ' #' + str(randint(minv, maxv)) + ', '+str(self)+'\n')
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parents:
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304
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305 def consume_regs(self, program):
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306 pass
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parents:
diff changeset
307
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308 class Immediate(object):
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parents:
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309 def __init__(self, value):
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310 self.value = value
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311
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parents:
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312 def __str__(self):
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parents:
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313 return '#' + str(self.value)
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parents:
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314
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parents:
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315 def write_init(self, outfile, size, already):
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parents:
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316 pass
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parents:
diff changeset
317
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parents:
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318 def consume_regs(self, program):
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parents:
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319 pass
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parents:
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320
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321 all_dregs = [Register('d', i) for i in range(0, 8)]
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parents:
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322 all_aregs = [Register('a', i) for i in range(0, 8)]
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parents:
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323 all_indirect = [Indirect(reg) for reg in all_aregs]
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parents:
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324 all_predec = [Decrement(reg) for reg in all_aregs]
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parents:
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325 all_postinc = [Increment(reg) for reg in all_aregs]
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parents:
diff changeset
326 from random import randint
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parents:
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327 def all_indexed():
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parents:
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328 return [Indexed(base, index, index_size, randint(-128, 127)) for base in all_aregs for index in all_dregs + all_aregs for index_size in ('w','l')]
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Mike Pavone <pavone@retrodev.com>
parents:
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329
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parents:
diff changeset
330 def all_disp():
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Mike Pavone <pavone@retrodev.com>
parents:
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331 return [Displacement(base, randint(-32768, 32767)) for base in all_aregs]
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
332
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parents:
diff changeset
333 def rand_pc_disp():
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parents:
diff changeset
334 return [Displacement(Register('pc', 0), randint(-32768, -1024)) for x in xrange(0, 8)]
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
335
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parents:
diff changeset
336 def all_pc_indexed():
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
337 return [Indexed(Register('pc', 0), index, index_size, randint(-128, 127)) for index in all_dregs + all_aregs for index_size in ('w','l')]
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
338
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parents:
diff changeset
339 def rand_abs_short():
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
340 return [Absolute(0xFFFF8000 + randint(0, 32767), 'w') for x in xrange(0, 8)]
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parents:
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341
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parents:
diff changeset
342 def rand_abs_long():
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
343 return [Absolute(0xFF0000 + randint(0, 65535), 'l') for x in xrange(0, 8)]
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parents:
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344
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parents:
diff changeset
345 def get_size_range(size):
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parents:
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346 if size == 'b':
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parents:
diff changeset
347 return (-128, 127)
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parents:
diff changeset
348 elif size == 'w':
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parents:
diff changeset
349 return (-32768, 32767)
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parents:
diff changeset
350 else:
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
351 return (-2147483648, 2147483647)
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parents:
diff changeset
352
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parents:
diff changeset
353 def rand_immediate(size):
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parents:
diff changeset
354 minv,maxv = get_size_range(size)
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parents:
diff changeset
355
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parents:
diff changeset
356 return [Immediate(randint(minv, maxv)) for x in xrange(0,8)]
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parents:
diff changeset
357
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parents:
diff changeset
358 def get_variations(mode, size):
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parents:
diff changeset
359 mapping = {
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diff changeset
360 'd':all_dregs,
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parents:
diff changeset
361 'a':all_aregs,
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
362 '(a)':all_indirect,
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
363 '-(a)':all_predec,
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
364 '(a)+':all_postinc,
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
365 '(n,a)':all_disp,
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parents:
diff changeset
366 '(n,a,x)':all_indexed,
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
367 '(n,pc)':rand_pc_disp,
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
368 '(n,pc,x)':all_pc_indexed,
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parents:
diff changeset
369 '(n).w':rand_abs_short,
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parents:
diff changeset
370 '(n).l':rand_abs_long
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parents:
diff changeset
371 }
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
372 if mode in mapping:
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parents:
diff changeset
373 ret = mapping[mode]
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parents:
diff changeset
374 if type(ret) != list:
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diff changeset
375 ret = ret()
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parents:
diff changeset
376 return ret
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parents:
diff changeset
377 elif mode == '#n':
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parents:
diff changeset
378 return rand_immediate(size)
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parents:
diff changeset
379 elif mode.startswith('#(') and mode.endswith(')'):
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diff changeset
380 inner = mode[2:-1]
224
f7ff02eeec2f Added testcases for move and roxl/roxr. Made some small improvements to test tools.
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parents: 220
diff changeset
381 start,sep,end = inner.rpartition('-')
220
cb72780e17b1 Add support for picking random numbers in a larger range in test generator. Add support for running a subset of tests in runner. Added testcases for bit and rotate instructions.
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parents: 217
diff changeset
382 start,end = int(start),int(end)
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parents: 217
diff changeset
383 if end-start > 16:
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parents: 217
diff changeset
384 return [Immediate(randint(start, end)) for x in range(0,8)]
cb72780e17b1 Add support for picking random numbers in a larger range in test generator. Add support for running a subset of tests in runner. Added testcases for bit and rotate instructions.
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parents: 217
diff changeset
385 else:
cb72780e17b1 Add support for picking random numbers in a larger range in test generator. Add support for running a subset of tests in runner. Added testcases for bit and rotate instructions.
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parents: 217
diff changeset
386 return [Immediate(num) for num in range(start, end+1)]
217
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
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parents: 214
diff changeset
387 else:
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parents: 214
diff changeset
388 print "Don't know what to do with source type", mode
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
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parents: 214
diff changeset
389 return None
214
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parents:
diff changeset
390
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parents:
diff changeset
391 class Inst2Op(object):
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parents:
diff changeset
392 def __init__(self, name, size, src, dst):
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parents:
diff changeset
393 self.name = name
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parents:
diff changeset
394 self.size = size
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parents:
diff changeset
395 self.src = src
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parents:
diff changeset
396 self.dst = dst
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parents:
diff changeset
397
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
398 def __str__(self):
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parents:
diff changeset
399 return self.name + '.' + self.size + ' ' + str(self.src) + ', ' + str(self.dst)
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parents:
diff changeset
400
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parents:
diff changeset
401 def write_init(self, outfile, already):
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parents:
diff changeset
402 self.src.write_init(outfile, self.size, already)
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parents:
diff changeset
403 self.dst.write_init(outfile, self.size, already)
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
404
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
405 def invalidate_dest(self, already):
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
406 if type(self.dst) == Register:
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parents:
diff changeset
407 del already[str(self.dst)]
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
408
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
409 def save_result(self, reg, always):
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parents:
diff changeset
410 if always or type(self.dst) != Register:
217
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
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parents: 214
diff changeset
411 if type(self.dst) == Decrement:
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
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parents: 214
diff changeset
412 src = Increment(self.dst.reg)
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
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parents: 214
diff changeset
413 elif type(self.dst) == Increment:
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
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parents: 214
diff changeset
414 src = Decrement(self.dst.reg)
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
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parents: 214
diff changeset
415 else:
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
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parents: 214
diff changeset
416 src = self.dst
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
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parents: 214
diff changeset
417 return 'move.' + self.size + ' ' + str(src) + ', ' + str(reg)
214
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
418 else:
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
419 return ''
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
420
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
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421 def consume_regs(self, program):
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422 self.src.consume_regs(program)
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423 self.dst.consume_regs(program)
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424
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425 class Entry(object):
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426 def __init__(self, line):
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427 fields = split_fields(line)
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428 self.name = fields[0]
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429 sizes = fields[1]
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430 sources = fields[2].split(';')
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431 dests = fields[3].split(';')
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432 combos = []
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433 for size in sizes:
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434 for source in sources:
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435 if size != 'b' or source != 'a':
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436 for dest in dests:
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437 if size != 'b' or dest != 'a':
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438 combos.append((size, source, dest))
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439 self.cases = combos
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440
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441 def programs(self):
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442 res = []
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443 for (size, src, dst) in self.cases:
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444 sources = get_variations(src, size)
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445 dests = get_variations(dst, size)
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446 for source in sources:
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447 for dest in dests:
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448 res.append(Program(Inst2Op(self.name, size, source, dest)))
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449 return res
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450
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451 def process_entries(f):
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452 entries = []
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453 for line in f:
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454 if not line.startswith('Name') and not line.startswith('#') and len(line.strip()) > 0:
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455 entries.append(Entry(line))
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456 return entries
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457
224
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458 from os import path, mkdir
214
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459 def main(args):
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460 entries = process_entries(open('testcases.txt'))
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461 for entry in entries:
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462 programs = entry.programs()
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463 for program in programs:
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464 dname = program.dirname()
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465 if not path.exists('generated_tests/' + dname):
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466 mkdir('generated_tests/' + dname)
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467 f = open('generated_tests/' + dname + '/' + program.name() + '.s68', 'w')
214
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468 program.write_rom_test(f)
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469 f.close()
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470
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471 if __name__ == '__main__':
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472 import sys
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473 main(sys.argv)
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474