view fib.s68 @ 2048:ed9a6de28158 mame_interp

Always use "call" style interp generation from CPU DSL and default to NEW_CORE in mame_interp branch
author Michael Pavone <pavone@retrodev.com>
date Tue, 21 Sep 2021 23:28:54 -0700
parents b7ecd0d6a77b
children
line wrap: on
line source

    dc.l $0, start
start:
	moveq #42, d0
	bsr fib
	reset
fib:
	cmp.l #2, d0
	blt base
	subq.l #1, d0
	move.l d0, -(a7)
	bsr fib
	move.l (a7), d1
	exg d0, d1
	move.l d1, (a7)
	subq.l #1, d0
	bsr fib
	move.l (a7)+, d1
	add.l d1, d0
	rts
base:
	moveq #1, d0
	rts