# HG changeset patch
# User Michael Pavone <pavone@retrodev.com>
# Date 1585435613 25200
# Node ID 00fb998054453261542102b396514493c93698d5
# Parent  f2ed8df7a00278541c0404b83d4411f3f66825e8
Skip invalid registers when dumping initial YM2612 state to VGM log

diff -r f2ed8df7a002 -r 00fb99805445 ym2612.c
--- a/ym2612.c	Sat Mar 28 15:46:30 2020 -0700
+++ b/ym2612.c	Sat Mar 28 15:46:53 2020 -0700
@@ -784,10 +784,18 @@
 	vgm_ym2612_init(vgm, 6 * master_clock / context->clock_inc);
 	context->vgm = vgm;
 	for (uint8_t reg = YM_PART1_START; reg < YM_REG_END; reg++) {
+		if ((reg >= REG_DETUNE_MULT && (reg & 3) == 3) || (reg >= 0x2D && reg < REG_DETUNE_MULT) || reg == 0x23 || reg == 0x29) {
+			//skip invalid registers
+			continue;
+		}
 		vgm_ym2612_part1_write(context->vgm, context->current_cycle, reg, context->part1_regs[reg - YM_PART1_START]);
 	}
 	
 	for (uint8_t reg = YM_PART2_START; reg < YM_REG_END; reg++) {
+		if ((reg & 3) == 3 || (reg >= REG_FNUM_LOW_CH3 && reg < REG_ALG_FEEDBACK)) {
+			//skip invalid registers
+			continue;
+		}
 		vgm_ym2612_part2_write(context->vgm, context->current_cycle, reg, context->part2_regs[reg - YM_PART2_START]);
 	}
 }