# HG changeset patch
# User Mike Pavone <pavone@retrodev.com>
# Date 1379311217 25200
# Node ID 1358045c0bdd6f3d63ae20c77240a340c9debc8e
# Parent  93dc0382fd708b9046f0c007f32830b612153389
Implement undocumented 8-bit VRAM read

diff -r 93dc0382fd70 -r 1358045c0bdd vdp.c
--- a/vdp.c	Sun Sep 15 22:43:01 2013 -0700
+++ b/vdp.c	Sun Sep 15 23:00:17 2013 -0700
@@ -378,12 +378,22 @@
 	context->colors[addr + CRAM_SIZE*2] = color_map[(value & 0xEEE) | FBUF_HILIGHT];
 }
 
-#define VRAM_READ 0
-#define VRAM_WRITE 1
-#define CRAM_READ 8
-#define CRAM_WRITE 3
-#define VSRAM_READ 4
-#define VSRAM_WRITE 5
+#define VRAM_READ 0 //0000
+#define VRAM_WRITE 1 //0001
+//2 would trigger register write 0010
+#define CRAM_WRITE 3 //0011
+#define VSRAM_READ 4 //0100
+#define VSRAM_WRITE 5//0101
+//6 would trigger regsiter write 0110
+//7 is a mystery
+#define CRAM_READ 8  //1000
+//9 is also a mystery //1001
+//A would trigger register write 1010
+//B is a mystery 1011
+#define VRAM_READ8 0xC //1100
+//D is a mystery 1101
+//E would trigger register write 1110
+//F is a mystery 1111
 #define DMA_START 0x20
 
 void external_slot(vdp_context * context)
@@ -1591,6 +1601,10 @@
 		}
 		value |= context->vdpmem[context->address | 1];
 		break;
+	case VRAM_READ8:
+		value = context->vdpmem[context->address ^ 1];
+		value |= context->fifo[context->fifo_write].value & 0xFF00;
+		break;
 	case CRAM_READ:
 		value = context->cram[(context->address/2) & (CRAM_SIZE-1)] & CRAM_BITS;
 		value |= context->fifo[context->fifo_write].value & ~CRAM_BITS;