# HG changeset patch
# User Mike Pavone <pavone@retrodev.com>
# Date 1368332371 25200
# Node ID 146c87616b050e2b8e84f21fd416ab57c241ab74
# Parent  67b6d351df0e99e79ef2e7fc97ada64324748939
Don't update interrupt mask on non-interrupt exceptions

diff -r 67b6d351df0e -r 146c87616b05 blastem.c
--- a/blastem.c	Sat May 11 01:57:41 2013 -0700
+++ b/blastem.c	Sat May 11 21:19:31 2013 -0700
@@ -180,7 +180,7 @@
 		z_context->current_cycle = mclks / MCLKS_PER_Z80;
 	}
 }
-
+uint32_t frame=0;
 m68k_context * sync_components(m68k_context * context, uint32_t address)
 {
 	//TODO: Handle sync targets smaller than a single frame
@@ -197,6 +197,7 @@
 		if (!headless) {
 			break_on_sync |= wait_render_frame(v_context);
 		}
+		frame++;
 		mclks -= MCLKS_PER_FRAME;
 		vdp_adjust_cycles(v_context, MCLKS_PER_FRAME);
 		io_adjust_cycles(&gamepad_1, context->current_cycle, MCLKS_PER_FRAME/MCLKS_PER_68K);
diff -r 67b6d351df0e -r 146c87616b05 m68k_to_x86.c
--- a/m68k_to_x86.c	Sat May 11 01:57:41 2013 -0700
+++ b/m68k_to_x86.c	Sat May 11 21:19:31 2013 -0700
@@ -46,6 +46,7 @@
 void bcd_add();
 void bcd_sub();
 void m68k_start_context(uint8_t * addr, m68k_context * context);
+void debug_print_sr();
 
 uint8_t * cycles(uint8_t * dst, uint32_t num)
 {
@@ -2927,6 +2928,7 @@
 				dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, opts->aregs[7], SZ_B);
 				dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, SZ_B);
 			}
+			//dst = call(dst, (uint8_t *)debug_print_sr);
 			if (inst->src.params.immed & 0x700) {
 				dst = call(dst, (uint8_t *)do_sync);
 			}
@@ -3224,6 +3226,7 @@
 		}
 		if (inst->op == M68K_ORI_SR) {
 			dst = xor_irdisp8(dst, inst->src.params.immed >> 8, CONTEXT, offsetof(m68k_context, status), SZ_B);
+			//dst = call(dst, (uint8_t *)debug_print_sr);
 			if (inst->src.params.immed & 0x700) {
 				dst = call(dst, (uint8_t *)do_sync);
 			}
@@ -3284,6 +3287,7 @@
 					dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, opts->aregs[7], SZ_D);
 					dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, SZ_D);
 				}
+				//dst = call(dst, (uint8_t *)debug_print_sr);
 				dst = call(dst, (uint8_t *)do_sync);
 			}
 			dst = cycles(dst, 12);
@@ -3472,6 +3476,7 @@
 		}
 		if (inst->op == M68K_ORI_SR) {
 			dst = or_irdisp8(dst, inst->src.params.immed >> 8, CONTEXT, offsetof(m68k_context, status), SZ_B);
+			//dst = call(dst, (uint8_t *)debug_print_sr);
 			if (inst->src.params.immed & 0x700) {
 				dst = call(dst, (uint8_t *)do_sync);
 			}
diff -r 67b6d351df0e -r 146c87616b05 runtime.S
--- a/runtime.S	Sat May 11 01:57:41 2013 -0700
+++ b/runtime.S	Sat May 11 21:19:31 2013 -0700
@@ -45,6 +45,9 @@
 	mov %cx, 6(%rsi) /* interrupt acknowlege */
 	shl $2, %ecx
 	add $0x60, %ecx
+	/* push %rcx
+	call debug_print_sr_int
+	pop %rcx */
 	call m68k_read_long_scratch1
 	call m68k_native_addr_and_sync
 	add $24, %eax
@@ -64,6 +67,33 @@
 skip_sync_int:
 	ret
 	
+sr_msg_int:
+	.asciz "SR set to $%X due to interrupt\n"
+debug_print_sr_int:
+	call m68k_save_context
+	push %rsi
+	lea sr_msg_int(%rip), %rdi
+	movzxb 5(%rsi), %rsi
+	xor %rax, %rax
+	call printf
+	pop %rsi
+	call m68k_load_context
+	ret
+
+sr_msg:
+	.asciz "SR set to $%X\n"
+	.global debug_print_sr
+debug_print_sr:
+	call m68k_save_context
+	push %rsi
+	lea sr_msg(%rip), %rdi
+	movzxb 5(%rsi), %rsi
+	xor %rax, %rax
+	call printf
+	pop %rsi
+	call m68k_load_context
+	ret
+	
 	.global m68k_trap
 m68k_trap:
 	push %rdi
@@ -85,11 +115,8 @@
 	mov %r15d, %edi
 	call get_sr
 	call m68k_write_word
-	/* update status register */
-	andb $0xF8, 5(%rsi)
-	mov 92(%rsi), %cl
-	or $0x20, %cl
-	or %cl, 5(%rsi)
+	/* set supervisor bit */
+	or $0x20, 5(%rsi)
 	/* calculate interrupt vector address */
 	pop %rcx
 	shl $2, %ecx
@@ -212,6 +239,7 @@
 	mov %cl, (%rsi)
 	shr $8, %cx
 	mov %cl, 5(%rsi)
+	/* call debug_print_sr */
 	ret
 
 	.global set_ccr