# HG changeset patch
# User Michael Pavone <pavone@retrodev.com>
# Date 1644478773 28800
# Node ID 17ecd28ddc8a98b43ab55b24923cee2ac12345af
# Parent  539450d905b3e9b31ce813d21f9eafad12ae5d64
Fix handling of address error for 32-bit accesses

diff -r 539450d905b3 -r 17ecd28ddc8a m68k_core_x86.c
--- a/m68k_core_x86.c	Wed Feb 09 23:39:03 2022 -0800
+++ b/m68k_core_x86.c	Wed Feb 09 23:39:33 2022 -0800
@@ -2738,6 +2738,10 @@
 	opts->write_8 = gen_mem_fun(&opts->gen, memmap, num_chunks, WRITE_8, NULL);
 
 	opts->read_32 = code->cur;
+	if (opts->gen.align_error_mask) {
+		test_ir(code, opts->gen.align_error_mask, opts->gen.scratch1, SZ_D);
+		jcc(code, CC_NZ, opts->gen.handle_align_error_read);
+	}
 	push_r(code, opts->gen.scratch1);
 	call(code, opts->read_16);
 	mov_rr(code, opts->gen.scratch1, opts->gen.scratch2, SZ_W);
@@ -2752,6 +2756,10 @@
 	retn(code);
 
 	opts->write_32_lowfirst = code->cur;
+	if (opts->gen.align_error_mask) {
+		test_ir(code, opts->gen.align_error_mask, opts->gen.scratch2, SZ_D);
+		jcc(code, CC_NZ, opts->gen.handle_align_error_write);
+	}
 	push_r(code, opts->gen.scratch2);
 	push_r(code, opts->gen.scratch1);
 	add_ir(code, 2, opts->gen.scratch2, SZ_D);
@@ -2762,6 +2770,10 @@
 	jmp(code, opts->write_16);
 
 	opts->write_32_highfirst = code->cur;
+	if (opts->gen.align_error_mask) {
+		test_ir(code, opts->gen.align_error_mask, opts->gen.scratch2, SZ_D);
+		jcc(code, CC_NZ, opts->gen.handle_align_error_write);
+	}
 	push_r(code, opts->gen.scratch1);
 	push_r(code, opts->gen.scratch2);
 	shr_ir(code, 16, opts->gen.scratch1, SZ_D);