# HG changeset patch
# User Michael Pavone <pavone@retrodev.com>
# Date 1587700634 25200
# Node ID 1dae9060519944bee6cadf1adb91b824d0943c63
# Parent  f23e70fb6607b457fcd75ab8b2a7b1dc4c2e8abe
Fix autogenerated temp variables in interrupt subroutine in CPU DSL

diff -r f23e70fb6607 -r 1dae90605199 cpu_dsl.py
--- a/cpu_dsl.py	Sat Apr 18 23:14:43 2020 -0700
+++ b/cpu_dsl.py	Thu Apr 23 20:57:14 2020 -0700
@@ -1597,7 +1597,11 @@
 				pieces.append('\n\t\tif (context->cycles >= context->sync_cycle) {')
 				self.meta = {}
 				self.temp = {}
-				self.subroutines[self.interrupt].inline(self, [], pieces, otype, None)
+				intpieces = []
+				self.subroutines[self.interrupt].inline(self, [], intpieces, otype, None)
+				for size in self.temp:
+					pieces.append('\n\tuint{sz}_t gen_tmp{sz}__;'.format(sz=size))
+				pieces += intpieces
 				pieces.append('\n\t\t}')
 			self.meta = {}
 			self.temp = {}