# HG changeset patch
# User Michael Pavone <pavone@retrodev.com>
# Date 1739675500 28800
# Node ID 2de52352936c58860ec5edf3e9500382e03edc4c
# Parent  fbb5115b1a275ab034aead47a9ee5323766f22a2
Fix lsl in new CPU core and make asl less broken

diff -r fbb5115b1a27 -r 2de52352936c cpu_dsl.py
--- a/cpu_dsl.py	Sat Feb 15 01:35:38 2025 -0800
+++ b/cpu_dsl.py	Sat Feb 15 19:11:40 2025 -0800
@@ -542,11 +542,13 @@
 			if calc == 'sign':
 				resultBit = prog.getLastSize() - 1
 			elif calc == 'carry':
-				if prog.lastOp.op in ('asr', 'lsr', 'rrc'):
+				if prog.lastOp.op in ('asr', 'lsr', 'rrc', 'rlc'):
 					if type(prog.lastB) is int:
 						if prog.lastB == 0:
 							explicit[flag] = 0
 							continue
+						elif prog.lastOp.op == 'rlc':
+							resultBit = prog.getLastSize() - prog.lastB
 						else:
 							resultBit = prog.lastB - 1
 					else:
@@ -554,23 +556,12 @@
 						_addExplicitFlagSet(prog, output, flag, 0)
 						output.append('\n\t} else {')
 						after = '\n\t}'
-						resultBit = f'({prog.lastB} - 1)'
-					myRes = prog.lastA
-				elif prog.lastOp.op == 'rlc':
-					if type(prog.lastB) is int:
-						if prog.lastB == 0:
-							explicit[flag] = 0
-							continue
+						if prog.lastOp.op == 'rlc':
+							resultBit = f'({prog.getLastSize()} - {prog.lastB})'
 						else:
-							resultBit = prog.getLastSize() - prog.lastB
-					else:
-						output.append(f'\n\tif (!{prog.lastB}) {{')
-						_addExplicitFlagSet(prog, output, flag, 0)
-						output.append('\n\t} else {')
-						after = '\n\t}'
-						resultBit = f'({prog.getLastSize()} - {prog.lastB})'
+							resultBit = f'({prog.lastB} - 1)'
 					myRes = prog.lastA
-				elif prog.lastOp.op == 'rol':
+				elif prog.lastOp.op in('rol', 'ror'):
 					if type(prog.lastBUnmasked) is int:
 						if prog.lastBUnmasked == 0:
 							explicit[flag] = 0
@@ -580,18 +571,10 @@
 						_addExplicitFlagSet(prog, output, flag, 0)
 						output.append('\n\t} else {')
 						after = '\n\t}'
-					resultBit = 0
-				elif prog.lastOp.op == 'ror':
-					if type(prog.lastBUnmasked) is int:
-						if prog.lastBUnmasked == 0:
-							explicit[flag] = 0
-							continue
+					if prog.lastOp.op == 'ror':
+						resultBit = prog.getLastSize() - 1
 					else:
-						output.append(f'\n\tif (!{prog.lastBUnmasked}) {{')
-						_addExplicitFlagSet(prog, output, flag, 0)
-						output.append('\n\t} else {')
-						after = '\n\t}'
-					resultBit = prog.getLastSize() - 1
+						resultBit = 0
 				elif prog.lastOp.op == 'neg':
 					if prog.carryFlowDst:
 						realSize = prog.getLastSize()
@@ -610,6 +593,16 @@
 						))
 					continue
 				else:
+					if prog.lastOp.op == 'lsl':
+						if type(prog.lastB) is int:
+							if prog.lastB == 0:
+								explicit[flag] = 0
+								continue
+						else:
+							output.append(f'\n\tif (!{prog.lastB}) {{')
+							_addExplicitFlagSet(prog, output, flag, 0)
+							output.append('\n\t} else {')
+							after = '\n\t}'
 					resultBit = prog.getLastSize()
 			elif calc == 'half':
 				resultBit = prog.getLastSize() - 4
@@ -655,6 +648,7 @@
 		elif calc == 'zero':
 			if prog.carryFlowDst:
 				realSize = prog.getLastSize()
+				output.append(f'\n\t//realSize = {realSize}, carryFlowDst size = {prog.paramSize(prog.carryFlowDst)}, carryFLowDst = {prog.carryFlowDst}')
 				if realSize != prog.paramSize(prog.carryFlowDst):
 					lastDst = '({res} & {mask})'.format(res=lastDst, mask = (1 << realSize) - 1)
 			if type(storage) is tuple:
@@ -2221,6 +2215,9 @@
 			return self.regs.regArrays[begin][0]
 		if self.regs.isReg(name):
 			return self.regs.regs[name]
+		for size in self.temp:
+			if self.temp[size] == name:
+				return size
 		return 32
 	
 	def getLastSize(self):
diff -r fbb5115b1a27 -r 2de52352936c m68k.cpu
--- a/m68k.cpu	Sat Feb 15 01:35:38 2025 -0800
+++ b/m68k.cpu	Sat Feb 15 19:11:40 2025 -0800
@@ -1573,8 +1573,59 @@
 	invalid Z 3
 	local shift 8
 	and dregs.C 63 shift
-	lsl dregs.R shift dregs.R Z
-	update_flags XNZV0C
+	switch Z
+	case 2
+		if shift >=U 32
+			if shift = 32
+				lsl dregs.R 31 dregs.R Z
+				lsl dregs.R 1 dregs.R Z
+				update_flags XN0Z1V0C
+			else
+				dregs.R:Z = 0
+				update_flags X0N0Z1V0C0
+			end
+		else
+			lsl dregs.R shift dregs.R Z
+			update_flags NZV0C
+			if shift
+				xflag = cflag
+			end
+		end
+	case 1
+		if shift >=U 16
+			if shift = 16
+				lsl dregs.R 15 dregs.R Z
+				lsl dregs.R 1 dregs.R Z
+				update_flags XN0Z1V0C
+			else
+				dregs.R:Z = 0
+				update_flags X0N0Z1V0C0
+			end
+		else
+			lsl dregs.R shift dregs.R Z
+			update_flags NZV0C
+			if shift
+				xflag = cflag
+			end
+		end
+	case 0
+		if shift >=U 8
+			if shift = 8
+				lsl dregs.R 7 dregs.R Z
+				lsl dregs.R 1 dregs.R Z
+				update_flags XN0Z1V0C
+			else
+				dregs.R:Z = 0
+				update_flags X0N0Z1V0C0
+			end
+		else
+			lsl dregs.R shift dregs.R Z
+			update_flags NZV0C
+			if shift
+				xflag = cflag
+			end
+		end
+	end
 	add shift shift shift
 	switch Z
 	case 2
@@ -1628,8 +1679,60 @@
 	invalid Z 3
 	local shift 8
 	and dregs.C 63 shift
-	lsl dregs.R shift dregs.R Z
-	update_flags XNZV0C
+	#TODO: implement loops and do this a bit at a time to implement V flag
+	switch Z
+	case 2
+		if shift >=U 32
+			if shift = 32
+				lsl dregs.R 31 dregs.R Z
+				lsl dregs.R 1 dregs.R Z
+				update_flags XNZ1V0C
+			else
+				dregs.R:Z = 0
+				update_flags X0N0Z1V0C0
+			end
+		else
+			lsl dregs.R shift dregs.R Z
+			update_flags NZV0C
+			if shift
+				xflag = cflag
+			end
+		end
+	case 1
+		if shift >=U 16
+			if shift = 16
+				lsl dregs.R 15 dregs.R Z
+				lsl dregs.R 1 dregs.R Z
+				update_flags XN0Z1V0C
+			else
+				dregs.R:Z = 0
+				update_flags X0N0Z1V0C0
+			end
+		else
+			lsl dregs.R shift dregs.R Z
+			update_flags NZV0C
+			if shift
+				xflag = cflag
+			end
+		end
+	case 0
+		if shift >=U 8
+			if shift = 8
+				lsl dregs.R 7 dregs.R Z
+				lsl dregs.R 1 dregs.R Z
+				update_flags XN0Z1V0C
+			else
+				dregs.R:Z = 0
+				update_flags X0N0Z1V0C0
+			end
+		else
+			lsl dregs.R shift dregs.R Z
+			update_flags NZV0C
+			if shift
+				xflag = cflag
+			end
+		end
+	end
 	add shift shift shift
 	switch Z
 	case 2