# HG changeset patch # User Michael Pavone # Date 1419720710 28800 # Node ID 314373222b1aa6cc5188bd69771737a0c0a85766 # Parent 66b730a8ae5189f8aa81f723cd7d4ba93a442a9a Decrement address register after fetching source in move with -(ax) dest to avoid bug when src is the dst addres reg diff -r 66b730a8ae51 -r 314373222b1a m68k_core_x86.c --- a/m68k_core_x86.c Sat Dec 27 14:50:50 2014 -0800 +++ b/m68k_core_x86.c Sat Dec 27 14:51:50 2014 -0800 @@ -604,10 +604,8 @@ break; case MODE_AREG_PREDEC: dec_amount = inst->extra.size == OPSIZE_WORD ? 2 : (inst->extra.size == OPSIZE_LONG ? 4 : (inst->dst.params.regs.pri == 7 ? 2 : 1)); - subi_areg(opts, dec_amount, inst->dst.params.regs.pri); case MODE_AREG_INDIRECT: case MODE_AREG_POSTINC: - areg_to_native(opts, inst->dst.params.regs.pri, opts->gen.scratch2); if (src.mode == MODE_REG_DIRECT) { if (src.base != opts->gen.scratch1) { mov_rr(code, src.base, opts->gen.scratch1, inst->extra.size); @@ -617,6 +615,10 @@ } else { mov_ir(code, src.disp, opts->gen.scratch1, inst->extra.size); } + if (inst->dst.addr_mode == MODE_AREG_PREDEC) { + subi_areg(opts, dec_amount, inst->dst.params.regs.pri); + } + areg_to_native(opts, inst->dst.params.regs.pri, opts->gen.scratch2); break; case MODE_AREG_DISPLACE: cycles(&opts->gen, BUS);