# HG changeset patch
# User Michael Pavone <pavone@retrodev.com>
# Date 1587863440 25200
# Node ID 35722beaf89562c89108e2a760d800545d2c4bf9
# Parent  9eec86183aae95f584d340ebce7df6baae84391b
Fix instruction timing for addq.w #i, (ay) in dynarec

diff -r 9eec86183aae -r 35722beaf895 m68k_core_x86.c
--- a/m68k_core_x86.c	Fri Apr 24 09:23:43 2020 -0700
+++ b/m68k_core_x86.c	Sat Apr 25 18:10:40 2020 -0700
@@ -1315,8 +1315,6 @@
 			numcycles = 6;
 		} else if (inst->op == M68K_AND && inst->variant == VAR_IMMEDIATE) {
 			numcycles = 6;
-		} else if (inst->op == M68K_ADD && inst->dst.addr_mode == MODE_AREG && inst->extra.size == OPSIZE_WORD && inst->variant == VAR_QUICK) {
-			numcycles = 4;
 		} else if (inst->dst.addr_mode <= MODE_AREG) {
 			numcycles = inst->src.addr_mode <= MODE_AREG || inst->src.addr_mode == MODE_IMMEDIATE ? 8 : 6;
 		} else {