# HG changeset patch # User Mike Pavone # Date 1367299941 25200 # Node ID 3b34deba4ca05d6f972bfd7cc58f4e8060f4bed5 # Parent 63b9a500a00b5bf95532a5074f0c79eb88f7cadc Squashing some bugs introduced when I switched the register assignments for z80_write_byte around. diff -r 63b9a500a00b -r 3b34deba4ca0 z80_to_x86.c --- a/z80_to_x86.c Mon Apr 29 21:46:48 2013 -0700 +++ b/z80_to_x86.c Mon Apr 29 22:32:21 2013 -0700 @@ -198,10 +198,17 @@ uint8_t * z80_save_result(uint8_t * dst, z80inst * inst) { - if (z80_size(inst) == SZ_B) { - dst = call(dst, (uint8_t *)z80_write_byte); - } else { - dst = call(dst, (uint8_t *)z80_write_word_lowfirst); + switch(inst->addr_mode & 0x1f) + { + case Z80_REG_INDIRECT: + case Z80_IMMED_INDIRECT: + case Z80_IX_DISPLACE: + case Z80_IY_DISPLACE: + if (z80_size(inst) == SZ_B) { + dst = call(dst, (uint8_t *)z80_write_byte); + } else { + dst = call(dst, (uint8_t *)z80_write_word_lowfirst); + } } return dst; } @@ -307,24 +314,24 @@ dst = zcycles(dst, (inst->reg == Z80_IX || inst->reg == Z80_IY) ? 9 : 5); dst = sub_ir(dst, 2, opts->regs[Z80_SP], SZ_W); if (inst->reg == Z80_AF) { - dst = mov_rdisp8r(dst, CONTEXT, zf_off(ZF_S), SCRATCH2, SZ_B); - dst = shl_ir(dst, 1, SCRATCH2, SZ_B); - dst = or_rdisp8r(dst, CONTEXT, zf_off(ZF_Z), SCRATCH2, SZ_B); - dst = shl_ir(dst, 2, SCRATCH2, SZ_B); - dst = or_rdisp8r(dst, CONTEXT, zf_off(ZF_H), SCRATCH2, SZ_B); - dst = shl_ir(dst, 2, SCRATCH2, SZ_B); - dst = or_rdisp8r(dst, CONTEXT, zf_off(ZF_PV), SCRATCH2, SZ_B); - dst = shl_ir(dst, 1, SCRATCH2, SZ_B); - dst = or_rdisp8r(dst, CONTEXT, zf_off(ZF_N), SCRATCH2, SZ_B); - dst = shl_ir(dst, 1, SCRATCH2, SZ_B); - dst = or_rdisp8r(dst, CONTEXT, zf_off(ZF_C), SCRATCH2, SZ_B); - dst = shl_ir(dst, 8, SCRATCH2, SZ_W); - dst = mov_rr(dst, opts->regs[Z80_A], SCRATCH2, SZ_B); + dst = mov_rdisp8r(dst, CONTEXT, zf_off(ZF_S), SCRATCH1, SZ_B); + dst = shl_ir(dst, 1, SCRATCH1, SZ_B); + dst = or_rdisp8r(dst, CONTEXT, zf_off(ZF_Z), SCRATCH1, SZ_B); + dst = shl_ir(dst, 2, SCRATCH1, SZ_B); + dst = or_rdisp8r(dst, CONTEXT, zf_off(ZF_H), SCRATCH1, SZ_B); + dst = shl_ir(dst, 2, SCRATCH1, SZ_B); + dst = or_rdisp8r(dst, CONTEXT, zf_off(ZF_PV), SCRATCH1, SZ_B); + dst = shl_ir(dst, 1, SCRATCH1, SZ_B); + dst = or_rdisp8r(dst, CONTEXT, zf_off(ZF_N), SCRATCH1, SZ_B); + dst = shl_ir(dst, 1, SCRATCH1, SZ_B); + dst = or_rdisp8r(dst, CONTEXT, zf_off(ZF_C), SCRATCH1, SZ_B); + dst = shl_ir(dst, 8, SCRATCH1, SZ_W); + dst = mov_rr(dst, opts->regs[Z80_A], SCRATCH1, SZ_B); } else { dst = translate_z80_reg(inst, &src_op, dst, opts); - dst = mov_rr(dst, src_op.base, SCRATCH2, SZ_W); + dst = mov_rr(dst, src_op.base, SCRATCH1, SZ_W); } - dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH1, SZ_W); + dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH2, SZ_W); dst = call(dst, (uint8_t *)z80_write_word_highfirst); //no call to save_z80_reg needed since there's no chance we'll use the only //the upper half of a register pair @@ -374,7 +381,7 @@ dst = mov_rdisp8r(dst, CONTEXT, zf_off(f), SCRATCH1, SZ_W); dst = mov_rdisp8r(dst, CONTEXT, zaf_off(f), SCRATCH2, SZ_W); dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, zaf_off(f), SZ_W); - dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, zf_off(f), SZ_W); + dst = mov_rrdisp8(dst, SCRATCH2, CONTEXT, zf_off(f), SZ_W); } } else { dst = xchg_rr(dst, opts->regs[Z80_DE], opts->regs[Z80_HL], SZ_W); @@ -382,9 +389,8 @@ } else { dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH1, SZ_W); dst = call(dst, (uint8_t *)z80_read_byte); - dst = mov_rr(dst, opts->regs[inst->reg], SCRATCH2, SZ_B); - dst = mov_rr(dst, SCRATCH1, opts->regs[inst->reg], SZ_B); - dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH1, SZ_W); + dst = xchg_rr(dst, opts->regs[inst->reg], SCRATCH1, SZ_B); + dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH2, SZ_W); dst = call(dst, (uint8_t *)z80_write_byte); dst = zcycles(dst, 1); uint8_t high_reg = z80_high_reg(inst->reg); @@ -397,10 +403,9 @@ dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH1, SZ_W); dst = add_ir(dst, 1, SCRATCH1, SZ_W); dst = call(dst, (uint8_t *)z80_read_byte); - dst = mov_rr(dst, use_reg, SCRATCH2, SZ_B); - dst = mov_rr(dst, SCRATCH1, use_reg, SZ_B); - dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH1, SZ_W); - dst = add_ir(dst, 1, SCRATCH1, SZ_W); + dst = xchg_rr(dst, use_reg, SCRATCH1, SZ_B); + dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH2, SZ_W); + dst = add_ir(dst, 1, SCRATCH2, SZ_W); dst = call(dst, (uint8_t *)z80_write_byte); //restore reg to normal rotation dst = ror_ir(dst, 8, use_reg, SZ_W); @@ -1011,8 +1016,8 @@ case Z80_CALL: { dst = zcycles(dst, 11);//T States: 4,3,4 dst = sub_ir(dst, 2, opts->regs[Z80_SP], SZ_W); - dst = mov_ir(dst, address + 3, SCRATCH2, SZ_W); - dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH1, SZ_W); + dst = mov_ir(dst, address + 3, SCRATCH1, SZ_W); + dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH2, SZ_W); dst = call(dst, (uint8_t *)z80_write_word_highfirst);//T States: 3, 3 if (inst->immed < 0x4000) { uint8_t * call_dst = z80_get_native_address(context, inst->immed); @@ -1058,8 +1063,8 @@ dst = jcc(dst, cond, dst+2); dst = zcycles(dst, 1);//Last of the above T states takes an extra cycle in the true case dst = sub_ir(dst, 2, opts->regs[Z80_SP], SZ_W); - dst = mov_ir(dst, address + 3, SCRATCH2, SZ_W); - dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH1, SZ_W); + dst = mov_ir(dst, address + 3, SCRATCH1, SZ_W); + dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH2, SZ_W); dst = call(dst, (uint8_t *)z80_write_word_highfirst);//T States: 3, 3 if (inst->immed < 0x4000) { uint8_t * call_dst = z80_get_native_address(context, inst->immed); @@ -1125,8 +1130,8 @@ //RST is basically CALL to an address in page 0 dst = zcycles(dst, 5);//T States: 5 dst = sub_ir(dst, 2, opts->regs[Z80_SP], SZ_W); - dst = mov_ir(dst, address + 3, SCRATCH2, SZ_W); - dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH1, SZ_W); + dst = mov_ir(dst, address + 3, SCRATCH1, SZ_W); + dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH2, SZ_W); dst = call(dst, (uint8_t *)z80_write_word_highfirst);//T States: 3, 3 uint8_t * call_dst = z80_get_native_address(context, inst->immed); if (!call_dst) { @@ -1208,7 +1213,7 @@ map->base = native_address; } map->offsets[address] = native_address - map->base; - for(--size; size; --size, orig_address++) { + for(--size, orig_address++; size; --size, orig_address++) { address = orig_address; if (address < 0x4000) { address &= 0x1FFF; diff -r 63b9a500a00b -r 3b34deba4ca0 zruntime.S --- a/zruntime.S Mon Apr 29 21:46:48 2013 -0700 +++ b/zruntime.S Mon Apr 29 22:32:21 2013 -0700 @@ -88,42 +88,42 @@ z80_write_byte: call z_inccycles z80_write_byte_noinc: - cmp $0x4000, %r13w + cmp $0x4000, %r14w jb z80_write_ram - cmp $0x8000, %r13w + cmp $0x8000, %r14w jae z80_write_bank - cmp $0x6000, %r13w + cmp $0x6000, %r14w je z80_write_bank_reg /* TODO: YM-2612, PSG/VDP */ ret z80_write_ram: - and $0x1FFF, %r13 - mov %r14b, (%r11, %r13) - mov %r13d, %r14d - shr $7, %r14d - bt %r14d, 152(%rsi) + and $0x1FFF, %r14 + mov %r13b, (%r11, %r14) + mov %r14d, %r13d + shr $7, %r13d + bt %r13d, 152(%rsi) jnc not_code call z80_save_context - mov %r13d, %edi + mov %r14d, %edi call z80_handle_code_write mov %rax, %rsi not_code: ret z80_write_bank: - and $0x7FFF, %r13 + and $0x7FFF, %r14 cmp $0, %r12 je slow_bank_write /* 68K memory is byte swapped */ - xor $1, %r13 - mov %r14b, (%r12, %r13) + xor $1, %r14 + mov %r13b, (%r12, %r14) ret slow_bank_write: /* TODO: Call into C to implement this */ ret z80_write_bank_reg: - and $1, %r14w + and $1, %r13w shl %r15w - or %r14w, %r15w + or %r13w, %r15w and $0x1FF, %r15w xor %r12, %r12 cmp $0x80, %r15w @@ -154,8 +154,8 @@ call z_inccycles push %r14 push %r13 - add $1, %r13w - shr $8, %r14w + add $1, %r14w + shr $8, %r13w call z80_write_byte_noinc pop %r13 pop %r14 @@ -171,8 +171,8 @@ call z80_write_byte_noinc pop %r13 pop %r14 - add $1, %r13w - shr $8, %r14w + add $1, %r14w + shr $8, %r13w call z_inccycles call z80_write_byte_noinc ret