# HG changeset patch
# User Michael Pavone <pavone@retrodev.com>
# Date 1707752552 28800
# Node ID 461fffc226e02dba83788ceee66c64599b577fcc
# Parent  52cfc7b14dd23158822c24fcd4f8a8d2e7ae66fe
Sugar for unary operators in CPU DSL

diff -r 52cfc7b14dd2 -r 461fffc226e0 cpu_dsl.py
--- a/cpu_dsl.py	Sun Feb 11 20:41:28 2024 -0800
+++ b/cpu_dsl.py	Mon Feb 12 07:42:32 2024 -0800
@@ -19,6 +19,11 @@
 	'|': 'or',
 	'^': 'xor'
 }
+unaryOps = {
+	'~': 'not',
+	'!': 'lnot',
+	'-': 'neg'
+}
 compareOps = {'>=U', '=', '!='}
 class Block:
 	def addOp(self, op):
@@ -50,6 +55,14 @@
 						op = parts[2]
 						parts[0] = binaryOps[op]
 						del parts[2]
+					elif len(parts) > 1 and parts[1][0] in unaryOps:
+						rest = parts[1][1:]
+						op = parts[1][0]
+						if rest:
+							parts[1] = rest
+						else:
+							del parts[1]
+						parts[0] = unaryOps[op]
 				else:
 					if op == '<<=' or op == '>>=':
 						parts.insert(1, dst)
diff -r 52cfc7b14dd2 -r 461fffc226e0 z80.cpu
--- a/z80.cpu	Sun Feb 11 20:41:28 2024 -0800
+++ b/z80.cpu	Mon Feb 12 07:42:32 2024 -0800
@@ -166,30 +166,30 @@
 	switch cond
 	case 0
 		meta istrue invert
-		lnot zflag invert
+		invert = !zflag
 	
 	case 1
 		meta istrue zflag
 	
 	case 2
 		meta istrue invert
-		not chflags invert
+		invert = ~chflags
 		invert &= 0x80
 	
 	case 3
 		meta istrue invert
-		and 0x80 chflags invert
+		invert = chflags & 0x80
 	
 	case 4
 		meta istrue invert
-		lnot pvflag invert
+		invert = !pvflag
 	
 	case 5
 		meta istrue pvflag
 	
 	case 6
 		meta istrue invert
-		not last_flag_result invert
+		invert = ~last_flag_result
 		invert &= 0x80
 	
 	case 7
@@ -1519,11 +1519,11 @@
 	sub 1 iy iy
 
 00101111 cpl
-	not a a
+	a = ~a
 	update_flags YH1XN1
 
 ed 01DDD100 neg
-	neg a a
+	a = -a
 	update_flags SZYHVXN1C
 
 00111111 ccf
@@ -2214,29 +2214,29 @@
 	
 cb 10BBBRRR res_reg
 	local tmp 8
-	lsl 1 B tmp
-	not tmp tmp
-	and main.R tmp main.R
+	tmp = 1 << B
+	tmp = ~tmp
+	main.R &= tmp
 	
 cb 10BBB110 res_hl
 	z80_fetch_hl
 	cycles 1
 	local tmp 8
-	lsl 1 B tmp
-	not tmp tmp
-	and scratch1 tmp scratch1
+	tmp = 1 << B
+	tmp = ~tmp
+	scratch1 &= tmp
 	z80_store_hl
 	
 z80_res_index
 	arg bit 8
 	arg tmp 8
-	lsl 1 bit tmp
-	not tmp tmp
-	mov wz scratch1
+	tmp = 1 << bit
+	tmp = ~tmp
+	scratch1 = wz
 	ocall read_8
 	cycles 1
-	and scratch1 tmp tmp
-	mov tmp scratch1
+	tmp &= scratch1
+	scratch1 = tmp
 	z80_store_index
 	
 ddcb 10BBB110 res_ixd