# HG changeset patch
# User Michael Pavone <pavone@retrodev.com>
# Date 1446180130 25200
# Node ID 5822c6e5642f609297ed07d7df0f047c0d958ba4
# Parent  4556818b6847a3e9fb3a625b0684a2fd1ee8b7fb
Fix timing of IM instruction

diff -r 4556818b6847 -r 5822c6e5642f z80_to_x86.c
--- a/z80_to_x86.c	Thu Oct 29 19:06:06 2015 -0700
+++ b/z80_to_x86.c	Thu Oct 29 21:42:10 2015 -0700
@@ -547,12 +547,12 @@
 		mov_rdispr(code, opts->gen.context_reg, zar_off(Z80_BC), opts->gen.scratch2, SZ_W);
 		mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zar_off(Z80_BC), SZ_W);
 		native_to_zreg(opts, opts->gen.scratch2, Z80_BC);
-		
+
 		zreg_to_native(opts, Z80_HL, opts->gen.scratch1);
 		mov_rdispr(code, opts->gen.context_reg, zar_off(Z80_HL), opts->gen.scratch2, SZ_W);
 		mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zar_off(Z80_HL), SZ_W);
 		native_to_zreg(opts, opts->gen.scratch2, Z80_HL);
-		
+
 		zreg_to_native(opts, Z80_DE, opts->gen.scratch1);
 		mov_rdispr(code, opts->gen.context_reg, zar_off(Z80_DE), opts->gen.scratch2, SZ_W);
 		mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zar_off(Z80_DE), SZ_W);
@@ -1010,7 +1010,7 @@
 		} else {
 			sub_irdisp(code, 1, dst_op.base, dst_op.disp, z80_size(inst));
 		}
-		
+
 		if (z80_size(inst) == SZ_B) {
 			mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
 			//TODO: Implement half-carry flag
@@ -1084,7 +1084,7 @@
 		call(code, opts->do_sync);
 		break;
 	case Z80_IM:
-		cycles(&opts->gen, 4);
+		cycles(&opts->gen, 8);
 		mov_irdisp(code, inst->immed, opts->gen.context_reg, offsetof(z80_context, im), SZ_B);
 		break;
 	case Z80_RLC: