# HG changeset patch
# User Mike Pavone <pavone@retrodev.com>
# Date 1367222390 25200
# Node ID 5f1b68cecfc7f112792adb7c2570e132d3999e63
# Parent  d94e6cd5a8a5ce048e2c59aab62fa0ae60e74fdf
Implemented basic interrupt support in Z80 core.

diff -r d94e6cd5a8a5 -r 5f1b68cecfc7 transz80.c
--- a/transz80.c	Mon Apr 29 00:59:32 2013 -0700
+++ b/transz80.c	Mon Apr 29 00:59:50 2013 -0700
@@ -1,12 +1,19 @@
 #include "z80inst.h"
 #include "z80_to_x86.h"
 #include "mem.h"
+#include "vdp.h"
 #include <stdio.h>
 #include <stdlib.h>
 
 uint8_t z80_ram[0x2000];
 uint16_t cart[0x200000];
 
+#define MCLKS_PER_Z80 15
+//TODO: Figure out the exact value for this
+#define MCLKS_PER_FRAME (MCLKS_LINE*262)
+#define VINT_CYCLE ((MCLKS_LINE * 226)/MCLKS_PER_Z80)
+#define CYCLE_NEVER 0xFFFFFFFF
+
 int main(int argc, char ** argv)
 {
 	long filesize;
@@ -38,18 +45,30 @@
 		fseek(f, 0, SEEK_SET);
 		fread(cart, 1, filesize < sizeof(cart) ? filesize : sizeof(cart), f);
 		fclose(f);
+		for(unsigned short * cur = cart; cur - cart < (filesize/2); ++cur)
+		{
+			*cur = (*cur >> 8) | (*cur << 8);
+		}
 	}
 	init_x86_z80_opts(&opts);
 	init_z80_context(&context, &opts);
 	//Z80 RAM
 	context.mem_pointers[0] = z80_ram;
-	context.sync_cycle = context.target_cycle = 0x7FFFFFFF;
+	context.sync_cycle = context.target_cycle = MCLKS_PER_FRAME/MCLKS_PER_Z80;
+	context.int_cycle = CYCLE_NEVER;
 	//cartridge/bank
-	context.mem_pointers[1] = context.mem_pointers[2] = cart;
+	context.mem_pointers[1] = context.mem_pointers[2] = (uint8_t *)cart;
 	z80_reset(&context);
 	for(;;)
 	{
 		z80_run(&context);
+		if (context.current_cycle >= MCLKS_PER_FRAME/MCLKS_PER_Z80) {
+			context.current_cycle -= MCLKS_PER_FRAME/MCLKS_PER_Z80;
+		}
+		if (context.current_cycle < VINT_CYCLE && context.iff1) {
+			context.int_cycle = VINT_CYCLE;
+		}
+		context.target_cycle = context.sync_cycle < context.int_cycle ? context.sync_cycle : context.int_cycle;
 	}
 	return 0;
 }
diff -r d94e6cd5a8a5 -r 5f1b68cecfc7 z80_to_x86.c
--- a/z80_to_x86.c	Mon Apr 29 00:59:32 2013 -0700
+++ b/z80_to_x86.c	Mon Apr 29 00:59:50 2013 -0700
@@ -10,6 +10,7 @@
 #define MODE_UNUSED (MODE_IMMED-1)
 
 #define ZCYCLES RBP
+#define ZLIMIT RDI
 #define SCRATCH1 R13
 #define SCRATCH2 R14
 #define CONTEXT RSI
@@ -24,6 +25,8 @@
 void z80_write_word_lowfirst();
 void z80_save_context();
 void z80_native_addr();
+void z80_do_sync();
+void z80_handle_cycle_limit_int();
 
 uint8_t z80_size(z80inst * inst)
 {
@@ -64,6 +67,17 @@
 	return add_ir(dst, num_cycles, ZCYCLES, SZ_D);
 }
 
+uint8_t * z80_check_cycles_int(uint8_t * dst, uint16_t address)
+{
+	dst = cmp_rr(dst, ZCYCLES, ZLIMIT, SZ_D);
+	uint8_t * jmp_off = dst+1;
+	dst = jcc(dst, CC_NC, dst + 7);
+	dst = mov_ir(dst, address, SCRATCH2, SZ_W);
+	dst = call(dst, (uint8_t *)z80_handle_cycle_limit_int);
+	*jmp_off = dst - (jmp_off+1);
+	return dst;
+}
+
 uint8_t * translate_z80_reg(z80inst * inst, x86_ea * ea, uint8_t * dst, x86_z80_options * opts)
 {
 	if (inst->reg == Z80_USE_IMMED) {
@@ -244,6 +258,7 @@
 	x86_ea src_op, dst_op;
 	uint8_t size;
 	x86_z80_options *opts = context->options;
+	dst = z80_check_cycles_int(dst, address);
 	switch(inst->op)
 	{
 	case Z80_LD:
@@ -697,12 +712,14 @@
 		dst = zcycles(dst, 4);
 		dst = mov_irdisp8(dst, 0, CONTEXT, offsetof(z80_context, iff1), SZ_B);
 		dst = mov_irdisp8(dst, 0, CONTEXT, offsetof(z80_context, iff2), SZ_B);
+		dst = mov_rdisp8r(dst, CONTEXT, offsetof(z80_context, sync_cycle), ZLIMIT, SZ_D);
 		break;
 	case Z80_EI:
 		//TODO: Implement interrupt enable latency of 1 instruction afer EI
 		dst = zcycles(dst, 4);
 		dst = mov_irdisp8(dst, 1, CONTEXT, offsetof(z80_context, iff1), SZ_B);
 		dst = mov_irdisp8(dst, 1, CONTEXT, offsetof(z80_context, iff2), SZ_B);
+		dst = call(dst, (uint8_t *)z80_do_sync);
 		break;
 	case Z80_IM:
 		dst = zcycles(dst, 4);
@@ -1189,6 +1206,9 @@
 	if (!addr) {
 		translate_z80_stream(context, address);
 		addr = z80_get_native_address(context, address);
+		if (!addr) {
+			printf("Failed to translate %X to native code\n", address);
+		}
 	}
 	return addr;
 }