# HG changeset patch
# User Mike Pavone <pavone@retrodev.com>
# Date 1368516525 25200
# Node ID 671a5be515224d28df88668d97230f22f58d8468
# Parent  de17e0352f2791333f2ecbfe430cffb0fec32abc
Update hv counter calculation for clock wonkiness

diff -r de17e0352f27 -r 671a5be51522 vdp.c
--- a/vdp.c	Tue May 14 00:03:26 2013 -0700
+++ b/vdp.c	Tue May 14 00:28:45 2013 -0700
@@ -1151,35 +1151,35 @@
 					inccycles = 20;
 					break;
 				case 59:
-					slot = 2;
+					slot = 3;
 					inccycles = 20;
 					break;
 				case 79:
-					slot = 3;
+					slot = 4;
 					inccycles = 18;
 					break;
 				case 97:
-					slot = 4;
-					inccycles = 20;
-					break;
-				case 117:
 					slot = 5;
 					inccycles = 20;
 					break;
+				case 117:
+					slot = 6;
+					inccycles = 20;
+					break;
 				case 137:
-					slot = 6;
+					slot = 7;
 					inccycles = 20;
 					break;
 				case 157:
-					slot = 7;
+					slot = 8;
 					inccycles = 18;
 					break;
 				case 175:
-					slot = 8;
+					slot = 9;
 					inccycles = 20;
 					break;
 				case 195:
-					slot = 9;
+					slot = 10;
 					inccycles = 20;
 					break;
 				case 215:
@@ -1429,7 +1429,72 @@
 	}
 	uint32_t linecyc = context->cycles % MCLKS_LINE;
 	if (context->latched_mode & BIT_H40) {
-		linecyc /= 8;
+		uint32_t slot;
+		if (linecyc < MCLKS_SLOT_H40*HSYNC_SLOT_H40) {
+			slot = linecyc/MCLKS_SLOT_H40;
+		} else if(linecyc < MCLK_WEIRD_END) {
+			switch(linecyc-(MCLKS_SLOT_H40*HSYNC_SLOT_H40))
+			{
+			case 0:
+				slot = 0;
+				break;
+			case 19:
+				slot = 1;
+				break;
+			case 39:
+				slot = 2;
+				break;
+			case 59:
+				slot = 2;
+				break;
+			case 79:
+				slot = 3;
+				break;
+			case 97:
+				slot = 4;
+				break;
+			case 117:
+				slot = 5;
+				break;
+			case 137:
+				slot = 6;
+				break;
+			case 157:
+				slot = 7;
+				break;
+			case 175:
+				slot = 8;
+				break;
+			case 195:
+				slot = 9;
+				break;
+			case 215:
+				slot = 11;
+				break;
+			case 235:
+				slot = 12;
+				break;
+			case 253:
+				slot = 13;
+				break;
+			case 273:
+				slot = 14;
+				break;
+			case 293:
+				slot = 15;
+				break;
+			case 313:
+				slot = 16;
+				break;
+			default:
+				fprintf(stderr, "cycles after weirdness %d\n", linecyc-(MCLKS_SLOT_H40*HSYNC_SLOT_H40));
+				exit(1);
+			}
+			slot += HSYNC_SLOT_H40;
+		} else {
+			slot = (linecyc-MCLK_WEIRD_END)/MCLKS_SLOT_H40 + SLOT_WEIRD_END;
+		}
+		linecyc = slot * 2;
 		if (linecyc >= 86) {
 			linecyc -= 86;
 		} else {