# HG changeset patch
# User Mike Pavone <pavone@retrodev.com>
# Date 1357379711 28800
# Node ID 6748022656b7e662afaeef98804314e5c3a57b7c
# Parent  69ac23d428974c0e790221243a8679d55a24eafa
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst

diff -r 69ac23d42897 -r 6748022656b7 m68k_to_x86.c
--- a/m68k_to_x86.c	Sat Jan 05 01:32:40 2013 -0800
+++ b/m68k_to_x86.c	Sat Jan 05 01:55:11 2013 -0800
@@ -507,6 +507,7 @@
 		}
 		ea->mode = MODE_REG_DIRECT;
 		ea->base = SCRATCH1;
+		break;
 	case MODE_PC_DISPLACE:
 		out = cycles(out, fake_read ? BUS+(inst->extra.size == OPSIZE_LONG ? BUS*2 : BUS) : BUS);
 		out = mov_ir(out, inst->dst.params.regs.displacement + inst->address+2, fake_read ? SCRATCH2 : SCRATCH1, SZ_D);
@@ -972,7 +973,7 @@
 
 uint8_t * translate_m68k_movem(uint8_t * dst, m68kinst * inst, x86_68k_options * opts)
 {
-	int8_t bit,reg;
+	int8_t bit,reg,sec_reg;
 	uint8_t early_cycles;
 	if(inst->src.addr_mode == MODE_REG) {
 		//reg to mem
@@ -995,6 +996,100 @@
 				dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->dst)), SCRATCH2, SZ_D);
 			}
 			break;
+		case MODE_AREG_DISPLACE:
+			early_cycles += BUS;
+			reg = SCRATCH2;
+			if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
+				dst = mov_rr(dst, opts->aregs[inst->dst.params.regs.pri], SCRATCH2, SZ_D);
+			} else {
+				dst = mov_rdisp8r(dst, CONTEXT,  reg_offset(&(inst->dst)), SCRATCH2, SZ_D);
+			}
+			dst = add_ir(dst, inst->dst.params.regs.displacement, SCRATCH2, SZ_D);
+			break;
+		case MODE_AREG_INDEX_DISP8:
+			early_cycles += 6;
+			if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
+				dst = mov_rr(dst, opts->aregs[inst->dst.params.regs.pri], SCRATCH2, SZ_D);
+			} else {
+				dst = mov_rdisp8r(dst, CONTEXT,  reg_offset(&(inst->dst)), SCRATCH2, SZ_D);
+			}
+			sec_reg = (inst->dst.params.regs.sec >> 1) & 0x7;
+			if (inst->dst.params.regs.sec & 1) {
+				if (inst->dst.params.regs.sec & 0x10) {
+					if (opts->aregs[sec_reg] >= 0) {
+						dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_D);
+					} else {
+						dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_D);
+					}
+				} else {
+					if (opts->dregs[sec_reg] >= 0) {
+						dst = add_rr(dst, opts->dregs[sec_reg], SCRATCH2, SZ_D);
+					} else {
+						dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_D);
+					}
+				}
+			} else {
+				if (inst->dst.params.regs.sec & 0x10) {
+					if (opts->aregs[sec_reg] >= 0) {
+						dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_W, SZ_D);
+					} else {
+						dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_W, SZ_D);
+					}
+				} else {
+					if (opts->dregs[sec_reg] >= 0) {
+						dst = movsx_rr(dst, opts->dregs[sec_reg], SCRATCH1, SZ_W, SZ_D);
+					} else {
+						dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_W, SZ_D);
+					}
+				}
+				dst = add_rr(dst, SCRATCH1, SCRATCH2, SZ_D);
+			}
+			if (inst->dst.params.regs.displacement) {
+				dst = add_ir(dst, inst->dst.params.regs.displacement, SCRATCH2, SZ_D);
+			}
+			break;
+		case MODE_PC_DISPLACE:
+			early_cycles += BUS;
+			dst = mov_ir(dst, inst->dst.params.regs.displacement + inst->address+2, SCRATCH2, SZ_D);
+			break;
+		case MODE_PC_INDEX_DISP8:
+			early_cycles += 6;
+			dst = mov_ir(dst, inst->address+2, SCRATCH2, SZ_D);
+			sec_reg = (inst->dst.params.regs.sec >> 1) & 0x7;
+			if (inst->dst.params.regs.sec & 1) {
+				if (inst->dst.params.regs.sec & 0x10) {
+					if (opts->aregs[sec_reg] >= 0) {
+						dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_D);
+					} else {
+						dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_D);
+					}
+				} else {
+					if (opts->dregs[sec_reg] >= 0) {
+						dst = add_rr(dst, opts->dregs[sec_reg], SCRATCH2, SZ_D);
+					} else {
+						dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_D);
+					}
+				}
+			} else {
+				if (inst->dst.params.regs.sec & 0x10) {
+					if (opts->aregs[sec_reg] >= 0) {
+						dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_W, SZ_D);
+					} else {
+						dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_W, SZ_D);
+					}
+				} else {
+					if (opts->dregs[sec_reg] >= 0) {
+						dst = movsx_rr(dst, opts->dregs[sec_reg], SCRATCH1, SZ_W, SZ_D);
+					} else {
+						dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_W, SZ_D);
+					}
+				}
+				dst = add_rr(dst, SCRATCH1, SCRATCH2, SZ_D);
+			}
+			if (inst->dst.params.regs.displacement) {
+				dst = add_ir(dst, inst->dst.params.regs.displacement, SCRATCH2, SZ_D);
+			}
+			break;
 		case MODE_ABSOLUTE:
 			early_cycles += 4;
 		case MODE_ABSOLUTE_SHORT: