# HG changeset patch
# User Michael Pavone <pavone@retrodev.com>
# Date 1708758547 28800
# Node ID 679c317680130ca714570e4b71798a752eeb9141
# Parent  3b1b7b2723112ab04512078d191b9132be4be40f
Fix carry flag calculation for neg instruction in CPU DSL

diff -r 3b1b7b272311 -r 679c31768013 cpu_dsl.py
--- a/cpu_dsl.py	Fri Feb 23 23:08:45 2024 -0800
+++ b/cpu_dsl.py	Fri Feb 23 23:09:07 2024 -0800
@@ -395,6 +395,7 @@
 				if destSize > size:
 					needsSizeAdjust = True
 					prog.sizeAdjust = size
+			needsCarry = needsOflow = needsHalf = False
 			if op == '-':
 				if flagUpdates:
 					for flag in flagUpdates:
@@ -407,13 +408,15 @@
 							needsOflow = True
 				if needsCarry or needsOflow or needsHalf or (flagUpdates and needsSizeAdjust):
 					size = prog.paramSize(rawParams[1])
-					if needsCarry:
-						size *= 2
 					decl,name = prog.getTemp(size)
 					dst = prog.carryFlowDst = name
 					prog.lastA = 0
 					prog.lastB = params[0]
 					prog.lastBFlow = params[0]
+					if needsSizeAdjust:
+						return decl + '\n\t{dst} = {op}({a} & {mask});'.format(
+							dst = dst, a = params[0], op = op, mask = (1 << prog.sizeAdjust) - 1
+						)
 			if needsSizeAdjust:
 				return decl + '\n\t{dst} = ({dst} & ~{mask}) | (({op}{a}) & {mask});'.format(
 					dst = dst, a = params[0], op = op, mask = (1 << prog.sizeAdjust) - 1
@@ -498,6 +501,23 @@
 						#FIXME!!!!!
 						resultBit = 0
 					myRes = prog.lastA
+				elif prog.lastOp.op == 'neg':
+					if prog.carryFlowDst:
+						realSize = prog.getLastSize()
+						if realSize != prog.paramSize(prog.carryFlowDst):
+							lastDst = '({res} & {mask})'.format(res=lastDst, mask = (1 << realSize) - 1)
+					if type(storage) is tuple:
+						reg,storageBit = storage
+						reg = prog.resolveParam(reg, None, {})
+						output.append('\n\t{reg} = {res} ? ({reg} | {bit}U) : ({reg} & {mask}U);'.format(
+							reg = reg, mask = ~(1 << storageBit), res = lastDst, bit = 1 << storageBit
+						))
+					else:
+						reg = prog.resolveParam(storage, None, {})
+						output.append('\n\t{reg} = {res} != 0;'.format(
+							reg = reg, res = lastDst
+						))
+					continue
 				else:
 					resultBit = prog.getLastSize()
 					if prog.lastOp.op == 'ror':