# HG changeset patch
# User Mike Pavone <pavone@retrodev.com>
# Date 1379403769 25200
# Node ID 863e868752cfbca4ace5732c22d57ae2639a7c08
# Parent  2e4a4188cfb0384d95a48a73973ca1e61bd346ec
Implement funny behavior for DMA fill to CRAM and VSRAM. Return VSRAM address 0 for reads to VSRAM at >= 40

diff -r 2e4a4188cfb0 -r 863e868752cf vdp.c
--- a/vdp.c	Tue Sep 17 00:11:45 2013 -0700
+++ b/vdp.c	Tue Sep 17 00:42:49 2013 -0700
@@ -421,13 +421,13 @@
 			break;
 		case CRAM_WRITE: {
 			//printf("CRAM Write | %X to %X\n", start->value, (start->address/2) & (CRAM_SIZE-1));
-			write_cram(context, start->address, start->value);
+			write_cram(context, start->address, start->partial == 2 ? context->fifo[context->fifo_write].value : start->value);
 			break;
 		}
 		case VSRAM_WRITE:
 			if (((start->address/2) & 63) < VSRAM_SIZE) {
 				//printf("VSRAM Write: %X to %X\n", start->value, context->address);
-				context->vsram[(start->address/2) & 63] = start->value;
+				context->vsram[(start->address/2) & 63] = start->partial == 2 ? context->fifo[context->fifo_write].value : start->value;
 			}
 
 			break;
@@ -1597,12 +1597,15 @@
 		value = context->cram[(context->address/2) & (CRAM_SIZE-1)] & CRAM_BITS;
 		value |= context->fifo[context->fifo_write].value & ~CRAM_BITS;
 		break;
-	case VSRAM_READ:
-		if (((context->address / 2) & 63) < VSRAM_SIZE) {
-			value = context->vsram[(context->address / 2) & 63] & VSRAM_BITS;
-			value |= context->fifo[context->fifo_write].value & VSRAM_DIRTY_BITS;
+	case VSRAM_READ: {
+		uint16_t address = (context->address /2) & 63;
+		if (address >= VSRAM_SIZE) {
+			address = 0;
 		}
+		value = context->vsram[address] & VSRAM_BITS;
+		value |= context->fifo[context->fifo_write].value & VSRAM_DIRTY_BITS;
 		break;
+		}
 	}
 	context->address += context->regs[REG_AUTOINC];
 	return value;