# HG changeset patch
# User Mike Pavone <pavone@retrodev.com>
# Date 1367718713 25200
# Node ID 872a8911e0f4860f3e3f3d111f515ed0d503c1b7
# Parent  021aeb6df19bde16723287179f2b552740c9f6a9
Implemente RLD

diff -r 021aeb6df19b -r 872a8911e0f4 z80_to_x86.c
--- a/z80_to_x86.c	Sat May 04 16:23:28 2013 -0700
+++ b/z80_to_x86.c	Sat May 04 18:51:53 2013 -0700
@@ -1083,8 +1083,27 @@
 		} else {
 			dst = z80_save_reg(dst, inst, opts);
 		}
-	/*case Z80_RLD:
-	case Z80_RRD:*/
+	case Z80_RLD:
+		dst = zcycles(dst, 8);
+		dst = mov_rr(dst, opts->regs[Z80_HL], SCRATCH1, SZ_W);
+		dst = call(dst, (uint8_t *)z80_read_byte);
+		//Before: (HL) = 0x12, A = 0x34
+		//After: (HL) = 0x24, A = 0x31
+		dst = mov_rr(dst, opts->regs[Z80_A], SCRATCH2, SZ_B);
+		dst = shl_ir(dst, 4, SCRATCH1, SZ_W);
+		dst = and_ir(dst, 0xF, SCRATCH2, SZ_W);
+		dst = and_ir(dst, 0xFFF, SCRATCH1, SZ_W);
+		dst = and_ir(dst, 0xF0, opts->regs[Z80_A], SZ_B);
+		dst = or_rr(dst, SCRATCH2, SCRATCH1, SZ_W);
+		//SCRATCH1 = 0x0124
+		dst = ror_ir(dst, 8, SCRATCH1, SZ_W);
+		dst = zcycles(dst, 4);
+		dst = or_rr(dst, SCRATCH1, opts->regs[Z80_A], SZ_B);
+		dst = mov_rr(dst, opts->regs[Z80_HL], SCRATCH2, SZ_W);
+		dst = ror_ir(dst, 8, SCRATCH1, SZ_W);
+		dst = call(dst, (uint8_t *)z80_write_byte);
+		break;
+	//case Z80_RRD:*/
 	case Z80_BIT:
 		cycles = (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) ? 8 : 16;
 		dst = zcycles(dst, cycles);