# HG changeset patch
# User Michael Pavone <pavone@retrodev.com>
# Date 1708395252 28800
# Node ID 8b3daed1c076fba6f37ee4683ec5c353a189cf2d
# Parent  edd73a0095377c585a82b53b02f2eb09f2fbce7d
Allow more if statements to be constant folded in CPU DSL

diff -r edd73a009537 -r 8b3daed1c076 cpu_dsl.py
--- a/cpu_dsl.py	Mon Feb 19 17:55:45 2024 -0800
+++ b/cpu_dsl.py	Mon Feb 19 18:14:12 2024 -0800
@@ -1151,6 +1151,11 @@
 		'!=': _neqCImpl
 	}
 }
+_ifCmpEval = {
+	'>=U': lambda a, b: a >= b,
+	'=': lambda a, b: a == b,
+	'!=': lambda a, b: a != b
+}
 #represents a DSL conditional construct
 class If(ChildBlock):
 	def __init__(self, parent, cond):
@@ -1214,6 +1219,13 @@
 			self._genConstParam(prog.checkBool(self.cond), prog, fieldVals, output, otype)
 		else:
 			if self.cond in _ifCmpImpl[otype]:
+				if prog.lastOp.op == 'cmp':
+					params = [prog.resolveParam(p, parent, fieldVals) for p in prog.lastOp.params]
+					if type(params[0]) is int and type(params[1]) is int:
+						output.pop()
+						res = _ifCmpEval[self.cond](params[1], params[0])
+						self._genConstParam(res, prog, fieldVals, output, otype)
+						return
 				oldCond = prog.conditional
 				prog.conditional = True
 				#temp = prog.temp.copy()