# HG changeset patch
# User Michael Pavone <pavone@retrodev.com>
# Date 1549423794 28800
# Node ID 91aa789e57bdd98ff62c87a63a2a430aa5ff18cb
# Parent  a1663a83dcabe9c9aa994e8d62165c7929f74729
Fixed half-carry flag calcuation for adc/sbc in new Z80 core

diff -r a1663a83dcab -r 91aa789e57bd cpu_dsl.py
--- a/cpu_dsl.py	Tue Feb 05 19:29:30 2019 -0800
+++ b/cpu_dsl.py	Tue Feb 05 19:29:54 2019 -0800
@@ -545,7 +545,7 @@
 		decl,name = prog.getTemp(size)
 		dst = prog.carryFlowDst = name
 		prog.lastA = params[0]
-		prog.lastB = '({b} + ({check} ? 1 : 0))'.format(b = params[1], check = carryCheck)
+		prog.lastB = params[1]
 		prog.lastBFlow = '(~{b})'.format(b=params[1])
 	else:
 		dst = params[2]
@@ -573,7 +573,7 @@
 		decl,name = prog.getTemp(size)
 		dst = prog.carryFlowDst = name
 		prog.lastA = params[1]
-		prog.lastB = '({b} ^ ({check} ? 1 : 0))'.format(b = params[0], check = carryCheck)
+		prog.lastB = params[0]
 		prog.lastBFlow = params[0]
 	else:
 		dst = params[2]