# HG changeset patch # User Michael Pavone # Date 1548738927 28800 # Node ID 9ab64ef5cba04a8d17d30101c5bfab7075d64206 # Parent 89932fd29abd3d7494a895b2339d8126e89bbcfc Initial stab at overflow flag implementation in CPU DSL. Probably broken for subtraction diff -r 89932fd29abd -r 9ab64ef5cba0 cpu_dsl.py --- a/cpu_dsl.py Mon Jan 28 20:54:55 2019 -0800 +++ b/cpu_dsl.py Mon Jan 28 21:15:27 2019 -0800 @@ -304,7 +304,7 @@ else: lastDst = prog.resolveParam(prog.lastDst, None, {}) storage = prog.flags.getStorage(flag) - if calc == 'bit' or calc == 'sign' or calc == 'carry' or calc == 'half': + if calc == 'bit' or calc == 'sign' or calc == 'carry' or calc == 'half' or calc == 'overflow': myRes = lastDst if calc == 'sign': resultBit = prog.paramSize(prog.lastDst) - 1 @@ -313,6 +313,9 @@ elif calc == 'half': resultBit = 4 myRes = '({a} ^ {b} ^ {res})'.format(a = prog.lastA, b = prog.lastB, res = lastDst) + elif calc == 'overflow': + resultBit = prog.paramSize(prog.lastDst) - 1 + myRes = '((~({a} ^ {b})) & ({a} ^ {res}))'.format(a = prog.lastA, b = prog.lastB, res = lastDst) else: resultBit = int(resultBit) if type(storage) is tuple: @@ -347,9 +350,7 @@ reg = prog.resolveParam(storage, None, {}) output.append('\n\t{reg} = {res} == 0;'.format( reg = reg, res = lastDst - )) - elif calc == 'overflow': - pass + )) elif calc == 'parity': pass else: diff -r 89932fd29abd -r 9ab64ef5cba0 ztestrun.c --- a/ztestrun.c Mon Jan 28 20:54:55 2019 -0800 +++ b/ztestrun.c Mon Jan 28 21:15:27 2019 -0800 @@ -116,7 +116,7 @@ printf("Flags: SZYHXVNC\n" " %d%d%d%d%d%d%d%d\n", context->last_flag_result >> 7, context->zflag != 0, context->last_flag_result >> 5 & 1, context->chflags >> 3 & 1, - context->last_flag_result >> 3 & 1, context->pvflag != 0, context->nflag, context->chflags >> 7 & 1 + context->last_flag_result >> 3 & 1, context->pvflag != 0, context->nflag != 0, context->chflags >> 7 & 1 ); puts("--Alternate Regs--"); printf("A: %X\nB: %X\nC: %X\nD: %X\nE: %X\nHL: %X\n",