# HG changeset patch
# User Michael Pavone <pavone@retrodev.com>
# Date 1469855205 25200
# Node ID ac4615d16226b920ba71862f184851b2bd6ae9cd
# Parent  ca38a29d2d76a36ba726603245349c221483e429
Implement undocumented flag bits for shift instructions

diff -r ca38a29d2d76 -r ac4615d16226 z80_to_x86.c
--- a/z80_to_x86.c	Fri Jul 29 20:59:19 2016 -0700
+++ b/z80_to_x86.c	Fri Jul 29 22:06:45 2016 -0700
@@ -1673,8 +1673,11 @@
 		mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
 		mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_H), SZ_B);
 		if (dst_op.mode == MODE_REG_DIRECT) {
+			mov_rrdisp(code, dst_op.base, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
 			cmp_ir(code, 0, dst_op.base, SZ_B);
 		} else {
+			mov_rdispr(code, dst_op.base, dst_op.disp, opts->gen.scratch1, SZ_B);
+			mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
 			cmp_irdisp(code, 0, dst_op.base, dst_op.disp, SZ_B);
 		}
 		setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV));
@@ -1716,8 +1719,11 @@
 		mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
 		mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_H), SZ_B);
 		if (dst_op.mode == MODE_REG_DIRECT) {
+			mov_rrdisp(code, dst_op.base, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
 			cmp_ir(code, 0, dst_op.base, SZ_B);
 		} else {
+			mov_rdispr(code, dst_op.base, dst_op.disp, opts->gen.scratch1, SZ_B);
+			mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
 			cmp_irdisp(code, 0, dst_op.base, dst_op.disp, SZ_B);
 		}
 		setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV));
@@ -1759,8 +1765,11 @@
 		mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
 		mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_H), SZ_B);
 		if (dst_op.mode == MODE_REG_DIRECT) {
+			mov_rrdisp(code, dst_op.base, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
 			cmp_ir(code, 0, dst_op.base, SZ_B);
 		} else {
+			mov_rdispr(code, dst_op.base, dst_op.disp, opts->gen.scratch1, SZ_B);
+			mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
 			cmp_irdisp(code, 0, dst_op.base, dst_op.disp, SZ_B);
 		}
 		setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV));