# HG changeset patch
# User Michael Pavone <pavone@retrodev.com>
# Date 1549004631 28800
# Node ID ac809d044cab1daaf4a31a16c1f1e7cceeb3ab41
# Parent  0e5df2bc0f9f9b6f3ed65c70c6dce162dc43e796
Implemented the rest of the rotate instructions in new Z80 core

diff -r 0e5df2bc0f9f -r ac809d044cab cpu_dsl.py
--- a/cpu_dsl.py	Thu Jan 31 22:41:37 2019 -0800
+++ b/cpu_dsl.py	Thu Jan 31 23:03:51 2019 -0800
@@ -326,6 +326,8 @@
 				resultBit = prog.paramSize(prog.lastDst) - 1
 			elif calc == 'carry':
 				resultBit = prog.paramSize(prog.lastDst)
+				if prog.lastOp.op == 'ror':
+					resultBit -= 1
 			elif calc == 'half':
 				resultBit = prog.paramSize(prog.lastDst) - 4
 				myRes = '({a} ^ {b} ^ {res})'.format(a = prog.lastA, b = prog.lastB, res = lastDst)
@@ -578,20 +580,8 @@
 	)
 	
 def _rorCImpl(prog, params, rawParams, flagUpdates):
-	needsCarry = False
-	if flagUpdates:
-		for flag in flagUpdates:
-			calc = prog.flags.flagCalc[flag]
-			if calc == 'carry':
-				needsCarry = True
-	decl = ''
 	size = prog.paramSize(rawParams[2])
-	if needsCarry:
-		decl,name = prog.getTemp(size)
-		dst = prog.carryFlowDst = name
-	else:
-		dst = params[2]
-	return decl + '\n\t{dst} = {a} >> {b} | {a} << ({size} - {b});'.format(dst = dst,
+	return '\n\t{dst} = {a} >> {b} | {a} << ({size} - {b});'.format(dst = params[2],
 		a = params[0], b = params[1], size=size
 	)
 
diff -r 0e5df2bc0f9f -r ac809d044cab z80.cpu
--- a/z80.cpu	Thu Jan 31 22:41:37 2019 -0800
+++ b/z80.cpu	Thu Jan 31 23:03:51 2019 -0800
@@ -1404,8 +1404,8 @@
 	mov tmp scratch1
 	z80_store_hl
 	
-ddcb 00010110 rl_ixd
-	local tmp 8
+z80_rl_index
+	arg tmp 8
 	mov wz scratch1
 	ocall read_8
 	cycles 1
@@ -1415,13 +1415,93 @@
 	mov tmp scratch1
 	z80_store_index
 	
+ddcb 00010110 rl_ixd
+	local tmp 8
+	z80_rl_index tmp
+	
 fdcb 00010110 rl_iyd
 	local tmp 8
+	z80_rl_index tmp
+	
+	
+ddcb 00010RRR rl_ixd_reg
+	z80_rl_index main.R
+	
+fdcb 00010RRR rl_iyd_reg
+	z80_rl_index main.R
+	
+cb 00001RRR rrc
+	ror main.R 1 main.R
+	update_flags SZYH0PXN0C
+	
+cb 00001110 rrc_hl
+	local tmp 8
+	z80_fetch_hl
+	mov scratch1 tmp
+	ror tmp 1 tmp
+	update_flags SZYH0PXN0C
+	mov tmp scratch1
+	z80_store_hl
+	
+z80_rrc_index
+	arg tmp 8
 	mov wz scratch1
 	ocall read_8
 	cycles 1
 	mov scratch1 tmp
-	rlc tmp 1 tmp
+	ror tmp 1 tmp
 	update_flags SZYH0PXN0C
 	mov tmp scratch1
-	z80_store_index
\ No newline at end of file
+	z80_store_index
+	
+ddcb 00001110 rrc_ixd
+	local tmp 8
+	z80_rrc_index tmp
+	
+ddcb 00001RRR rrc_ixd_reg
+	z80_rrc_index main.R
+	
+fdcb 00001110 rrc_iyd
+	local tmp 8
+	z80_rrc_index tmp
+	
+fdcb 00001RRR rrc_iyd_reg
+	z80_rrc_index main.R
+	
+cb 00011RRR rr
+	rrc main.R 1 main.R
+	update_flags SZYH0PXN0C
+	
+cb 00011110 rr_hl
+	local tmp 8
+	z80_fetch_hl
+	mov scratch1 tmp
+	rrc tmp 1 tmp
+	update_flags SZYH0PXN0C
+	mov tmp scratch1
+	z80_store_hl
+	
+z80_rr_index
+	arg tmp 8
+	mov wz scratch1
+	ocall read_8
+	cycles 1
+	mov scratch1 tmp
+	rrc tmp 1 tmp
+	update_flags SZYH0PXN0C
+	mov tmp scratch1
+	z80_store_index
+	
+ddcb 00011110 rr_ixd
+	local tmp 8
+	z80_rr_index tmp
+	
+ddcb 00011RRR rr_ixd_reg
+	z80_rr_index main.R
+	
+fdcb 00011110 rr_iyd
+	local tmp 8
+	z80_rr_index tmp
+	
+fdcb 00011RRR rr_iyd_reg
+	z80_rr_index main.R
\ No newline at end of file