# HG changeset patch
# User Michael Pavone <pavone@retrodev.com>
# Date 1696576818 25200
# Node ID ae073c2167e2cc2c3a99ab4e37c9ba0f8034ab72
# Parent  49bd818ec9d841afcccd41276b89e309a4f840b2
Fix timing of sub CPU level 5 interrupt when main CPU is reading CDC data

diff -r 49bd818ec9d8 -r ae073c2167e2 segacd.c
--- a/segacd.c	Sun Oct 01 23:41:19 2023 -0700
+++ b/segacd.c	Fri Oct 06 00:20:18 2023 -0700
@@ -1270,7 +1270,10 @@
 		if (dst == DST_MAIN_CPU) {
 			if (cd->gate_array[GA_CDC_CTRL] & BIT_DSR) {
 				cd->gate_array[GA_CDC_CTRL] &= ~BIT_DSR;
-				lc8951_resume_transfer(&cd->cdc, scd_cycle);
+				//Using the sub CPU's cycle count here is a bit of a hack
+				//needed to ensure the interrupt does not get triggered prematurely
+				//because the sub CPU execution granularity is too high
+				lc8951_resume_transfer(&cd->cdc, cd->m68k->current_cycle);
 			} else {
 				printf("Read of CDC host data with DSR clear at %u\n", scd_cycle);
 			}