# HG changeset patch
# User Michael Pavone <pavone@retrodev.com>
# Date 1549150515 28800
# Node ID b0e01e64d76df19e021893ce75b8bb1f379d4a18
# Parent  9ea0b4cc8f0266f3f21c780d2bbf7e16d56b5748
Implemented RES instruction in new Z80 core

diff -r 9ea0b4cc8f02 -r b0e01e64d76d cpu_dsl.py
--- a/cpu_dsl.py	Sat Feb 02 15:10:18 2019 -0800
+++ b/cpu_dsl.py	Sat Feb 02 15:35:15 2019 -0800
@@ -745,6 +745,13 @@
 					output.append(_opMap['mov'].generate(otype, prog, shortProc, shortParams, None))
 			else:
 				output.append(opDef.generate(otype, prog, procParams, self.params, flagUpdates))
+				for dstIdx in opDef.outOp:
+					dst = self.params[dstIdx]
+					while dst in prog.meta:
+						dst = prog.meta[dst]
+					if dst in parent.regValues:
+						del parent.regValues[dst]
+					
 		elif self.op in prog.subroutines:
 			procParams = []
 			for param in self.params:
diff -r 9ea0b4cc8f02 -r b0e01e64d76d z80.cpu
--- a/z80.cpu	Sat Feb 02 15:10:18 2019 -0800
+++ b/z80.cpu	Sat Feb 02 15:35:15 2019 -0800
@@ -1750,4 +1750,45 @@
 	lsl 1 B tmp
 	lsr wz 8 last_flag_result
 	and scratch1 tmp tmp
-	update_flags SZH1PN0
\ No newline at end of file
+	update_flags SZH1PN0
+	
+cb 10BBBRRR res_reg
+	local tmp 8
+	lsl 1 B tmp
+	not tmp tmp
+	and main.R tmp main.R
+	
+cb 10BBB110 res_hl
+	z80_fetch_hl
+	cycles 1
+	local tmp 8
+	lsl 1 B tmp
+	not tmp tmp
+	and scratch1 tmp scratch1
+	z80_store_hl
+	
+z80_res_index
+	arg bit 8
+	arg tmp 8
+	lsl 1 bit tmp
+	not tmp tmp
+	mov wz scratch1
+	ocall read_8
+	cycles 1
+	and scratch1 tmp tmp
+	mov tmp scratch1
+	z80_store_index
+	
+ddcb 10BBB110 res_ixd
+	local tmp 8
+	z80_res_index B tmp
+	
+ddcb 10BBBRRR res_ixd_reg
+	z80_res_index B main.R
+	
+fdcb 10BBB110 res_iyd
+	local tmp 8
+	z80_res_index B tmp
+	
+fdcb 10BBBRRR res_iyd_reg
+	z80_res_index B main.R
\ No newline at end of file