# HG changeset patch
# User Mike Pavone <pavone@retrodev.com>
# Date 1357508533 28800
# Node ID c07713463c91e668db510b563ee9a333b3435371
# Parent  7b099f2b382b4166911f80c5d7375c58dbaea201
Fix a bunch of addressing modes in movem when a register list is the destination

diff -r 7b099f2b382b -r c07713463c91 m68k_to_x86.c
--- a/m68k_to_x86.c	Sun Jan 06 12:17:10 2013 -0800
+++ b/m68k_to_x86.c	Sun Jan 06 13:42:13 2013 -0800
@@ -1155,23 +1155,23 @@
 		case MODE_AREG_DISPLACE:
 			early_cycles += BUS;
 			reg = SCRATCH2;
-			if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
-				dst = mov_rr(dst, opts->aregs[inst->dst.params.regs.pri], SCRATCH1, SZ_D);
+			if (opts->aregs[inst->src.params.regs.pri] >= 0) {
+				dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D);
 			} else {
-				dst = mov_rdisp8r(dst, CONTEXT,  reg_offset(&(inst->dst)), SCRATCH1, SZ_D);
+				dst = mov_rdisp8r(dst, CONTEXT,  reg_offset(&(inst->src)), SCRATCH1, SZ_D);
 			}
-			dst = add_ir(dst, inst->dst.params.regs.displacement, SCRATCH1, SZ_D);
+			dst = add_ir(dst, inst->src.params.regs.displacement, SCRATCH1, SZ_D);
 			break;
 		case MODE_AREG_INDEX_DISP8:
 			early_cycles += 6;
-			if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
-				dst = mov_rr(dst, opts->aregs[inst->dst.params.regs.pri], SCRATCH1, SZ_D);
+			if (opts->aregs[inst->src.params.regs.pri] >= 0) {
+				dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D);
 			} else {
-				dst = mov_rdisp8r(dst, CONTEXT,  reg_offset(&(inst->dst)), SCRATCH1, SZ_D);
+				dst = mov_rdisp8r(dst, CONTEXT,  reg_offset(&(inst->src)), SCRATCH1, SZ_D);
 			}
-			sec_reg = (inst->dst.params.regs.sec >> 1) & 0x7;
-			if (inst->dst.params.regs.sec & 1) {
-				if (inst->dst.params.regs.sec & 0x10) {
+			sec_reg = (inst->src.params.regs.sec >> 1) & 0x7;
+			if (inst->src.params.regs.sec & 1) {
+				if (inst->src.params.regs.sec & 0x10) {
 					if (opts->aregs[sec_reg] >= 0) {
 						dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_D);
 					} else {
@@ -1185,7 +1185,7 @@
 					}
 				}
 			} else {
-				if (inst->dst.params.regs.sec & 0x10) {
+				if (inst->src.params.regs.sec & 0x10) {
 					if (opts->aregs[sec_reg] >= 0) {
 						dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D);
 					} else {
@@ -1200,20 +1200,20 @@
 				}
 				dst = add_rr(dst, SCRATCH2, SCRATCH1, SZ_D);
 			}
-			if (inst->dst.params.regs.displacement) {
-				dst = add_ir(dst, inst->dst.params.regs.displacement, SCRATCH1, SZ_D);
+			if (inst->src.params.regs.displacement) {
+				dst = add_ir(dst, inst->src.params.regs.displacement, SCRATCH1, SZ_D);
 			}
 			break;
 		case MODE_PC_DISPLACE:
 			early_cycles += BUS;
-			dst = mov_ir(dst, inst->dst.params.regs.displacement + inst->address+2, SCRATCH1, SZ_D);
+			dst = mov_ir(dst, inst->src.params.regs.displacement + inst->address+2, SCRATCH1, SZ_D);
 			break;
 		case MODE_PC_INDEX_DISP8:
 			early_cycles += 6;
 			dst = mov_ir(dst, inst->address+2, SCRATCH1, SZ_D);
-			sec_reg = (inst->dst.params.regs.sec >> 1) & 0x7;
-			if (inst->dst.params.regs.sec & 1) {
-				if (inst->dst.params.regs.sec & 0x10) {
+			sec_reg = (inst->src.params.regs.sec >> 1) & 0x7;
+			if (inst->src.params.regs.sec & 1) {
+				if (inst->src.params.regs.sec & 0x10) {
 					if (opts->aregs[sec_reg] >= 0) {
 						dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_D);
 					} else {
@@ -1227,7 +1227,7 @@
 					}
 				}
 			} else {
-				if (inst->dst.params.regs.sec & 0x10) {
+				if (inst->src.params.regs.sec & 0x10) {
 					if (opts->aregs[sec_reg] >= 0) {
 						dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D);
 					} else {
@@ -1242,8 +1242,8 @@
 				}
 				dst = add_rr(dst, SCRATCH2, SCRATCH1, SZ_D);
 			}
-			if (inst->dst.params.regs.displacement) {
-				dst = add_ir(dst, inst->dst.params.regs.displacement, SCRATCH1, SZ_D);
+			if (inst->src.params.regs.displacement) {
+				dst = add_ir(dst, inst->src.params.regs.displacement, SCRATCH1, SZ_D);
 			}
 			break;
 		case MODE_ABSOLUTE: