# HG changeset patch
# User Michael Pavone <pavone@retrodev.com>
# Date 1706248444 28800
# Node ID cde4ea2b4929e0ae3240a8bedd35e148fa2a0974
# Parent  794ba17f07166d15d5341c107bb0f19e16ed4d9f
Clear DSR in certain gate array writes. Fixes issue in Penn & Teller's Smoke and Mirrors

diff -r 794ba17f0716 -r cde4ea2b4929 segacd.c
--- a/segacd.c	Wed Jan 24 20:18:17 2024 -0800
+++ b/segacd.c	Thu Jan 25 21:54:04 2024 -0800
@@ -856,11 +856,18 @@
 		}
 		cd->gate_array[GA_CDC_DMA_ADDR] = 0;
 		cd->cdc_dst_low = 0;
+		//TODO: Confirm if DSR is cleared here on hardware
+		cd->gate_array[GA_CDC_CTRL] &= ~BIT_DSR;
 		break;
 	}
 	case GA_CDC_REG_DATA:
 		cdd_run(cd, m68k->current_cycle);
 		printf("CDC write %X: %X @ %u\n", cd->cdc.ar, value, m68k->current_cycle);
+		if (cd->cdc.ar == 6) {
+			cd->cdc_dst_low = 0;
+			//TODO: Confirm if DSR is cleared here on hardware
+			cd->gate_array[GA_CDC_CTRL] &= ~BIT_DSR;
+		}
 		lc8951_reg_write(&cd->cdc, value);
 		calculate_target_cycle(m68k);
 		break;
@@ -872,6 +879,8 @@
 		cdd_run(cd, m68k->current_cycle);
 		cd->gate_array[reg] = value;
 		cd->cdc_dst_low = 0;
+		//TODO: Confirm if DSR is cleared here on hardware
+		cd->gate_array[GA_CDC_CTRL] &= ~BIT_DSR;
 		break;
 	case GA_STOP_WATCH:
 		//docs say you should only write zero to reset