# HG changeset patch
# User Mike Pavone <pavone@retrodev.com>
# Date 1593405069 25200
# Node ID e08c489d5602ac5fdcfa2b7559a3b77c4dda95dc
# Parent  e35b00626b3e2a44e640e4f6fa70579c4ab718b7
Fix regressions from most recent address/cd latch change. Need to do more research still, but probably good enough for now

diff -r e35b00626b3e -r e08c489d5602 vdp.c
--- a/vdp.c	Thu Jun 18 00:28:53 2020 -0700
+++ b/vdp.c	Sun Jun 28 21:31:09 2020 -0700
@@ -3755,6 +3755,10 @@
 		if ((value & 0xC000) == 0x8000) {
 			//Register write
 			uint8_t reg = (value >> 8) & 0x1F;
+			// The fact that this is needed seems to pour some cold water on my theory
+			// about how the address latch actually works. Needs more search to definitively confirm
+			context->address = (context->address & 0x1C000) | (value & 0x3FFF);
+			context->cd = (context->cd & 0x3C) | (value >> 14);
 			if (reg < (mode_5 ? VDP_REGS : 0xB)) {
 				//printf("register %d set to %X\n", reg, value & 0xFF);
 				if (reg == REG_MODE_1 && (value & BIT_HVC_LATCH) && !(context->regs[reg] & BIT_HVC_LATCH)) {
@@ -3779,11 +3783,6 @@
 					update_video_params(context);
 				}
 			}
-			// The fact that this is needed seems to pour some cold water on my theory
-			// about how the address latch actually works. Needs more search to definitively confirm
-			clear_pending(context);
-			context->flags &= ~FLAG_READ_FETCHED;
-			context->flags2 &= ~FLAG2_READ_PENDING;
 		} else if (mode_5) {
 			context->flags |= FLAG_PENDING;
 			//Should these be taken care of here or after the second write?