# HG changeset patch
# User Michael Pavone <pavone@retrodev.com>
# Date 1432143303 25200
# Node ID eaba6789f3161a99ec75a57df84b965aef1851ed
# Parent  22dbdf50d33c9b6c70906e5e76beb04585550f8b
Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse.

diff -r 22dbdf50d33c -r eaba6789f316 blastem.c
--- a/blastem.c	Tue May 19 23:23:53 2015 -0700
+++ b/blastem.c	Wed May 20 10:35:03 2015 -0700
@@ -247,7 +247,7 @@
 	context->sync_cycle = gen->frame_end;
 	//printf("Set sync cycle to: %d @ %d, vcounter: %d, hslot: %d\n", context->sync_cycle, context->current_cycle, v_context->vcounter, v_context->hslot);
 	if (context->int_ack) {
-		printf("acknowledging %d @ %d:%d, vcounter: %d, hslot: %d\n", context->int_ack, context->current_cycle, v_context->cycles, v_context->vcounter, v_context->hslot);
+		//printf("acknowledging %d @ %d:%d, vcounter: %d, hslot: %d\n", context->int_ack, context->current_cycle, v_context->cycles, v_context->vcounter, v_context->hslot);
 		vdp_int_ack(v_context, context->int_ack);
 		context->int_ack = 0;
 	}
diff -r 22dbdf50d33c -r eaba6789f316 vdp.c
--- a/vdp.c	Tue May 19 23:23:53 2015 -0700
+++ b/vdp.c	Wed May 20 10:35:03 2015 -0700
@@ -487,7 +487,7 @@
 		}
 		case VSRAM_WRITE:
 			if (((start->address/2) & 63) < VSRAM_SIZE) {
-				//printf("VSRAM Write: %X to %X\n", start->value, context->address);
+				//printf("VSRAM Write: %X to %X @ vcounter: %d, hslot: %d, cycle: %d\n", start->value, context->address, context->vcounter, context->hslot, context->cycles);
 				context->vsram[(start->address/2) & 63] = start->partial == 2 ? context->fifo[context->fifo_write].value : start->value;
 			}
 
@@ -659,9 +659,24 @@
 		vscroll <<= 1;
 		vscroll |= 1;
 	}
-	//TODO: Further research on vscroll latch behavior and the "first column bug" seen in Gynoug
-	//this should be close, but won't match the exact behavior Eke-Eke has written about
-	if (column == 2 || (column && (context->regs[REG_MODE_3] & BIT_VSCROLL))) {
+	//TODO: Further research on vscroll latch behavior and the "first column bug"
+	if (!column) {
+		if (context->regs[REG_MODE_3] & BIT_VSCROLL) {
+			if (context->regs[REG_MODE_4] & BIT_H40) {
+				//Based on observed behavior documented by Eke-Eke, I'm guessing the VDP
+				//ends up fetching the last value on the VSRAM bus in the H40 case
+				//getting the last latched value should be close enough for now
+				if (!vsram_off) {
+					context->vscroll_latch[0] = context->vscroll_latch[1];
+				}
+			} else {
+				//supposedly it's always forced to 0 in the H32 case
+				context->vscroll_latch[0] = context->vscroll_latch[1] = 0;
+			}
+		} else {
+			context->vscroll_latch[vsram_off] = context->vsram[vsram_off];
+		}
+	} else if (context->regs[REG_MODE_3] & BIT_VSCROLL) {
 		context->vscroll_latch[vsram_off] = context->vsram[column - 2 + vsram_off];
 	}
 	vscroll &= context->vscroll_latch[vsram_off] + line;
@@ -1664,9 +1679,9 @@
 				if (reg == REG_BG_COLOR) {
 					value &= 0x3F;
 				}
-				if (reg == REG_MODE_4 && ((value ^ context->regs[reg]) & BIT_H40)) {
+				/*if (reg == REG_MODE_4 && ((value ^ context->regs[reg]) & BIT_H40)) {
 					printf("Mode changed from H%d to H%d @ %d, frame: %d\n", context->regs[reg] & BIT_H40 ? 40 : 32, value & BIT_H40 ? 40 : 32, context->cycles, context->frame);
-				}
+				}*/
 				context->regs[reg] = value;
 				if (reg == REG_MODE_4) {
 					context->double_res = (value & (BIT_INTERLACE | BIT_DOUBLE_RES)) == (BIT_INTERLACE | BIT_DOUBLE_RES);
@@ -1952,9 +1967,9 @@
 		}
 	} else {
 		if (context->vcounter < jump_start) {
-			lines = jump_start - context->vcounter + 512 - jump_dst + 1;
+			lines = jump_start - context->vcounter + 512 - jump_dst;
 		} else {
-			lines = 512 - context->vcounter + 1;
+			lines = 512 - context->vcounter;
 		}
 		if (target < jump_start) {
 			lines += target;