# HG changeset patch
# User Mike Pavone <pavone@retrodev.com>
# Date 1357381111 28800
# Node ID eba78ad49a11b66ff8f605307d35063271145af6
# Parent  6748022656b7e662afaeef98804314e5c3a57b7c
Implement more movem modes src

diff -r 6748022656b7 -r eba78ad49a11 m68k_to_x86.c
--- a/m68k_to_x86.c	Sat Jan 05 01:55:11 2013 -0800
+++ b/m68k_to_x86.c	Sat Jan 05 02:18:31 2013 -0800
@@ -1152,6 +1152,100 @@
 				dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D);
 			}
 			break;
+		case MODE_AREG_DISPLACE:
+			early_cycles += BUS;
+			reg = SCRATCH2;
+			if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
+				dst = mov_rr(dst, opts->aregs[inst->dst.params.regs.pri], SCRATCH1, SZ_D);
+			} else {
+				dst = mov_rdisp8r(dst, CONTEXT,  reg_offset(&(inst->dst)), SCRATCH1, SZ_D);
+			}
+			dst = add_ir(dst, inst->dst.params.regs.displacement, SCRATCH1, SZ_D);
+			break;
+		case MODE_AREG_INDEX_DISP8:
+			early_cycles += 6;
+			if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
+				dst = mov_rr(dst, opts->aregs[inst->dst.params.regs.pri], SCRATCH1, SZ_D);
+			} else {
+				dst = mov_rdisp8r(dst, CONTEXT,  reg_offset(&(inst->dst)), SCRATCH1, SZ_D);
+			}
+			sec_reg = (inst->dst.params.regs.sec >> 1) & 0x7;
+			if (inst->dst.params.regs.sec & 1) {
+				if (inst->dst.params.regs.sec & 0x10) {
+					if (opts->aregs[sec_reg] >= 0) {
+						dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_D);
+					} else {
+						dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D);
+					}
+				} else {
+					if (opts->dregs[sec_reg] >= 0) {
+						dst = add_rr(dst, opts->dregs[sec_reg], SCRATCH1, SZ_D);
+					} else {
+						dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D);
+					}
+				}
+			} else {
+				if (inst->dst.params.regs.sec & 0x10) {
+					if (opts->aregs[sec_reg] >= 0) {
+						dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D);
+					} else {
+						dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D);
+					}
+				} else {
+					if (opts->dregs[sec_reg] >= 0) {
+						dst = movsx_rr(dst, opts->dregs[sec_reg], SCRATCH2, SZ_W, SZ_D);
+					} else {
+						dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D);
+					}
+				}
+				dst = add_rr(dst, SCRATCH2, SCRATCH1, SZ_D);
+			}
+			if (inst->dst.params.regs.displacement) {
+				dst = add_ir(dst, inst->dst.params.regs.displacement, SCRATCH1, SZ_D);
+			}
+			break;
+		case MODE_PC_DISPLACE:
+			early_cycles += BUS;
+			dst = mov_ir(dst, inst->dst.params.regs.displacement + inst->address+2, SCRATCH1, SZ_D);
+			break;
+		case MODE_PC_INDEX_DISP8:
+			early_cycles += 6;
+			dst = mov_ir(dst, inst->address+2, SCRATCH1, SZ_D);
+			sec_reg = (inst->dst.params.regs.sec >> 1) & 0x7;
+			if (inst->dst.params.regs.sec & 1) {
+				if (inst->dst.params.regs.sec & 0x10) {
+					if (opts->aregs[sec_reg] >= 0) {
+						dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_D);
+					} else {
+						dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D);
+					}
+				} else {
+					if (opts->dregs[sec_reg] >= 0) {
+						dst = add_rr(dst, opts->dregs[sec_reg], SCRATCH1, SZ_D);
+					} else {
+						dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D);
+					}
+				}
+			} else {
+				if (inst->dst.params.regs.sec & 0x10) {
+					if (opts->aregs[sec_reg] >= 0) {
+						dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D);
+					} else {
+						dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D);
+					}
+				} else {
+					if (opts->dregs[sec_reg] >= 0) {
+						dst = movsx_rr(dst, opts->dregs[sec_reg], SCRATCH2, SZ_W, SZ_D);
+					} else {
+						dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D);
+					}
+				}
+				dst = add_rr(dst, SCRATCH2, SCRATCH1, SZ_D);
+			}
+			if (inst->dst.params.regs.displacement) {
+				dst = add_ir(dst, inst->dst.params.regs.displacement, SCRATCH1, SZ_D);
+			}
+			break;
 		case MODE_ABSOLUTE:
 			early_cycles += 4;
 		case MODE_ABSOLUTE_SHORT: