# HG changeset patch
# User Mike Pavone <pavone@retrodev.com>
# Date 1370061011 25200
# Node ID fc820ab1394b077827aff8be5e7e6d776b6d2be6
# Parent  c9d2a2371f5edeace64315f21352b066d9df5a85
Fix left/right enable default value

diff -r c9d2a2371f5e -r fc820ab1394b ym2612.c
--- a/ym2612.c	Fri May 31 20:47:34 2013 -0700
+++ b/ym2612.c	Fri May 31 21:30:11 2013 -0700
@@ -95,6 +95,10 @@
 		context->operators[i].envelope = MAX_ENVELOPE;
 		context->operators[i].env_phase = PHASE_RELEASE;
 	}
+	//some games seem to expect that the LR flags start out as 1
+	for (int i = 0; i < NUM_CHANNELS; i++) {
+		context->channels[i].lr = 0xC0;
+	}
 	if (!did_tbl_init) {
 		//populate sine table
 		for (int32_t i = 0; i < 512; i++) {
@@ -478,7 +482,7 @@
 		case REG_DAC:
 			if (context->dac_enable) {
 				context->channels[5].output = (((int16_t)value) - 0x80) << 6;
-				//printf("DAC Write %X(%d)\n", context->channels[5].output, context->channels[5].output);
+				//printf("DAC Write %X(%d)\n", value, context->channels[5].output);
 			}
 			break;
 		case REG_DAC_ENABLE:
@@ -567,13 +571,13 @@
 				context->channels[channel].pms = value & 0x7;
 				context->channels[channel].ams = value >> 4 & 0x3;
 				context->channels[channel].lr = value & 0xC0;
+				//printf("Write of %X to LR_AMS_PMS reg for channel %d\n", value, channel);
 				break;
 			}
 		}
 	}
 	
 	context->write_cycle = context->current_cycle;
-	context->selected_reg = 0;//TODO: Verify this
 }
 
 uint8_t ym_read_status(ym2612_context * context)