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comparison src/sim.tp @ 14:26cfb964fe81

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removed debug printing
author William Morgan <bill@mrgn.org>
date Sat, 14 Jul 2012 10:52:28 -0700
parents c92633098f1d
children 998ef2173f28 50a456168c25
comparison
equal deleted inserted replaced
13:c92633098f1d 14:26cfb964fe81
91 robot <- false 91 robot <- false
92 endreached <- false 92 endreached <- false
93 foreach: in_grid :index el{ 93 foreach: in_grid :index el{
94 nextGrid append: el 94 nextGrid append: el
95 if: (el isrobot) { 95 if: (el isrobot) {
96 print: "found robot\n"
97 robot <- el 96 robot <- el
98 } else: { true } 97 } else: { true }
99 } 98 }
100 #{ 99 #{
101 grid <- in_grid 100 grid <- in_grid
164 } 163 }
165 164
166 testMoves <- { 165 testMoves <- {
167 myStep <- 0 166 myStep <- 0
168 { 167 {
169 print: (string: myStep)
170 myStep <- myStep + 1 168 myStep <- myStep + 1
171 if: myStep > 5 {"A"} else: {"W"} 169 if: myStep > 5 {"A"} else: {"W"}
172 } 170 }
173 } 171 }
174 172
175 readFile <- :path { 173 readFile <- :path {
176 fd <- os open: path (os O_RDONLY) 174 fd <- os open: path (os O_RDONLY)
177 print: "fd: " . fd . "\n"
178 if: fd < 0 { "" } else: { 175 if: fd < 0 { "" } else: {
179 cur <- "" 176 cur <- ""
180 part <- "" 177 part <- ""
181 while: { 178 while: {
182 part <- os read: fd 128 179 part <- os read: fd 128
183 print: "read: " . part . "\n"
184 part != "" 180 part != ""
185 } do: { 181 } do: {
186 cur <- cur . part 182 cur <- cur . part
187 } 183 }
188 os close: fd 184 os close: fd
196 192
197 main <- :args { 193 main <- :args {
198 if: (args length) < 2 { 194 if: (args length) < 2 {
199 print: "usage: sim filename\n" 195 print: "usage: sim filename\n"
200 } else: { 196 } else: {
201 print: (args get: 1) . "\n"
202 text <- readFile: (args get: 1) 197 text <- readFile: (args get: 1)
198 print: text
203 simState <- state fromStr: text 199 simState <- state fromStr: text
204 while: { if: (simState ended) {false} else: {true} } do: { 200 while: { if: (simState ended) {false} else: {true} } do: {
205 print: "step...\n"
206 simState advance: (getMove: ) 201 simState advance: (getMove: )
207 } 202 }
208 } 203 }
209 } 204 }
210 205