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Updated the HTML documentation a bit
author Michael Pavone <pavone@retrodev.com>
date Tue, 30 Aug 2016 22:04:29 -0700
parents 5338b9affd09
children
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48:9a3b9d86dabf 49:5f30c4d18d79
8 </style> 8 </style>
9 </head> 9 </head>
10 <body> 10 <body>
11 <h1>Simple 16</h1> 11 <h1>Simple 16</h1>
12 <p> 12 <p>
13 Simple 16 is a toy 16-bit video game console designed with simplicity of implementation in mind. While it is technically a 16-bit system, 13 Simple 16 is a toy 16-bit video game console designed with simplicity of implementation in mind. The hope is that
14 it's capabilites are in many ways closer to an 8-bit system. Ultimately, the hope is that Simple 16 is simple enough to provide an easy 14 Simple 16 is simple enough to provide an easy introduction for the novice emudev while still containing all the
15 introduction for the novice emudev while still containing all the essential features of an older game console. 15 essential features of an older game console and providing sufficient capabilities to support compelling games.
16 16
17 </p> 17 </p>
18 <h2>Table of Contents</h2> 18 <h2>Table of Contents</h2>
19 <ul> 19 <ul>
20 <li><a href="#cpu">CPU</a> 20 <li><a href="#cpu">CPU</a>
46 </ul> 46 </ul>
47 <h2 id="cpu">CPU</h2> 47 <h2 id="cpu">CPU</h2>
48 <h3 id="cpuover">Overview</h3> 48 <h3 id="cpuover">Overview</h3>
49 <p> 49 <p>
50 The Simple 16 CPU is a 16-bit RISC design. It has a main register file of 16 16-bit registers. Additionally, there are five special 50 The Simple 16 CPU is a 16-bit RISC design. It has a main register file of 16 16-bit registers. Additionally, there are five special
51 purpose registers dedicated to exception processing. It has a flag 16-bit addres space. Instructions are a fixed size and are also 16-bits. 51 purpose registers dedicated to exception processing and an additional special register for holding the upper bits of the program counter.
52 It has a 23-bit addres space addressable with 16-bit offsets. Instructions are a fixed size and are also 16-bits.
52 </p> 53 </p>
53 <h3 id="cpuregs">Registers</h3> 54 <h3 id="cpuregs">Registers</h3>
54 <p> 55 <p>
55 The first 14 registers in the main file have no fixed function and are named r0 through r13. r14 serves as the program counter and 56 The first 12 registers in the main file have no fixed function and are named r0 through r11. r12 holds the upper 8-bits of the
56 points to the next instruction to be fetched. More information about instruction fetch and execution can be found in 57 upper and lower data segments and is also named db. r13 holds the stack pointer and is also named sp. r14 serves as the program
58 counter and points to the next instruction to be fetched. More information about instruction fetch and execution can be found in
57 <a href="#execution">Execution Details</a>. r15 serves as the status register. The status register contains bits corresponding 59 <a href="#execution">Execution Details</a>. r15 serves as the status register. The status register contains bits corresponding
58 to the result of the last arithmetic instruction and the interrupt mask. The layout of the status register is given below. 60 to the result of the last arithmetic instruction and the interrupt mask. It also contains the uppper 7-bits of the stack segment.
61 The layout of the status register is given below.
59 </p> 62 </p>
60 <table> 63 <table>
61 <tr> 64 <tr>
62 <th>Bit</th> 65 <th>Bit</th>
63 <th>Use</th> 66 <th>Use</th>
64 <th>Notes</th> 67 <th>Notes</th>
65 <tr> 68 <tr>
66 <td>15-5</td> 69 <td>15</td>
67 <td>Unused</td> 70 <td>Unused</td>
68 <td>Should be set to zero.</td> 71 <td>Should be set to zero.</td>
72 </tr>
73 <tr>
74 <td>14-8</td>
75 <td>Stack Segment</td>
76 <td>Bits 8-14 of the 23-bit address for stack-relative load and stores</td>
69 </tr> 77 </tr>
70 <tr> 78 <tr>
71 <td>4</td> 79 <td>4</td>
72 <td>Negative Flag</td> 80 <td>Negative Flag</td>
73 <td>Indicates the last result was negative.</td> 81 <td>Indicates the last result was negative.</td>
126 <li><a href="#lsli">lsli IM, rD</a></li> 134 <li><a href="#lsli">lsli IM, rD</a></li>
127 <li><a href="#lsri">lsri IM, rD</a></li> 135 <li><a href="#lsri">lsri IM, rD</a></li>
128 <li><a href="#cmpi">cmpi IM, rD</a></li> 136 <li><a href="#cmpi">cmpi IM, rD</a></li>
129 <li><a href="#reti">reti rD</a></li> 137 <li><a href="#reti">reti rD</a></li>
130 <li><a href="#trapi">trapi IM</a></li> 138 <li><a href="#trapi">trapi IM</a></li>
139 <li><a href="#push">push rD</a></li>
140 <li><a href="#pop">pop rD</a></li>
141 <li><a href="#getepc">getpch rD</a></li>
142 <li><a href="#setepc">setpch rD</a></li>
131 <li><a href="#getepc">getepc rD</a></li> 143 <li><a href="#getepc">getepc rD</a></li>
132 <li><a href="#setepc">setepc rD</a></li> 144 <li><a href="#setepc">setepc rD</a></li>
133 <li><a href="#getesr">getesr rD</a></li> 145 <li><a href="#getesr">getesr rD</a></li>
134 <li><a href="#setesr">setser rD</a></li> 146 <li><a href="#setesr">setser rD</a></li>
135 <li><a href="#geteur">geteur rD</a></li> 147 <li><a href="#geteur">geteur rD</a></li>
785 exception or interrupt. 797 exception or interrupt.
786 </p> 798 </p>
787 <p> 799 <p>
788 <strong>Flags:</strong> Updated corresponding to the value in ESR. 800 <strong>Flags:</strong> Updated corresponding to the value in ESR.
789 </p> 801 </p>
790 <h4 id="trap">trap rD</h4>
791 <p>
792 Causes an exception to be taken to the vector indicated by rD.
793 </p>
794 <p>
795 <strong>Flags:</strong> Condition code flags unchanged, interrupt enable bits cleared.
796 </p>
797 <h4 id="trapi">trapi IM</h4> 802 <h4 id="trapi">trapi IM</h4>
798 <p> 803 <p>
799 Causes an exception to be taken to the vector indicated by IM 804 Causes an exception to be taken to the vector indicated by IM
800 </p> 805 </p>
801 <p> 806 <h4 id="push">push rD</h4>
802 <strong>Flags:</strong> Condition code flags unchanged, interrupt enable bits cleared. 807 <p>
808 Pushes the value in register rD onto the stack.
809 </p>
810 <p>
811 <strong>Flags:</strong> Condition code flags unchanged.
812 </p>
813 <hr id="pop">pop rD</h4>
814 <p>
815 Pops a value of the stack and stores it in rD
816 </p>
817 <p>
818 <strong>Flags:</strong> Condition code flags unchanged.
803 </p> 819 </p>
804 <h4 id="getepc">getepc rD</h4> 820 <h4 id="getepc">getepc rD</h4>
805 <p> 821 <p>
806 Stores the value of EPC in rD. 822 Stores the value of EPC in rD.
807 </p> 823 </p>
872 <strong>Flags:</strong> No change 888 <strong>Flags:</strong> No change
873 </p> 889 </p>
874 <h2 id="video">Video</h2> 890 <h2 id="video">Video</h2>
875 <h3 id="vidover">Overview</h3> 891 <h3 id="vidover">Overview</h3>
876 <p> 892 <p>
877 Simple 16 features a tile-based video processor using 8x8 pixel tiles. It supports a single background plane with a fixed width of 64 tiles and configurable height. 893 Simple 16 features a simple linear framebuffer using indexed color. There is 128KB of VRAM arranged as two 64KB framebuffers. At any given time one buffer is used for
878 64 sprites can be displayed simultaneously and 20 can be displayed on each line. Each sprite can either be 8x8 or 16x16 pixels and can use either of the first two 894 display and the other is accessible to the CPU. Both 4bpp and 8bpp depths are available. The resolution of the display is fixed at 320x240, but up to 31 lines can be
879 16 color palettes. The background plane can make use of all 4 palettes. 895 blanked at the top and bottom of the display to save on VRAM usage or to implement a letterbox effect.
880 </p> 896 </p>
881 <h2 id="audio">Audio</h2> 897 <h2 id="audio">Audio</h2>
882 <h3 id="audover">Overview</h3> 898 <h3 id="audover">Overview</h3>
883 <p> 899 <p>
884 Simple 16 has four square-wave tone generators with a 16-bit period and an 8-bit volume. The special value of 0 for the period causes the volume to be output constantly 900 Simple 16 has four square-wave tone generators with a 16-bit period and an 8-bit volume. The special value of 0 for the period causes the volume to be output constantly