Mercurial > repos > simple16
comparison src/cpu.c @ 2:6204c81e2933
Revert changes to handling of immediate versions of bitwise instructions. Replace asri with cmpi.
author | Michael Pavone <pavone@retrodev.com> |
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date | Wed, 23 Mar 2016 19:19:29 -0700 |
parents | 7e44f7d5810b |
children | 74a6d629b78f |
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1:a44e078d792b | 2:6204c81e2933 |
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214 context->regs[REG_PC] += sign_extend(a << 4 | b) * 2; | 214 context->regs[REG_PC] += sign_extend(a << 4 | b) * 2; |
215 context->state = STATE_NEED_FETCH; | 215 context->state = STATE_NEED_FETCH; |
216 } | 216 } |
217 } | 217 } |
218 | 218 |
219 uint16_t format_immediate_bitwise(uint16_t val) | 219 uint16_t format_immediate(uint16_t val) |
220 { | 220 { |
221 if (val & 8) { | 221 if (val & 8) { |
222 val |= 0xFFF0; | 222 val |= 0xFFF0; |
223 } | 223 } |
224 return val; | |
225 } | |
226 | |
227 uint16_t format_immediate(uint16_t val) | |
228 { | |
229 val = format_immediate_bitwise(val); | |
230 if (!val) { | 224 if (!val) { |
231 val = 8; | 225 val = 8; |
232 } | 226 } |
233 return val; | 227 return val; |
234 } | 228 } |
337 tmp = context->regs[dst] + format_immediate(a); | 331 tmp = context->regs[dst] + format_immediate(a); |
338 context->regs[dst] = tmp; | 332 context->regs[dst] = tmp; |
339 update_flags_arith(context, tmp); | 333 update_flags_arith(context, tmp); |
340 break; | 334 break; |
341 case ANDI: | 335 case ANDI: |
342 context->regs[dst] = context->regs[dst] & format_immediate_bitwise(a); | 336 context->regs[dst] = context->regs[dst] & format_immediate(a); |
343 update_flags_bitwise(context, context->regs[dst]); | 337 update_flags_bitwise(context, context->regs[dst]); |
344 break; | 338 break; |
345 case ORI: | 339 case ORI: |
346 context->regs[dst] = context->regs[dst] | format_immediate_bitwise(a); | 340 context->regs[dst] = context->regs[dst] | format_immediate(a); |
347 update_flags_bitwise(context, context->regs[dst]); | 341 update_flags_bitwise(context, context->regs[dst]); |
348 break; | 342 break; |
349 case LSI: | 343 case LSI: |
350 shift = a & 7; | 344 shift = a & 7; |
351 if (!shift) { | 345 if (!shift) { |
358 tmp = context->regs[dst] << (a & 7); | 352 tmp = context->regs[dst] << (a & 7); |
359 } | 353 } |
360 context->regs[dst] = tmp; | 354 context->regs[dst] = tmp; |
361 update_flags_arith(context, tmp); | 355 update_flags_arith(context, tmp); |
362 break; | 356 break; |
363 case ASRI: | 357 case CMPI: |
364 shift = a; | 358 tmp = a; |
365 if (!shift) { | 359 if (a & 8) { |
366 shift = 16; | 360 a |= 0xFFF0; |
367 } | 361 } |
368 tmp = context->regs[dst]; | 362 tmp = context->regs[dst] - a; |
369 if (tmp & 0x8000) { | |
370 tmp |= 0xFFFF0000; | |
371 } | |
372 tmp = tmp >> shift & 0xFFFF; | |
373 tmp |= (context->regs[dst] >> (context->regs[shift] - 1)) << 16 & 0x10000; | |
374 context->regs[dst] = tmp; | |
375 update_flags_arith(context, tmp); | 363 update_flags_arith(context, tmp); |
376 break; | 364 break; |
377 case SINGLE_REG: | 365 case SINGLE_REG: |
378 run_single_reg(context, dst, a); | 366 run_single_reg(context, dst, a); |
379 return; | 367 return; |