annotate modules/il.tp @ 203:56b2100d9fff

Add code for converting IL into x86 machine code
author Mike Pavone <pavone@retrodev.com>
date Wed, 28 Aug 2013 01:05:45 -0700
parents 49bca6487178
children 2308336790d4
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
rev   line source
185
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1 {
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2 //commutative ops
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
3 _add <- 0
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
4 _and <- 1
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
5 _or <- 2
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
6 _xor <- 3
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
7 //non-commutative ops
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
8 _sub <- 4
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
9 _cmp <- 5
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
10 _not <- 6
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
11 _sl <- 7
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
12 _asr <- 8
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
13 _lsr <- 9
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
14 _rol <- 10
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
15 _ror <- 11
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
16 _mov <- 12
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
17 _call <- 13
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
18 _ret <- 14
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
19 _skipif <- 15
195
7856f0916549 Add save il instruction to save callee saved registers in function prolog
Mike Pavone <pavone@retrodev.com>
parents: 194
diff changeset
20 _save <- 16
185
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
21
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
22 _names <- #[
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
23 "add"
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
24 "and"
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
25 "or"
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
26 "xor"
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
27 "sub"
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
28 "cmp"
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
29 "not"
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
30 "sl"
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
31 "asr"
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
32 "lsr"
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
33 "rol"
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
34 "ror"
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
35 "mov"
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
36 "call"
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
37 "ret"
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
38 "skipIf"
195
7856f0916549 Add save il instruction to save callee saved registers in function prolog
Mike Pavone <pavone@retrodev.com>
parents: 194
diff changeset
39 "save"
185
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
40 ]
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
41
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
42 op3:a:b:out:size <- :_opcode :_ina :_inb :_out :_size {
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
43 #{
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
44 opcode <- { _opcode }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
45 ina <- { _ina }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
46 inb <- { _inb }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
47 commutative? <- { _opcode < _sub }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
48 out <- { _out }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
49 size <- { _size }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
50 numops <- { 3 }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
51 name <- { _names get: _opcode }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
52 string <- { name . " " . (string: _ina) . " " . (string: _inb) . " " . (string: _out) . " " . (string: _size) }
189
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
53 recordUsage:at <- :tracker :address {
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
54 if: (not: (_ina isInteger?)) {
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
55 _ina recordUsage: tracker at: 0 | address withSize: _size
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
56 }
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
57 _inb recordUsage: tracker at: 0 | address withSize: _size
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
58 _out recordUsage: tracker at: 1 | address withSize: _size
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
59 }
200
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions.
Mike Pavone <pavone@retrodev.com>
parents: 195
diff changeset
60 assignRegs:at:withSource:andUsage <- :assignments :at :regSrc :usage {
194
30bed95cbb18 Apply register assignments in il module
Mike Pavone <pavone@retrodev.com>
parents: 193
diff changeset
61 newa <- if: (not: (_ina isInteger?)) {
30bed95cbb18 Apply register assignments in il module
Mike Pavone <pavone@retrodev.com>
parents: 193
diff changeset
62 _ina assign: assignments withSource: regSrc
30bed95cbb18 Apply register assignments in il module
Mike Pavone <pavone@retrodev.com>
parents: 193
diff changeset
63 } else: { _ina }
30bed95cbb18 Apply register assignments in il module
Mike Pavone <pavone@retrodev.com>
parents: 193
diff changeset
64 newb <- _inb assign: assignments withSource: regSrc
30bed95cbb18 Apply register assignments in il module
Mike Pavone <pavone@retrodev.com>
parents: 193
diff changeset
65 newout <- _out assign: assignments withSource: regSrc
30bed95cbb18 Apply register assignments in il module
Mike Pavone <pavone@retrodev.com>
parents: 193
diff changeset
66 op3: _opcode a: newa b: newb out: newout size: _size
30bed95cbb18 Apply register assignments in il module
Mike Pavone <pavone@retrodev.com>
parents: 193
diff changeset
67 }
185
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
68 }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
69 }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
70 op2:in:out:size <- :_opcode :_in :_out :_size {
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
71 #{
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
72 opcode <- { _opcode }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
73 in <- { _in }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
74 out <- { _out }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
75 size <- { _size }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
76 numops <- { 2 }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
77 name <- { _names get: _opcode }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
78 string <- { name . " " . (string: _in) . " " . (string: _out) . " " . (string: _size) }
189
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
79 recordUsage:at <- :tracker :address {
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
80 if: (not: (_in isInteger?)) {
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
81 _in recordUsage: tracker at: 0 | address withSize: _size
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
82 }
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
83 _out recordUsage: tracker at: 1 | address withSize: _size
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
84 }
200
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions.
Mike Pavone <pavone@retrodev.com>
parents: 195
diff changeset
85 assignRegs:at:withSource:andUsage <- :assignments :at :regSrc :usage {
194
30bed95cbb18 Apply register assignments in il module
Mike Pavone <pavone@retrodev.com>
parents: 193
diff changeset
86 newin <- if: (not: (_in isInteger?)) {
30bed95cbb18 Apply register assignments in il module
Mike Pavone <pavone@retrodev.com>
parents: 193
diff changeset
87 _in assign: assignments withSource: regSrc
30bed95cbb18 Apply register assignments in il module
Mike Pavone <pavone@retrodev.com>
parents: 193
diff changeset
88 } else: { _in }
30bed95cbb18 Apply register assignments in il module
Mike Pavone <pavone@retrodev.com>
parents: 193
diff changeset
89 newout <- _out assign: assignments withSource: regSrc
30bed95cbb18 Apply register assignments in il module
Mike Pavone <pavone@retrodev.com>
parents: 193
diff changeset
90 op2: _opcode in: newin out: newout size: _size
30bed95cbb18 Apply register assignments in il module
Mike Pavone <pavone@retrodev.com>
parents: 193
diff changeset
91 }
185
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
92 }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
93 }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
94 op1:arg:size <- :_opcode :_arg :_size {
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
95 #{
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
96 opcode <- { _opcode }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
97 arg <- { _arg }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
98 size <- { _size }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
99 numops <- { 1 }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
100 name <- { _names get: _opcode }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
101 string <- { name . " " . (string: _arg) . " " . (string: _size) }
189
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
102 recordUsage:at <- :tracker :address {
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
103 if: (not: (_arg isInteger?)) {
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
104 _arg recordUsage: tracker at: address withSize: _size
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
105 }
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
106 }
200
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions.
Mike Pavone <pavone@retrodev.com>
parents: 195
diff changeset
107 assignRegs:at:withSource:andUsage <- :assignments :at :regSrc :usage {
194
30bed95cbb18 Apply register assignments in il module
Mike Pavone <pavone@retrodev.com>
parents: 193
diff changeset
108 newarg <- if: (not: (_arg isInteger?)) {
30bed95cbb18 Apply register assignments in il module
Mike Pavone <pavone@retrodev.com>
parents: 193
diff changeset
109 _arg assign: assignments withSource: regSrc
30bed95cbb18 Apply register assignments in il module
Mike Pavone <pavone@retrodev.com>
parents: 193
diff changeset
110 } else: { _arg }
30bed95cbb18 Apply register assignments in il module
Mike Pavone <pavone@retrodev.com>
parents: 193
diff changeset
111 op1: _opcode arg: newarg size: _size
30bed95cbb18 Apply register assignments in il module
Mike Pavone <pavone@retrodev.com>
parents: 193
diff changeset
112 }
185
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
113 }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
114 }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
115
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
116 _sizenames <- #["b" "w" "l" "q"]
193
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
117 _size <- :_bytes {
185
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
118 #{
193
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
119 bytes <- { _bytes }
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
120 string <- {
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
121 idx <- if: _bytes = 8 { 3 } else: { _bytes / 2}
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
122 _sizenames get: idx
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
123 }
185
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
124 = <- :other {
193
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
125 _bytes = (other bytes)
185
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
126 }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
127 <= <- :other {
193
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
128 _bytes <= (other bytes)
185
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
129 }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
130 >= <- :other {
193
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
131 _bytes >= (other bytes)
185
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
132 }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
133 > <- :other {
193
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
134 _bytes > (other bytes)
185
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
135 }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
136 < <- :other {
193
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
137 _bytes < (other bytes)
185
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
138 }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
139 }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
140 }
193
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
141 byte <- _size: 1
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
142 word <- _size: 2
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
143 long <- _size: 4
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
144 quad <- _size: 8
185
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
145
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
146 _retr <- #{
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
147 isInteger? <- { false }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
148 register? <- { true }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
149 argument? <- { false }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
150 return? <- { true }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
151 string <- { "retr" }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
152 = <- :other {
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
153 (not: (other isInteger?)) && (other register?) && (other return?)
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
154 }
189
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
155 != <- :other {
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
156 not: self = other
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
157 }
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
158 recordUsage:at:withSize <- :tracker :address :size {
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
159 //TODO: Figure out what tracking is necessary here
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
160 }
194
30bed95cbb18 Apply register assignments in il module
Mike Pavone <pavone@retrodev.com>
parents: 193
diff changeset
161 assign:withSource <- :assignments :regSrc {
30bed95cbb18 Apply register assignments in il module
Mike Pavone <pavone@retrodev.com>
parents: 193
diff changeset
162 regSrc allocRet
30bed95cbb18 Apply register assignments in il module
Mike Pavone <pavone@retrodev.com>
parents: 193
diff changeset
163 }
185
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
164 }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
165
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
166 _condnames <- #[
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
167 "eq"
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
168 "neq"
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
169 "ge"
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
170 "le"
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
171 "gr"
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
172 "ls"
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
173 "uge"
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
174 "ule"
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
175 "ugr"
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
176 "uls"
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
177 ]
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
178 condition <- :num {
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
179 #{
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
180 cc <- { num }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
181 string <- { _condnames get: num }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
182 = <- :other { num = (other cc) }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
183 }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
184 }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
185 _eq <- condition: 0
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
186 _neq <- condition: 1
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
187 _ge <- condition: 2
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
188 _le <- condition: 3
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
189 _gr <- condition: 4
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
190 _ls <- condition: 5
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
191 _uge <- condition: 6
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
192 _ule <- condition: 7
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
193 _ugr <- condition: 8
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
194 _uls <- condition: 9
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
195
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
196 #{
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
197 b <- { byte }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
198 w <- { word }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
199 l <- { long }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
200 q <- { quad }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
201
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
202 eq <- { _eq }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
203 neq <- { _neq }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
204
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
205 //signed conditions
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
206 ge <- { _ge }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
207 le <- { _le }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
208 gr <- { _gr }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
209 ls <- { _ls }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
210
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
211 //unsigned conditions
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
212 uge <- { _uge }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
213 ule <- { _ule }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
214 ugr <- { _ugr }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
215 uls <- { _uls }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
216
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
217
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
218 reg <- :num {
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
219 #{
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
220 isInteger? <- { false }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
221 register? <- { true }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
222 argument? <- { false }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
223 return? <- { false }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
224 regnum <- { num }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
225 string <- { "r" . (string: num) }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
226 = <- :other {
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
227 (not: (other isInteger?)) && (other register?) && (not: (other argument?)) && (not: (other return?)) && num = (other regnum)
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
228 }
189
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
229 != <- :other {
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
230 not: self = other
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
231 }
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
232 recordUsage:at:withSize <- :tracker :address :size {
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
233 tracker reg: self usedAt: address withSize: size
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
234 }
194
30bed95cbb18 Apply register assignments in il module
Mike Pavone <pavone@retrodev.com>
parents: 193
diff changeset
235 assign:withSource <- :assignments :regSrc {
30bed95cbb18 Apply register assignments in il module
Mike Pavone <pavone@retrodev.com>
parents: 193
diff changeset
236 assignments get: self
30bed95cbb18 Apply register assignments in il module
Mike Pavone <pavone@retrodev.com>
parents: 193
diff changeset
237 }
185
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
238 }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
239 }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
240 arg <- :num {
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
241 #{
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
242 isInteger? <- { false }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
243 register? <- { true }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
244 argument? <- { true }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
245 return? <- { false }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
246 argnum <- { num }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
247 string <- { "a" . (string: num) }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
248 = <- :other {
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
249 (not: (other isInteger?)) && (other register?) && (other argument?) && num = (other regnum)
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
250 }
189
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
251 != <- :other {
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
252 not: self = other
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
253 }
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
254 recordUsage:at:withSize <- :tracker :address :size {
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
255 tracker arg: self usedAt: address withSize: size
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
256 }
194
30bed95cbb18 Apply register assignments in il module
Mike Pavone <pavone@retrodev.com>
parents: 193
diff changeset
257 assign:withSource <- :assignments :regSrc {
30bed95cbb18 Apply register assignments in il module
Mike Pavone <pavone@retrodev.com>
parents: 193
diff changeset
258 regSrc allocArg: num
30bed95cbb18 Apply register assignments in il module
Mike Pavone <pavone@retrodev.com>
parents: 193
diff changeset
259 }
185
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
260 }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
261 }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
262 retr <- { _retr }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
263
189
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
264 base:offset <- :_base :_offset {
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
265 #{
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
266 base <- { _base }
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
267 offset <- { _offset }
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
268 string <- {
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
269 start <- if: _offset = 0 { "" } else: { (string: _offset) }
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
270 start . "[" . (string: _base) . "]"
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
271 }
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
272 recordUsage:at:withSize <- :tracker :address :size {
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
273 _base recordUsage: tracker at: address withSize: size
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
274 }
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
275 }
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
276 }
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
277
185
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
278 add <- :ina inb out size {
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
279 op3: _add a: ina b: inb out: out size: size
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
280 }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
281
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
282 sub <- :ina inb out size {
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
283 op3: _sub a: ina b: inb out: out size: size
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
284 }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
285
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
286 cmp <- :ina inb out size {
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
287 op3: _cmp a: ina b: inb out: out size: size
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
288 }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
289
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
290 and <- :ina inb out size {
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
291 op3: _and a: ina b: inb out: out size: size
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
292 }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
293
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
294 or <- :ina inb out size {
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
295 op3: _or a: ina b: inb out: out size: size
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
296 }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
297
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
298 xor <- :ina inb out size {
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
299 op3: _xor a: ina b: inb out: out size: size
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
300 }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
301
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
302 bnot <- :in out size {
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
303 op2: _not in: in out: out size: size
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
304 }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
305
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
306 sl <- :shift in out size {
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
307 op3: _sl a: shift b: in out: out size: size
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
308 }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
309
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
310 asr <- :shift in out size {
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
311 op3: _asr a: shift b: in out: out size: size
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
312 }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
313
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
314 lsr <- :shift in out size {
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
315 op3: _lsr a: shift b: in out: out size: size
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
316 }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
317
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
318 rol <- :rot in out size {
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
319 op3: _rol a: rot b: in out: out size: size
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
320 }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
321
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
322 ror <- :rot in out size {
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
323 op3: _ror a: rot b: in out: out size: size
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
324 }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
325
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
326 mov <- :in out size {
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
327 op2: _mov in: in out: out size: size
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
328 }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
329
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
330 call:withArgs <- :_target :_args {
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
331 #{
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
332 opcode <- { _call }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
333 target <- { _target }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
334 args <- { _args }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
335 numops <- { 0 }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
336 name <- { _names get: _call }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
337 string <- {
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
338 argstr <- _args map: :el {
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
339 string: el
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
340 }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
341 name . " " . (string: _target) . " " . (argstr join: " ")
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
342 }
189
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
343 recordUsage:at <- :tracker :address {
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
344 if: (not: (_target isString?)) {
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
345 //TODO: use size l for 32-bit targets or an abstract pointer size
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
346 _target recordUsage: tracker at: address withSize: q
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
347 }
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
348 foreach: _args :_ arg {
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
349 //TODO: have some mechanism for properly expressing sizes of arguments
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
350 arg recordUsage: tracker at: address withSize: q
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
351 }
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
352 }
200
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions.
Mike Pavone <pavone@retrodev.com>
parents: 195
diff changeset
353 assignRegs:at:withSource:andUsage <- :assignments :address :regSrc :usage {
194
30bed95cbb18 Apply register assignments in il module
Mike Pavone <pavone@retrodev.com>
parents: 193
diff changeset
354 newtarget <- if: (_target isString?) { _target } else: {
30bed95cbb18 Apply register assignments in il module
Mike Pavone <pavone@retrodev.com>
parents: 193
diff changeset
355 _target assign: assignments withSource: regSrc
30bed95cbb18 Apply register assignments in il module
Mike Pavone <pavone@retrodev.com>
parents: 193
diff changeset
356 }
30bed95cbb18 Apply register assignments in il module
Mike Pavone <pavone@retrodev.com>
parents: 193
diff changeset
357 newargs <- _args map: :arg {
30bed95cbb18 Apply register assignments in il module
Mike Pavone <pavone@retrodev.com>
parents: 193
diff changeset
358 if: (arg isInteger?) { arg } else: {
30bed95cbb18 Apply register assignments in il module
Mike Pavone <pavone@retrodev.com>
parents: 193
diff changeset
359 arg assign: assignments withSource: regSrc
30bed95cbb18 Apply register assignments in il module
Mike Pavone <pavone@retrodev.com>
parents: 193
diff changeset
360 }
30bed95cbb18 Apply register assignments in il module
Mike Pavone <pavone@retrodev.com>
parents: 193
diff changeset
361 }
200
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions.
Mike Pavone <pavone@retrodev.com>
parents: 195
diff changeset
362 newcall <- call: newtarget withArgs: newargs
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions.
Mike Pavone <pavone@retrodev.com>
parents: 195
diff changeset
363 regSrc returnAll
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions.
Mike Pavone <pavone@retrodev.com>
parents: 195
diff changeset
364 raddress <- address reverse
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions.
Mike Pavone <pavone@retrodev.com>
parents: 195
diff changeset
365 foreach: (usage liveArgsAt: raddress) :_ arg {
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions.
Mike Pavone <pavone@retrodev.com>
parents: 195
diff changeset
366 regSrc allocArg: (arg num)
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions.
Mike Pavone <pavone@retrodev.com>
parents: 195
diff changeset
367 }
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions.
Mike Pavone <pavone@retrodev.com>
parents: 195
diff changeset
368 foreach: (usage liveRegsAt: raddress) :_ reg {
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions.
Mike Pavone <pavone@retrodev.com>
parents: 195
diff changeset
369 regSrc allocSpecific: (assignments get: reg)
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions.
Mike Pavone <pavone@retrodev.com>
parents: 195
diff changeset
370 }
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions.
Mike Pavone <pavone@retrodev.com>
parents: 195
diff changeset
371 tosave <- regSrc needSaveForCall
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions.
Mike Pavone <pavone@retrodev.com>
parents: 195
diff changeset
372 if: (tosave length) > 0 {
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions.
Mike Pavone <pavone@retrodev.com>
parents: 195
diff changeset
373 save: tosave #[newcall]
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions.
Mike Pavone <pavone@retrodev.com>
parents: 195
diff changeset
374 } else: {
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions.
Mike Pavone <pavone@retrodev.com>
parents: 195
diff changeset
375 newcall
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions.
Mike Pavone <pavone@retrodev.com>
parents: 195
diff changeset
376 }
194
30bed95cbb18 Apply register assignments in il module
Mike Pavone <pavone@retrodev.com>
parents: 193
diff changeset
377 }
185
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
378 }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
379 }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
380
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
381 return <- :val size {
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
382 op1: _ret arg: val size: size
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
383 }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
384 skipIf <- :_cond _toskip {
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
385 #{
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
386 opcode <- { _skipif }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
387 toskip <- { _toskip }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
388 cond <- { _cond }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
389 numops <- { 0 }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
390 name <- { _names get: _skipif }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
391 string <- {
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
392 block <- (_toskip map: :el { string: el }) join: "\n\t"
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
393 if: (_toskip length) > 0 {
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
394 block <- "\n\t" . block . "\n"
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
395 }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
396 name . " " . (string: _cond) . " {" . block . "}"
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
397 }
189
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
398 recordUsage:at <- :tracker :address {
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
399 foreach: _toskip :idx inst {
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
400 inst recordUsage: tracker at: idx | address
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
401 }
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
402 }
200
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions.
Mike Pavone <pavone@retrodev.com>
parents: 195
diff changeset
403 assignRegs:at:withSource:andUsage <- :assignments :address :regSrc :usage {
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions.
Mike Pavone <pavone@retrodev.com>
parents: 195
diff changeset
404 newskip <- #[]
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions.
Mike Pavone <pavone@retrodev.com>
parents: 195
diff changeset
405 foreach: _toskip :idx inst {
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions.
Mike Pavone <pavone@retrodev.com>
parents: 195
diff changeset
406 newskip append: (inst assignRegs: assignments at: idx | address withSource: regSrc andUsage: usage)
194
30bed95cbb18 Apply register assignments in il module
Mike Pavone <pavone@retrodev.com>
parents: 193
diff changeset
407 }
30bed95cbb18 Apply register assignments in il module
Mike Pavone <pavone@retrodev.com>
parents: 193
diff changeset
408 skipIf: _cond newskip
30bed95cbb18 Apply register assignments in il module
Mike Pavone <pavone@retrodev.com>
parents: 193
diff changeset
409 }
200
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions.
Mike Pavone <pavone@retrodev.com>
parents: 195
diff changeset
410 to2OpInst <- {
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions.
Mike Pavone <pavone@retrodev.com>
parents: 195
diff changeset
411 skipIf: _cond (to2Op: _toskip)
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions.
Mike Pavone <pavone@retrodev.com>
parents: 195
diff changeset
412 }
185
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
413 }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
414 }
203
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 200
diff changeset
415 save <- :regs :_scope{
195
7856f0916549 Add save il instruction to save callee saved registers in function prolog
Mike Pavone <pavone@retrodev.com>
parents: 194
diff changeset
416 #{
7856f0916549 Add save il instruction to save callee saved registers in function prolog
Mike Pavone <pavone@retrodev.com>
parents: 194
diff changeset
417 opcode <- { _save }
7856f0916549 Add save il instruction to save callee saved registers in function prolog
Mike Pavone <pavone@retrodev.com>
parents: 194
diff changeset
418 numops <- { 0 }
7856f0916549 Add save il instruction to save callee saved registers in function prolog
Mike Pavone <pavone@retrodev.com>
parents: 194
diff changeset
419 name <- { _names get: _save }
203
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 200
diff changeset
420 tosave <- { regs }
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 200
diff changeset
421 scope <- { _scope }
195
7856f0916549 Add save il instruction to save callee saved registers in function prolog
Mike Pavone <pavone@retrodev.com>
parents: 194
diff changeset
422 string <- {
203
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 200
diff changeset
423 block <- _scope join: "\n\t"
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 200
diff changeset
424 if: (_scope length) > 0 {
195
7856f0916549 Add save il instruction to save callee saved registers in function prolog
Mike Pavone <pavone@retrodev.com>
parents: 194
diff changeset
425 block <- "\n\t" . block . "\n"
7856f0916549 Add save il instruction to save callee saved registers in function prolog
Mike Pavone <pavone@retrodev.com>
parents: 194
diff changeset
426 }
7856f0916549 Add save il instruction to save callee saved registers in function prolog
Mike Pavone <pavone@retrodev.com>
parents: 194
diff changeset
427 name . " " . (regs join: " ") . " {" . block . "}"
7856f0916549 Add save il instruction to save callee saved registers in function prolog
Mike Pavone <pavone@retrodev.com>
parents: 194
diff changeset
428 }
200
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions.
Mike Pavone <pavone@retrodev.com>
parents: 195
diff changeset
429 to2OpInst <- {
203
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 200
diff changeset
430 save: regs (to2Op: _scope)
200
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions.
Mike Pavone <pavone@retrodev.com>
parents: 195
diff changeset
431 }
195
7856f0916549 Add save il instruction to save callee saved registers in function prolog
Mike Pavone <pavone@retrodev.com>
parents: 194
diff changeset
432 }
7856f0916549 Add save il instruction to save callee saved registers in function prolog
Mike Pavone <pavone@retrodev.com>
parents: 194
diff changeset
433 }
185
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
434
189
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
435 allocRegs:withSource <- :instarr:regSrc {
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
436 _regMap <- dict linear
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
437 _argMap <- dict linear
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
438
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
439 _usageTracker <- :_firstUsage {
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
440 #{
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
441 firstUsage <- _firstUsage
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
442 lastUsage <- _firstUsage
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
443 useCount <- 0
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
444 maxSize <- byte
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
445 usedAt:withSize <- :address :size {
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
446 useCount <- useCount + 1
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
447 lastUsage <- address
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
448 if: size > maxSize {
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
449 maxSize <- size
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
450 }
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
451 }
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
452 string <- {
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
453 "Uses: " . useCount . ", FirstUse: " . (firstUsage join: ":") . ", Last Use: " . (lastUsage join: ":") . ", Max Size: " . maxSize
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
454 }
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
455 }
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
456 }
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
457
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
458 _maxUses <- 0
200
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions.
Mike Pavone <pavone@retrodev.com>
parents: 195
diff changeset
459 liveFrom:to <- :regs :from :to {
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions.
Mike Pavone <pavone@retrodev.com>
parents: 195
diff changeset
460 live <- #[]
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions.
Mike Pavone <pavone@retrodev.com>
parents: 195
diff changeset
461 foreach: regs :reg usage {
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions.
Mike Pavone <pavone@retrodev.com>
parents: 195
diff changeset
462 if: ((usage lastUsage) addrGreatEq: from) && ((usage firstUsage) addrLessEq: to) {
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions.
Mike Pavone <pavone@retrodev.com>
parents: 195
diff changeset
463 live append: reg
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions.
Mike Pavone <pavone@retrodev.com>
parents: 195
diff changeset
464 }
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions.
Mike Pavone <pavone@retrodev.com>
parents: 195
diff changeset
465 }
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions.
Mike Pavone <pavone@retrodev.com>
parents: 195
diff changeset
466 live
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions.
Mike Pavone <pavone@retrodev.com>
parents: 195
diff changeset
467 }
189
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
468 regUsage <- #{
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
469 reg:usedAt:withSize <- :reg :address :size {
193
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
470 raddress <- address reverse
189
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
471 usage <- _regMap get: reg elseSet: {
193
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
472 _usageTracker: raddress
189
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
473 }
193
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
474 usage usedAt: raddress withSize: size
189
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
475 if: (usage useCount) > _maxUses {
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
476 _maxUses <- usage useCount
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
477 }
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
478 }
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
479 arg:usedAt:withSize <- :arg :address :size {
193
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
480 raddress <- address reverse
189
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
481 usage <- _argMap get: arg elseSet: {
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
482 _usageTracker: [0 0]
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
483 }
193
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
484 usage usedAt: raddress withSize: size
189
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
485 }
200
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions.
Mike Pavone <pavone@retrodev.com>
parents: 195
diff changeset
486
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions.
Mike Pavone <pavone@retrodev.com>
parents: 195
diff changeset
487 liveRegsAt <- :address {
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions.
Mike Pavone <pavone@retrodev.com>
parents: 195
diff changeset
488 _regMap liveFrom: address to: address
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions.
Mike Pavone <pavone@retrodev.com>
parents: 195
diff changeset
489 }
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions.
Mike Pavone <pavone@retrodev.com>
parents: 195
diff changeset
490 liveArgsAt <- :address {
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions.
Mike Pavone <pavone@retrodev.com>
parents: 195
diff changeset
491 _argMap liveFrom: address to: address
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions.
Mike Pavone <pavone@retrodev.com>
parents: 195
diff changeset
492 }
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions.
Mike Pavone <pavone@retrodev.com>
parents: 195
diff changeset
493
189
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
494 print <- {
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
495 foreach: _regMap :reg usage {
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
496 print: (string: reg) . " | " . (string: usage) . "\n"
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
497 }
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
498 foreach: _argMap :arg usage {
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
499 print: (string: arg) . " | " . (string: usage) . "\n"
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
500 }
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
501 }
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
502 }
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
503 foreach: instarr :idx inst {
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
504 inst recordUsage: regUsage at: [idx]
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
505 }
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
506 print: regUsage
193
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
507
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
508 addrLessEq <- :left :right {
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
509 lesseq <- true
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
510 while: { lesseq && (not: (left empty?)) && (not: (right empty?)) } do: {
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
511 if: (left value) > (right value) {
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
512 lesseq <- false
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
513 } else: {
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
514 if: (left value) < (right value) {
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
515 left <- []
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
516 } else: {
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
517 left <- left tail
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
518 right <- right tail
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
519 }
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
520 }
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
521 }
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
522 lesseq
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
523 }
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
524
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
525 addrGreatEq <- :left :right {
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
526 greateq <- true
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
527 while: { greateq && (not: (left empty?)) && (not: (right empty?)) } do: {
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
528 if: (left value) < (right value) {
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
529 greateq <- false
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
530 } else: {
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
531 if: (left value) > (right value) {
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
532 left <- []
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
533 } else: {
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
534 left <- left tail
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
535 right <- right tail
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
536 }
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
537 }
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
538 }
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
539 greateq
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
540 }
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
541
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
542 _assignments <- dict linear
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
543 curuses <- _maxUses
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
544 while: { curuses > 0 && (_assignments length) < (_regMap length) } do: {
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
545 foreach: _regMap :reg usage {
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
546 if: (usage useCount) = curuses {
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
547 liveArgs <- _argMap liveFrom: (usage firstUsage) to: (usage lastUsage)
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
548 foreach: liveArgs :_ arg {
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
549 regSrc allocArg: (arg num)
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
550 }
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
551
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
552 liveRegs <- _regMap liveFrom: (usage firstUsage) to: (usage lastUsage)
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
553 print: (string: reg) . " | Live: " . (liveRegs join: ", ") . ", Live Args: " . (liveArgs join: ", ") . "\n"
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
554 foreach: liveRegs :_ reg {
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
555 if: (_assignments contains?: reg) {
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
556 regSrc allocSpecific: (_assignments get: reg)
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
557 }
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
558 }
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
559 _assignments set: reg (regSrc alloc: (usage maxSize))
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
560
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
561 regSrc returnAll
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
562 }
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
563 }
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
564 curuses <- curuses - 1
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
565 }
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
566 print: "\n\nAssignments:\n\n"
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
567 foreach: _assignments :reg assign {
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
568 print: (string: reg) . " = " . assign . "\n"
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
569 }
194
30bed95cbb18 Apply register assignments in il module
Mike Pavone <pavone@retrodev.com>
parents: 193
diff changeset
570
200
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions.
Mike Pavone <pavone@retrodev.com>
parents: 195
diff changeset
571 withassign <- #[]
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions.
Mike Pavone <pavone@retrodev.com>
parents: 195
diff changeset
572 foreach: instarr :idx inst {
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions.
Mike Pavone <pavone@retrodev.com>
parents: 195
diff changeset
573 withassign append: (inst assignRegs: _assignments at: [idx] withSource: regSrc andUsage: regUsage)
194
30bed95cbb18 Apply register assignments in il module
Mike Pavone <pavone@retrodev.com>
parents: 193
diff changeset
574 }
195
7856f0916549 Add save il instruction to save callee saved registers in function prolog
Mike Pavone <pavone@retrodev.com>
parents: 194
diff changeset
575 psave <- regSrc needSaveProlog
7856f0916549 Add save il instruction to save callee saved registers in function prolog
Mike Pavone <pavone@retrodev.com>
parents: 194
diff changeset
576 if: (psave length) > 0 {
7856f0916549 Add save il instruction to save callee saved registers in function prolog
Mike Pavone <pavone@retrodev.com>
parents: 194
diff changeset
577 withassign <- #[save: psave withassign]
7856f0916549 Add save il instruction to save callee saved registers in function prolog
Mike Pavone <pavone@retrodev.com>
parents: 194
diff changeset
578 }
7856f0916549 Add save il instruction to save callee saved registers in function prolog
Mike Pavone <pavone@retrodev.com>
parents: 194
diff changeset
579 withassign
189
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
580 }
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
581
185
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
582 //used to convert IL to a format suitable for a 2-operand architecture
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
583 //should be run after register allocation (I think....)
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
584 to2Op <- :instarr {
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
585 instarr fold: #[] with: :newarr inst {
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
586 if: (inst numops) = 3 {
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
587 if: (inst inb) = (inst out) {
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
588 newarr append: (op2: (inst opcode) in: (inst ina) out: (inst out) size: (inst size))
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
589 } else: {
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
590 if: (inst commutative?) && (inst ina) = (inst out) {
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
591 newarr append: (op2: (inst opcode) in: (inst inb) out: (inst out) size: (inst size))
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
592 } else: {
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
593 newarr append: (mov: (inst inb) (inst out) (inst size))
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
594 newarr append: (op2: (inst opcode) in: (inst ina) out: (inst out) size: (inst size))
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
595 }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
596 }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
597 } else: {
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
598 if: (inst numops) = 2 && (inst opcode) != _mov {
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
599 if: (inst in) != (inst out) {
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
600 newarr append: (mov: (inst in) (inst out) (inst size))
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
601 }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
602 newarr append: (op1: (inst opcode) val: (inst out) size: (inst size))
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
603 } else: {
200
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions.
Mike Pavone <pavone@retrodev.com>
parents: 195
diff changeset
604 if: (inst opcode) = _skipif || (inst opcode) = _save {
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions.
Mike Pavone <pavone@retrodev.com>
parents: 195
diff changeset
605 newarr append: (inst to2OpInst)
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions.
Mike Pavone <pavone@retrodev.com>
parents: 195
diff changeset
606 } else: {
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions.
Mike Pavone <pavone@retrodev.com>
parents: 195
diff changeset
607 newarr append: inst
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions.
Mike Pavone <pavone@retrodev.com>
parents: 195
diff changeset
608 }
185
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
609 }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
610 }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
611 }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
612 }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
613
203
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 200
diff changeset
614 toBackend <- :program :backend {
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 200
diff changeset
615 prepped <- program map: :fun {
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 200
diff changeset
616 backend adjustIL: fun
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 200
diff changeset
617 }
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 200
diff changeset
618 labels <- prepped map: :_ {
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 200
diff changeset
619 backend label
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 200
diff changeset
620 }
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 200
diff changeset
621 outprog <- #[]
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 200
diff changeset
622 foreach: prepped :name instarr {
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 200
diff changeset
623 outprog append: (labels get: name)
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 200
diff changeset
624 foreach: instarr :_ inst {
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 200
diff changeset
625 backend convertIL: inst to: outprog withLabels: labels
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 200
diff changeset
626 }
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 200
diff changeset
627 }
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 200
diff changeset
628 outprog
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 200
diff changeset
629 }
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 200
diff changeset
630
185
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
631 main <- {
203
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 200
diff changeset
632 prog <- dict linear
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 200
diff changeset
633
185
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
634 fib <- #[
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
635 sub: 2 (arg: 0) (reg: 0) q
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
636 skipIf: ge #[
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
637 return: 1 q
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
638 ]
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
639 call: "fib" withArgs: #[reg: 0]
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
640 mov: retr (reg: 1) q
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
641 add: 1 (reg: 0) (reg: 2) q
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
642 call: "fib" withArgs: #[reg: 2]
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
643 add: retr (reg: 1) (reg: 3) q
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
644 return: (reg: 3) q
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
645 ]
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
646 print: "Original:\n\n"
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
647 foreach: fib :idx inst {
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
648 print: (string: inst) . "\n"
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
649 }
203
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 200
diff changeset
650 prog set: "fib" fib
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 200
diff changeset
651
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 200
diff changeset
652 mprog <- prog toBackend: x86
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 200
diff changeset
653 ba <- bytearray executableFromBytes: mprog
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 200
diff changeset
654 res <- ba runWithArg: 30u64
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 200
diff changeset
655 print: (string: res) . "\n"
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 200
diff changeset
656 0
185
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
657 }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
658 }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
659 }