Mercurial > repos > tabletprog

annotate modules/x86.tp @ 177:76e3d4ae1746

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
Support more bitwise operations and function pointers in llMessages
author Mike Pavone <pavone@retrodev.com>
date Sat, 24 Aug 2013 09:54:47 -0700
parents 20b6041a8b23
children 75aca5f87969
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
rev   line source
174
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1 {
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2 ireg <- :regnum {
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
3 #{
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
4 num <- { regnum }
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
5 reg <- { regnum and 7u8}
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
6 rm <- :tail { reg or 0xC0u8 | tail }
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
7 validforSize? <- :size { true }
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
8 isInteger? <- { false }
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
9 register? <- { true }
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
10 upper? <- { true }
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
11 needsRex? <- { regnum >= 8u8 }
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
12 rexBitReg <- {
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
13 if: needsRex? {
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
14 4u8
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
15 } else: {
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
16 0u8
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
17 }
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
18 }
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
19 rexBitRM <- {
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
20 if: needsRex? {
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
21 1u8
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
22 } else: {
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
23 0u8
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
24 }
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
25 }
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
26 = <- :other {
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
27 (not: (other isInteger?)) && (other register?) && (not: (other upper?)) && regnum = (other num)
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
28 }
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
29 }
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
30 }
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
31
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
32 upper <- :regnum {
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
33 #{
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
34 num <- { regnum }
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
35 reg <- { regnum }
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
36 rm <- :tail { regnum or 0xC0u8 | tail }
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
37 validforSize? <- :size {
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
38 size = byte
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
39 }
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
40 isInteger? <- { false }
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
41 register? <- { true }
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
42 upper? <- { true }
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
43 needsRex? <- { false }
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
44 = <- :other {
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
45 (not: (other isInteger?)) && (other register?) && (other upper?) && regnum = (other num)
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
46 }
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
47 }
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
48 }
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
49 fakesrc <- #{
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
50 needsRex? <- { false }
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
51 rexBitReg <- { 0u8 }
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
52 rexBitRM <- { 0u8 }
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
53 }
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
54 size <- :s {
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
55 #{
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
56 num <- { s }
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
57 = <- :other {
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
58 s = (other num)
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
59 }
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
60 > <- :other {
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
61 s > (other num)
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
62 }
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
63 >= <- :other {
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
64 s >= (other num)
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
65 }
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
66 < <- :other {
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
67 s < (other num)
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
68 }
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
69 <= <- :other {
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
70 s <= (other num)
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
71 }
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
72 needsRex? <- { s = 3 }
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
73 rexBit <- {
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
74 if: needsRex? {
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
75 0x08u8
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
76 } else: {
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
77 0u8
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
78 }
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
79 }
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
80 }
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
81 }
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
82 byte <- size: 0
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
83 word <- size: 1
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
84 dword <- size: 2
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
85 qword <- size: 3
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
86
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
87 size_bit <- :opcode size {
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
88 if: size = byte {
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
89 opcode
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
90 } else: {
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
91 opcode or 2u8
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
92 }
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
93 }
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
94 opex <- :val {
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
95 #{
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
96 reg <- { val }
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
97 }
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
98 }
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
99
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
100 mod_rm:withTail <- :register regmem :end {
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
101 l <- regmem rm: end
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
102 (l value) or (register reg) | (l tail)
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
103 }
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
104
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
105 mod_rm <- :reg rm {
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
106 mod_rm: reg rm withTail: []
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
107 }
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
108
175
20b6041a8b23 Small refactor in x86 module. Added a few more instructions.
Mike Pavone <pavone@retrodev.com>
parents: 174
diff changeset
109 int_op:withTail <- :value size :tail {
174
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
110 if: size >= dword {
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
111 tail <- (uint8: (value rshift: 16)) | (uint8: (value rshift: 24)) | tail
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
112 }
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
113 if: size >= word {
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
114 tail <- (uint8: (value rshift: 8)) | tail
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
115 }
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
116 (uint8: value) | tail
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
117 }
175
20b6041a8b23 Small refactor in x86 module. Added a few more instructions.
Mike Pavone <pavone@retrodev.com>
parents: 174
diff changeset
118 int_op <- :value size {
20b6041a8b23 Small refactor in x86 module. Added a few more instructions.
Mike Pavone <pavone@retrodev.com>
parents: 174
diff changeset
119 int_op: value size withTail: []
20b6041a8b23 Small refactor in x86 module. Added a few more instructions.
Mike Pavone <pavone@retrodev.com>
parents: 174
diff changeset
120 }
20b6041a8b23 Small refactor in x86 module. Added a few more instructions.
Mike Pavone <pavone@retrodev.com>
parents: 174
diff changeset
121 //used for mov instructions that support 64-bit immediate operands/offsets
20b6041a8b23 Small refactor in x86 module. Added a few more instructions.
Mike Pavone <pavone@retrodev.com>
parents: 174
diff changeset
122 int_op64 <- :value size {
20b6041a8b23 Small refactor in x86 module. Added a few more instructions.
Mike Pavone <pavone@retrodev.com>
parents: 174
diff changeset
123 tail <- []
20b6041a8b23 Small refactor in x86 module. Added a few more instructions.
Mike Pavone <pavone@retrodev.com>
parents: 174
diff changeset
124 if: size = qword {
20b6041a8b23 Small refactor in x86 module. Added a few more instructions.
Mike Pavone <pavone@retrodev.com>
parents: 174
diff changeset
125 tail <- (uint8: (value rshift: 32)) | (uint8: (value rshift: 40)) | (uint8: (value rshift: 48)) | (uint8: (value rshift: 56)) | tail
20b6041a8b23 Small refactor in x86 module. Added a few more instructions.
Mike Pavone <pavone@retrodev.com>
parents: 174
diff changeset
126 }
20b6041a8b23 Small refactor in x86 module. Added a few more instructions.
Mike Pavone <pavone@retrodev.com>
parents: 174
diff changeset
127 int_op: value size withTail: tail
20b6041a8b23 Small refactor in x86 module. Added a few more instructions.
Mike Pavone <pavone@retrodev.com>
parents: 174
diff changeset
128 }
174
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
129
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
130 prefix:withInstruction <- :reg rm size :inst {
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
131 if: size = word {
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
132 inst <- 0x66u8 | inst
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
133 }
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
134 if: (size needsRex?) || (reg needsRex?) || (rm needsRex?) {
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
135 rex <- 0x40u8 or (size rexBit) or (reg rexBitReg) or (rm rexBitRM)
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
136 inst <- rex | inst
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
137 }
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
138 inst
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
139 }
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
140
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
141 _rax <- ireg: 0u8
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
142 _rcx <- ireg: 1u8
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
143 _rdx <- ireg: 2u8
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
144 _rbx <- ireg: 3u8
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
145 _rsp <- ireg: 4u8
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
146 _rbp <- ireg: 5u8
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
147 _rsi <- ireg: 6u8
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
148 _rdi <- ireg: 7u8
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
149 _r8 <- ireg: 8u8
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
150 _r9 <- ireg: 9u8
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
151 _r10 <- ireg: 10u8
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
152 _r11 <- ireg: 11u8
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
153 _r12 <- ireg: 12u8
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
154 _r13 <- ireg: 13u8
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
155 _r14 <- ireg: 14u8
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
156 _r15 <- ireg: 15u8
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
157 _ah <- upper: 4u8
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
158 _ch <- upper: 5u8
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
159 _dh <- upper: 6u8
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
160 _bh <- upper: 7u8
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
161
175
20b6041a8b23 Small refactor in x86 module. Added a few more instructions.
Mike Pavone <pavone@retrodev.com>
parents: 174
diff changeset
162 op:withCode:withImmed:withOpEx <- :src dst size :normal :immed :myopex {
174
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
163 reg <- src
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
164 rm <- dst
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
165 base <- if: (src isInteger?) {
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
166 reg <- fakesrc
175
20b6041a8b23 Small refactor in x86 module. Added a few more instructions.
Mike Pavone <pavone@retrodev.com>
parents: 174
diff changeset
167 (size_bit: immed size) | (mod_rm: (opex: myopex) dst withTail: (int_op: src size))
174
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
168 } else: {
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
169 if: (src register?) {
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
170 (size_bit: normal size) | (mod_rm: src dst)
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
171 } else: {
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
172 reg <- dst
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
173 rm <- src
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
174 (size_bit: normal or 0x02u8 size) | (mod_rm: dst src)
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
175 }
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
176 }
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
177 prefix: reg rm size withInstruction: base
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
178 }
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
179
175
20b6041a8b23 Small refactor in x86 module. Added a few more instructions.
Mike Pavone <pavone@retrodev.com>
parents: 174
diff changeset
180 op:withCode:withImmed:withImmedRax:withOpEx:withByteExtend <- :src dst size :normal :immed :immedRax :myopex :byteExt {
20b6041a8b23 Small refactor in x86 module. Added a few more instructions.
Mike Pavone <pavone@retrodev.com>
parents: 174
diff changeset
181 reg <- src
20b6041a8b23 Small refactor in x86 module. Added a few more instructions.
Mike Pavone <pavone@retrodev.com>
parents: 174
diff changeset
182 rm <- dst
20b6041a8b23 Small refactor in x86 module. Added a few more instructions.
Mike Pavone <pavone@retrodev.com>
parents: 174
diff changeset
183 if: (src isInteger?) {
20b6041a8b23 Small refactor in x86 module. Added a few more instructions.
Mike Pavone <pavone@retrodev.com>
parents: 174
diff changeset
184 reg <- fakesrc
20b6041a8b23 Small refactor in x86 module. Added a few more instructions.
Mike Pavone <pavone@retrodev.com>
parents: 174
diff changeset
185 base <- if: size > byte && (((src signed?) && src < 128 && src >= -128) || ((not: (src signed?)) && src < 256)) {
20b6041a8b23 Small refactor in x86 module. Added a few more instructions.
Mike Pavone <pavone@retrodev.com>
parents: 174
diff changeset
186 0x83u8 | (mod_rm: (opex: myopex) dst withTail: [(uint8: src)])
20b6041a8b23 Small refactor in x86 module. Added a few more instructions.
Mike Pavone <pavone@retrodev.com>
parents: 174
diff changeset
187 } else: {
20b6041a8b23 Small refactor in x86 module. Added a few more instructions.
Mike Pavone <pavone@retrodev.com>
parents: 174
diff changeset
188 if: dst = _rax {
20b6041a8b23 Small refactor in x86 module. Added a few more instructions.
Mike Pavone <pavone@retrodev.com>
parents: 174
diff changeset
189 (size_bit: immedRax size) | (int_op: src size)
20b6041a8b23 Small refactor in x86 module. Added a few more instructions.
Mike Pavone <pavone@retrodev.com>
parents: 174
diff changeset
190 } else: {
20b6041a8b23 Small refactor in x86 module. Added a few more instructions.
Mike Pavone <pavone@retrodev.com>
parents: 174
diff changeset
191 (size_bit: immed size) | (mod_rm: (opex: myopex) dst withTail: (int_op: src size))
20b6041a8b23 Small refactor in x86 module. Added a few more instructions.
Mike Pavone <pavone@retrodev.com>
parents: 174
diff changeset
192 }
20b6041a8b23 Small refactor in x86 module. Added a few more instructions.
Mike Pavone <pavone@retrodev.com>
parents: 174
diff changeset
193 }
20b6041a8b23 Small refactor in x86 module. Added a few more instructions.
Mike Pavone <pavone@retrodev.com>
parents: 174
diff changeset
194 prefix: reg rm size withInstruction: base
20b6041a8b23 Small refactor in x86 module. Added a few more instructions.
Mike Pavone <pavone@retrodev.com>
parents: 174
diff changeset
195 } else: {
20b6041a8b23 Small refactor in x86 module. Added a few more instructions.
Mike Pavone <pavone@retrodev.com>
parents: 174
diff changeset
196 op: src dst size withCode: normal withImmed: immed withOpEx: myopex
20b6041a8b23 Small refactor in x86 module. Added a few more instructions.
Mike Pavone <pavone@retrodev.com>
parents: 174
diff changeset
197 }
20b6041a8b23 Small refactor in x86 module. Added a few more instructions.
Mike Pavone <pavone@retrodev.com>
parents: 174
diff changeset
198
20b6041a8b23 Small refactor in x86 module. Added a few more instructions.
Mike Pavone <pavone@retrodev.com>
parents: 174
diff changeset
199 }
20b6041a8b23 Small refactor in x86 module. Added a few more instructions.
Mike Pavone <pavone@retrodev.com>
parents: 174
diff changeset
200
174
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
201 #{
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
202 rax <- { _rax }
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
203 rcx <- { _rcx }
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
204 rdx <- { _rdx }
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
205 rbx <- { _rbx }
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
206 rsp <- { _rsp }
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
207 rbp <- { _rbp }
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
208 rsi <- { _rsi }
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
209 rdi <- { _rdi }
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
210 r8 <- { _r8 }
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
211 r9 <- { _r9 }
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
212 r10 <- { _r10 }
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
213 r11 <- { _r11 }
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
214 r12 <- { _r12 }
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
215 r13 <- { _r13 }
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
216 r14 <- { _r14 }
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
217 r15 <- { _r15 }
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
218 ah <- { _ah }
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
219 ch <- { _ch }
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
220 dh <- { _dh }
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
221 bh <- { _bh }
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
222
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
223 b <- { byte }
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
224 w <- { word }
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
225 d <- { dword }
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
226 q <- { qword }
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
227
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
228 add <- :src dst size {
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
229 op: src dst size withCode: 0u8 withImmed: 0x80u8 withImmedRax: 0x04u8 withOpEx: 0u8 withByteExtend: 0x83u8
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
230 }
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
231
175
20b6041a8b23 Small refactor in x86 module. Added a few more instructions.
Mike Pavone <pavone@retrodev.com>
parents: 174
diff changeset
232 sub <- :src dst size {
20b6041a8b23 Small refactor in x86 module. Added a few more instructions.
Mike Pavone <pavone@retrodev.com>
parents: 174
diff changeset
233 op: src dst size withCode: 0x28u8 withImmed: 0x80u8 withImmedRax: 0x2Cu8 withOpEx: 5u8 withByteExtend: 0x83u8
20b6041a8b23 Small refactor in x86 module. Added a few more instructions.
Mike Pavone <pavone@retrodev.com>
parents: 174
diff changeset
234 }
20b6041a8b23 Small refactor in x86 module. Added a few more instructions.
Mike Pavone <pavone@retrodev.com>
parents: 174
diff changeset
235
20b6041a8b23 Small refactor in x86 module. Added a few more instructions.
Mike Pavone <pavone@retrodev.com>
parents: 174
diff changeset
236 mov <- :src dst size {
20b6041a8b23 Small refactor in x86 module. Added a few more instructions.
Mike Pavone <pavone@retrodev.com>
parents: 174
diff changeset
237 reg <- src
20b6041a8b23 Small refactor in x86 module. Added a few more instructions.
Mike Pavone <pavone@retrodev.com>
parents: 174
diff changeset
238 rm <- dst
20b6041a8b23 Small refactor in x86 module. Added a few more instructions.
Mike Pavone <pavone@retrodev.com>
parents: 174
diff changeset
239 if: (src isInteger?) && (dst register?) {
20b6041a8b23 Small refactor in x86 module. Added a few more instructions.
Mike Pavone <pavone@retrodev.com>
parents: 174
diff changeset
240 opval <- if: size = byte { 0xB0u8 } else: { 0xB8u8 }
20b6041a8b23 Small refactor in x86 module. Added a few more instructions.
Mike Pavone <pavone@retrodev.com>
parents: 174
diff changeset
241 base <- opval | (int_op64: src size)
20b6041a8b23 Small refactor in x86 module. Added a few more instructions.
Mike Pavone <pavone@retrodev.com>
parents: 174
diff changeset
242 prefix: fakesrc rm size withInstruction: base
20b6041a8b23 Small refactor in x86 module. Added a few more instructions.
Mike Pavone <pavone@retrodev.com>
parents: 174
diff changeset
243 } else: {
20b6041a8b23 Small refactor in x86 module. Added a few more instructions.
Mike Pavone <pavone@retrodev.com>
parents: 174
diff changeset
244 op: src dst size withCode: 0x88u8 withImmed: 0xC6u8 withOpEx: 0u8
20b6041a8b23 Small refactor in x86 module. Added a few more instructions.
Mike Pavone <pavone@retrodev.com>
parents: 174
diff changeset
245 }
20b6041a8b23 Small refactor in x86 module. Added a few more instructions.
Mike Pavone <pavone@retrodev.com>
parents: 174
diff changeset
246 }
20b6041a8b23 Small refactor in x86 module. Added a few more instructions.
Mike Pavone <pavone@retrodev.com>
parents: 174
diff changeset
247
20b6041a8b23 Small refactor in x86 module. Added a few more instructions.
Mike Pavone <pavone@retrodev.com>
parents: 174
diff changeset
248 ret <- { [ 0xC3u8 ] }
20b6041a8b23 Small refactor in x86 module. Added a few more instructions.
Mike Pavone <pavone@retrodev.com>
parents: 174
diff changeset
249
174
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
250
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
251 main <- {
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
252 print: ((add: rax r8 b) map: :el { hex: el })
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
253 print: "\n"
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
254 print: ((add: r9 rdx w) map: :el { hex: el })
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
255 print: "\n"
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
256 print: ((add: rax rbx q) map: :el { hex: el })
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
257 print: "\n"
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
258 print: ((add: 25 rax q) map: :el { hex: el })
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
259 print: "\n"
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
260 print: ((add: rcx rdx d) map: :el { hex: el })
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
261 print: "\n"
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
262 0
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
263 }
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
264 }
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
265 }