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comparison modules/x86.tp @ 198:3606a7cb3999

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Fix ireg upper, regSource returnAll and regSource needSaveForCall in x86 module
author Mike Pavone <pavone@retrodev.com>
date Tue, 27 Aug 2013 22:51:57 -0700
parents 7856f0916549
children 3b13ced3b562
comparison
equal deleted inserted replaced
197:1417f13f219c 198:3606a7cb3999
9 rm <- :tail { reg or 0xC0u8 | tail } 9 rm <- :tail { reg or 0xC0u8 | tail }
10 validforSize? <- :size { true } 10 validforSize? <- :size { true }
11 isInteger? <- { false } 11 isInteger? <- { false }
12 register? <- { true } 12 register? <- { true }
13 label? <- { false } 13 label? <- { false }
14 upper? <- { true } 14 upper? <- { false }
15 needsRex? <- { regnum >= 8u8 } 15 needsRex? <- { regnum >= 8u8 }
16 rexBitReg <- { 16 rexBitReg <- {
17 if: needsRex? { 17 if: needsRex? {
18 4u8 18 4u8
19 } else: { 19 } else: {
580 } 580 }
581 stackSize <- { _nextStackOff } 581 stackSize <- { _nextStackOff }
582 return <- :reg { 582 return <- :reg {
583 _used <- _used and (0xF xor (lshift: 1 by: (reg num))) 583 _used <- _used and (0xF xor (lshift: 1 by: (reg num)))
584 } 584 }
585 returnAll <- { _used = 0 } 585 returnAll <- { _used <- 0 }
586 needSaveProlog <- { 586 needSaveProlog <- {
587 retval <- #[] 587 retval <- #[]
588 foreach: _calleesave :idx reg { 588 foreach: _calleesave :idx reg {
589 bit <- lshift: 1 by: (reg num) 589 bit <- lshift: 1 by: (reg num)
590 if: (_usedAllTime and bit) != 0 { 590 if: (_usedAllTime and bit) != 0 {
593 } 593 }
594 retval 594 retval
595 } 595 }
596 needSaveForCall <- { 596 needSaveForCall <- {
597 retval <- #[] 597 retval <- #[]
598 foreach: #[_tempregs _argregs] :_ regs { 598 print: "Used: " . (hex: _used) . "\n"
599 foreach: #[(_tempregs) (_argregs)] :_ regs {
599 foreach: regs :_ reg { 600 foreach: regs :_ reg {
601 print: "Checking bit: " . (hex: (lshift: 1 by: (reg num))) . "\n"
600 if: (_used and (lshift: 1 by: (reg num))) != 0 { 602 if: (_used and (lshift: 1 by: (reg num))) != 0 {
603 print: (string: reg) . " needs saving for call\n"
601 retval append: reg 604 retval append: reg
602 } 605 }
603 } 606 }
604 } 607 }
605 retval 608 retval