view samples/iterfib.tp @ 193:4293c725394c

Mostly complete register allocation in il module with a register source in the x86 module
author Mike Pavone <pavone@retrodev.com>
date Mon, 26 Aug 2013 19:53:16 -0700
parents 3a169ebb3224
children
line wrap: on
line source

#{

fib <- :n {
  last <- 0
  cur <- 1
  counter <- 0
  while: { counter < n } do: {
  	counter <- counter + 1
  	tmp <- last
  	last <- cur
  	cur <- last + tmp
  }
  cur
}

main <- {
  print: (string: (fib: 30)) . "\n"
}

}