# HG changeset patch
# User Mike Pavone <pavone@retrodev.com>
# Date 1377209535 25200
# Node ID 20b6041a8b235935e3c7b3773d4fc8d634fbeabd
# Parent  8b5829372ad1d971b3dbaed202890efbfa605037
Small refactor in x86 module. Added a few more instructions.

diff -r 8b5829372ad1 -r 20b6041a8b23 modules/x86.tp
--- a/modules/x86.tp	Wed Aug 21 08:00:57 2013 -0700
+++ b/modules/x86.tp	Thu Aug 22 15:12:15 2013 -0700
@@ -106,8 +106,7 @@
 		mod_rm: reg rm withTail: []
 	}
 
-	int_op <- :value size {
-		tail <- []
+	int_op:withTail <- :value size :tail {
 		if: size >= dword {
 			tail <- (uint8: (value rshift: 16)) | (uint8: (value rshift: 24)) | tail
 		}
@@ -116,6 +115,17 @@
 		}
 		(uint8: value) | tail
 	}
+	int_op <- :value size {
+		int_op: value size withTail: []
+	}
+	//used for mov instructions that support 64-bit immediate operands/offsets
+	int_op64 <- :value size {
+		tail <- []
+		if: size = qword {
+			tail <- (uint8: (value rshift: 32)) | (uint8: (value rshift: 40)) | (uint8: (value rshift: 48)) | (uint8: (value rshift: 56)) | tail
+		}
+		int_op: value size withTail: tail
+	}
 
 	prefix:withInstruction <- :reg rm size :inst {
 		if: size = word {
@@ -149,20 +159,12 @@
 	_dh <- upper: 6u8
 	_bh <- upper: 7u8
 
-	op:withCode:withImmed:withImmedRax:withOpEx:withByteExtend <- :src dst size :normal :immed :immedRax :myopex :byteExt {
+	op:withCode:withImmed:withOpEx <- :src dst size :normal :immed :myopex {
 		reg <- src
 		rm <- dst
 		base <- if: (src isInteger?) {
 			reg <- fakesrc
-			if: size > byte && (((src signed?) && src < 128 && src >= -128) || ((not: (src signed?)) && src < 256)) {
-				0x83u8 | (mod_rm: (opex: myopex) dst withTail: [(uint8: src)])
-			} else: {
-				if: dst = _rax {
-					(size_bit: immedRax size) | (int_op: src size)
-				} else: {
-					(size_bit: immed size) | (mod_rm: (opex: myopex) dst withTail: (int_op: src size))
-				}
-			}
+			(size_bit: immed size) | (mod_rm: (opex: myopex) dst withTail: (int_op: src size))
 		} else: {
 			if: (src register?) {
 				(size_bit: normal size) | (mod_rm: src dst)
@@ -175,6 +177,27 @@
 		prefix: reg rm size withInstruction: base
 	}
 
+	op:withCode:withImmed:withImmedRax:withOpEx:withByteExtend <- :src dst size :normal :immed :immedRax :myopex :byteExt {
+		reg <- src
+		rm <- dst
+		if: (src isInteger?) {
+			reg <- fakesrc
+			base <- if: size > byte && (((src signed?) && src < 128 && src >= -128) || ((not: (src signed?)) && src < 256)) {
+				0x83u8 | (mod_rm: (opex: myopex) dst withTail: [(uint8: src)])
+			} else: {
+				if: dst = _rax {
+					(size_bit: immedRax size) | (int_op: src size)
+				} else: {
+					(size_bit: immed size) | (mod_rm: (opex: myopex) dst withTail: (int_op: src size))
+				}
+			}
+			prefix: reg rm size withInstruction: base
+		} else: {
+			op: src dst size withCode: normal withImmed: immed withOpEx: myopex
+		}
+
+	}
+
 	#{
 		rax <- { _rax }
 		rcx <- { _rcx }
@@ -206,6 +229,24 @@
 			op: src dst size withCode: 0u8 withImmed: 0x80u8 withImmedRax: 0x04u8 withOpEx: 0u8 withByteExtend: 0x83u8
 		}
 
+		sub <- :src dst size {
+			op: src dst size withCode: 0x28u8 withImmed: 0x80u8 withImmedRax: 0x2Cu8 withOpEx: 5u8 withByteExtend: 0x83u8
+		}
+
+		mov <- :src dst size {
+			reg <- src
+			rm <- dst
+			if: (src isInteger?) && (dst register?) {
+				opval <- if: size = byte { 0xB0u8 } else: { 0xB8u8 }
+				base <- opval | (int_op64: src size)
+				prefix: fakesrc rm size withInstruction: base
+			} else: {
+				op: src dst size withCode: 0x88u8 withImmed: 0xC6u8 withOpEx: 0u8
+			}
+		}
+
+		ret <- { [ 0xC3u8 ] }
+
 
 		main <- {
 			print: ((add: rax r8 b) map: :el { hex: el })