# HG changeset patch
# User Mike Pavone <pavone@retrodev.com>
# Date 1377574940 25200
# Node ID 30bed95cbb181dd829fc28cb087c7db4a05547c7
# Parent  4293c725394c68516c2aeeede75d24a4dc17a5b1
Apply register assignments in il module

diff -r 4293c725394c -r 30bed95cbb18 modules/il.tp
--- a/modules/il.tp	Mon Aug 26 19:53:16 2013 -0700
+++ b/modules/il.tp	Mon Aug 26 20:42:20 2013 -0700
@@ -55,6 +55,14 @@
 				_inb recordUsage: tracker at: 0 | address withSize: _size
 				_out recordUsage: tracker at: 1 | address withSize: _size
 			}
+			assignRegs:withSource <- :assignments :regSrc {
+				newa <- if: (not: (_ina isInteger?)) {
+					_ina assign: assignments withSource: regSrc
+				} else: { _ina }
+				newb <- _inb assign: assignments withSource: regSrc
+				newout <- _out assign: assignments withSource: regSrc
+				op3: _opcode a: newa b: newb out: newout size: _size
+			}
 		}
 	}
 	op2:in:out:size <- :_opcode :_in :_out :_size {
@@ -72,6 +80,13 @@
 				}
 				_out recordUsage: tracker at: 1 | address withSize: _size
 			}
+			assignRegs:withSource <- :assignments :regSrc {
+				newin <- if: (not: (_in isInteger?)) {
+					_in assign: assignments withSource: regSrc
+				} else: { _in }
+				newout <- _out assign: assignments withSource: regSrc
+				op2: _opcode in: newin out: newout size: _size
+			}
 		}
 	}
 	op1:arg:size <- :_opcode :_arg :_size {
@@ -87,6 +102,12 @@
 					_arg recordUsage: tracker at: address withSize: _size
 				}
 			}
+			assignRegs:withSource <- :assignments :regSrc {
+				newarg <- if: (not: (_arg isInteger?)) {
+					_arg assign: assignments withSource: regSrc
+				} else: { _arg }
+				op1: _opcode arg: newarg size: _size
+			}
 		}
 	}
 
@@ -135,6 +156,9 @@
 		recordUsage:at:withSize <- :tracker :address :size {
 			//TODO: Figure out what tracking is necessary here
 		}
+		assign:withSource <- :assignments :regSrc {
+			regSrc allocRet
+		}
 	}
 
 	_condnames <- #[
@@ -206,6 +230,9 @@
 				recordUsage:at:withSize <- :tracker :address :size {
 					tracker reg: self usedAt: address withSize: size
 				}
+				assign:withSource <- :assignments :regSrc {
+					assignments get: self
+				}
 			}
 		}
 		arg <- :num {
@@ -225,6 +252,9 @@
 				recordUsage:at:withSize <- :tracker :address :size {
 					tracker arg: self usedAt: address withSize: size
 				}
+				assign:withSource <- :assignments :regSrc {
+					regSrc allocArg: num
+				}
 			}
 		}
 		retr <- { _retr }
@@ -318,6 +348,19 @@
 						arg recordUsage: tracker at: address withSize: q
 					}
 				}
+				assignRegs:withSource <- :assignments :regSrc {
+					newtarget <- if: (_target isString?) { _target } else: {
+						_target assign: assignments withSource: regSrc
+					}
+					newargs <- _args map: :arg {
+						if: (arg isInteger?) { arg } else: {
+							arg assign: assignments withSource: regSrc
+						}
+					}
+					//TODO: Save caller-save regs if necessary
+					//TODO: Add instructions for moving arguments to proper regs/stack locations
+					call: newtarget withArgs: newargs
+				}
 			}
 		}
 
@@ -343,6 +386,12 @@
 						inst recordUsage: tracker at: idx | address
 					}
 				}
+				assignRegs:withSource <- :assignments :regSrc {
+					newskip <- _toskip map: :inst {
+						inst assignRegs: assignments withSource: regSrc
+					}
+					skipIf: _cond newskip
+				}
 			}
 		}
 
@@ -474,6 +523,11 @@
 			foreach: _assignments :reg assign {
 				print: (string: reg) . " = " . assign . "\n"
 			}
+
+			//TODO: Save callee saved regs
+			map: instarr :inst {
+				inst assignRegs: _assignments withSource: regSrc
+			}
 		}
 
 		//used to convert IL to a format suitable for a 2-operand architecture
@@ -522,8 +576,12 @@
 				print: (string: inst) . "\n"
 			}
 			print: "\n\nUsage:\n\n"
-			allocRegs: fib withSource: (x86 regSource)
-			fib2 <- to2Op: fib
+			fiba <- allocRegs: fib withSource: (x86 regSource)
+			print: "\n\nAFter Assignment:\n\n"
+			foreach: fiba :idx inst {
+				print: (string: inst) . "\n"
+			}
+			fib2 <- to2Op: fiba
 			print: "\n\n2-Operand:\n\n"
 			foreach: fib2 :idx inst {
 				print: (string: inst) . "\n"
diff -r 4293c725394c -r 30bed95cbb18 modules/x86.tp
--- a/modules/x86.tp	Mon Aug 26 19:53:16 2013 -0700
+++ b/modules/x86.tp	Mon Aug 26 20:42:20 2013 -0700
@@ -210,7 +210,9 @@
 	_tempregs <- #[
 		_r10
 		_r11
-		_rax
+		//TODO: Add rax back in once there's logic in il to properly
+		//allocate it for the instances in which it's live
+		//_rax
 	]
 
 
@@ -553,7 +555,7 @@
 					]
 				}
 				//allocated the return register
-				allocRet <- :size {
+				allocRet <- {
 					bit <- (lshift: 1 by: (_rax num))
 					_used <- _used or bit
 					_usedAllTime <- _usedAllTime or bit
@@ -565,6 +567,7 @@
 						bit <- (lshift: 1 by: (reg num))
 						_used <- _used or bit
 						_usedAllTime <- _usedAllTime or bit
+						reg
 					} else: {
 						il base: _rsp offset: _nextStackOff + 8 * (argnum - (_argregs length))
 					}